Philips TDA8766G-C1-S2, TDA8766G-C1, TDA8766G-C1-S1 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

TDA8766

10-bit high-speed 2.7 to 5.25 V analog-to-digital converter

Product specification

1996 Mar 20

Supersedes data of 1995 Mar 22

File under Integrated Circuits, IC02

Philips Semiconductors	Product specification

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

FEATURES

∙10-bit resolution

∙2.7 to 5.25 V operation

∙Sampling rate up to 20 MHz

∙DC sampling allowed

∙High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 1.0 MHz full-scale input at fclk = 20 MHz)

∙In range (IR) CMOS output

∙CMOS/TTL compatible digital inputs and outputs

∙External reference voltage regulator

∙Power dissipation only 53 mW (typical)

∙Low analog input capacitance, no buffer amplifier required

∙Standby mode

∙No sample-and-hold circuit required.

QUICK REFERENCE DATA

APPLICATIONS

High-speed analog-to-digital conversion for:

∙Video data digitizing

∙Camera

∙Camcorder

∙Radio communication.

GENERAL DESCRIPTION

The TDA8766 is a 10-bit high-speed analog-to-digital converter (ADC) for professional video and other applications. It converts with 2.7 to 5.25 V operation the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 20 MHz. All digital inputs and outputs are CMOS compatible. A standby mode allows reduction of the device power consumption down to 4 mW.

SYMBOL	PARAMETER		CONDITIONS	MIN.	TYP.	MAX.	UNIT
VDDA	analog supply voltage			2.7	3.3	5.25	V
VDDD1	digital supply voltage 1			2.7	3.3	5.25	V
VDDD2	digital supply voltage 2			2.7	3.3	5.25	V
VDDO	output stages supply voltage			2.5	3.3	5.25	V
IDDA	analog supply current			−	7.5	10	mA
IDDD	digital supply current			−	7.5	10	mA
IDDO	output stages supply current	fclk = 20	MHz; CL = 20 pF;	−	1	2	mA
		ramp input
INL	integral non-linearity	fclk = 20	MHz; ramp input	−	±1	±2	LSB
DNL	differential non-linearity	fclk = 20	MHz; ramp input	−	±0.25	±0.7	LSB
fclk(max)	maximum clock frequency			20	−	−	MHz
Ptot	total power dissipation	VDDA = VDDD = VDDO = 3.3 V		−	53	73	mW

ORDERING INFORMATION

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
TDA8766G	LQFP32	plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm	SOT401-1

1996 Mar 20

2

Philips Semiconductors	Product specification

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

BLOCK DIAGRAM

handbook, full pagewidth			VDDA		CLK	VDDD2		OE
			7		5	18		16
				CLOCK DRIVER					6		STDBY
						TDA8766
	VRT	15
									1	D9	MSB
									31	D8
									30	D7
			RLAD						29	D6
	V I	14						CMOS	28	D5
analog			ANALOG -TO - DIGITAL		LATCHES				27	D4	data outputs
voltage input				CONVERTER				OUTPUTS
	VRM								26	D3
		11							25	D2
									23	D1
									22	D0	LSB
	VRB	10							20		VDDO
					IN RANGE LATCH			CMOS	2		IR
								OUTPUT			output
									4		VDDD1
			9	19		21		3
			VSSA	VSSD2		VSSO		VSSD1	MLC853
		analog		digital		output	digital
		ground		ground 2		ground	ground 1

Fig.1 Block diagram.

1996 Mar 20

3

Philips Semiconductors	Product specification

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

PINNING

	SYMBOL		PIN	DESCRIPTION
	D9		1	data output; bit 9 (MSB)
	IR		2	in range data output
	VSSD1		3	digital ground 1
	VDDD1		4	digital supply voltage 1 (2.7 to 5.25 V)
	CLK		5	clock input
	STDBY		6	standby mode input
	VDDA		7	analog supply voltage (2.7 to 5.25 V)
	n.c.		8	not connected
	VSSA		9	analog ground
	VRB		10	reference voltage BOTTOM input
	VRM		11	reference voltage MIDDLE
	n.c.		12	not connected
	n.c.		13	not connected
	VI		14	analog input voltage
	VRT		15	reference voltage TOP input
			16	output enable input
	OE
	n.c.		17	not connected

SYMBOL	PIN	DESCRIPTION
VDDD2	18	digital supply voltage 2 (2.7 to 5.25 V)
VSSD2	19	digital ground 2
VDDO	20	positive supply voltage for output
		stage (2.5 to 5.25 V)
VSSO	21	digital output ground
D0	22	data output; bit 0 (LSB)
D1	23	data output; bit 1
n.c.	24	not connected
D2	25	data output; bit 2
D3	26	data output; bit 3
D4	27	data output; bit 4
D5	28	data output; bit 5
D6	29	data output; bit 6
D7	30	data output; bit 7
D8	31	data output; bit 8
n.c.	32	not connected

index corner

D9 1

IR 2

VSSD1 3

VDDD1 4

CLK 5

STDBY 6

VDDA 7

n.c. 8

n.c.		D8		D7		D6		D5		D4		D3		D2
32		31		30		29		28		27		26		25

TDA8766

9

10

11

12

13

14

15

16

SSA

RB

RM

n.c.

n.c.

I

RT

OE

V

V

V

V

V

24 n.c.

23 D1

22 D0

21 VSSO

20 VDDO

19 VSSD2

18 VDDD2

17 n.c.

MLC854

Fig.2 Pin configuration.

1996 Mar 20

4

Philips Semiconductors	Product specification

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VDDA	analog supply voltage	note 1	−0.3	+7.0	V
VDDD1, VDDD2	digital supply voltages	note 1	−0.3	+7.0	V
VDDO	output stages supply voltage	note 1	−0.3	+7.0	V
VDD	supply voltage difference
	VDDA − VDDD		−1.0	+4.0	V
	VDDD − VDDO		−1.0	+4.0	V
	VDDA − VDDO		−1.0	+4.0	V
VI	input voltage	referenced to VSSA	−0.3	+7.0	V
Vclk(p-p)	AC input voltage for switching	referenced to VSSD	−	VDDD	V
	(peak-to-peak value)
IO	output current		−	10	mA
Tstg	storage temperature		−55	+150	°C
Tamb	operating ambient temperature		−20	+75	°C
Tj	junction temperature		−	+150	°C

Note

1. The supply voltages VDDA, VDDD and VDDO may have any value between −0.3 V and +7.0 V provided that the supply voltage differences VDD are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL	PARAMETER	VALUE	UNIT
Rth j-a	thermal resistance from junction to ambient in free air	90	K/W

1996 Mar 20

5

Philips Semiconductors	Product specification

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

CHARACTERISTICS

VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO short-circuited together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 to +70 °C; typical values measured at Tamb = 25 °C; unless otherwise specified.

SYMBOL			PARAMETER		CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supply
VDDA			analog supply voltage			2.7	3.3	5.25	V
VDDD1			digital supply voltage 1			2.7	3.3	5.25	V
VDDD2			digital supply voltage 2			2.7	3.3	5.25	V
VDDO			output stages supply voltage			2.5	3.3	5.25	V
VDD			voltage difference
			VDDA − VDDD			−0.2	−	+0.2	V
			VDDA − VDDO			−0.2	−	+3.0	V
			VDDD − VDDO			−0.2	−	+3.0	V
IDDA			analog supply current			−	7.5	10	mA
IDDD			digital supply current			−	7.5	10	mA
IDDO			output stages supply current	fclk = 20 MHz;		−	1	2	mA
				ramp input; CL = 20 pF
Inputs
CLOCK INPUT CLK (REFERENCED TO VSSD); see note 1
VIL			LOW level input voltage			0	−	0.3VDDD	V
VIH			HIGH level input voltage			0.7VDDD	−	VDDD	V
				VDDD ≤ 3.6 V		0.6VDDD	−	VDDD	V
IIL			LOW level input current	Vclk	= 0.3VDDD	−1	0	+1	μA
IIH			HIGH level input current	Vclk	= 0.7VDDD	−	−	5	μA
ZI			input impedance	fclk = 20 MHz		−	4	−	kΩ
CI			input capacitance	fclk = 20 MHz		−	3	−	pF
INPUTS			AND STDBY (REFERENCED TO VSSD); see Table 3
	OE
VIL			LOW level input voltage			0	−	0.3VDDD	V
VIH			HIGH level input voltage			0.7VDDD	−	VDDD	V
				VDDD ≤ 3.6 V		0.6VDDD	−	VDDD	V
IIL			LOW level input current	VIL = 0.3VDDD		−1	−	−	μA
IIH			HIGH level input current	VIH = 0.7VDDD		−	−	+1	μA
VI (ANALOG INPUT VOLTAGE REFERENCED TO VSSA)
IIL			LOW level input current	VI = VRB		−	0	−	μA
IIH			HIGH level input current	VI = VRT		−	35	−	μA
ZI			input impedance	fi = 1 MHz		−	5	−	kΩ
CI			input capacitance	fi = 1 MHz		−	8	−	pF

1996 Mar 20

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