Philips TDA8766G-C1-S2, TDA8766G-C1, TDA8766G-C1-S1 Datasheet
DATA SH EET
Product specification
Supersedes data of 1995 Mar 22
File under Integrated Circuits, IC02
1996 Mar 20
INTEGRATED CIRCUITS
TDA8766
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
1996 Mar 20 2
Philips Semiconductors Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
FEATURES
• 10-bit resolution
• 2.7 to 5.25 V operation
• Sampling rate up to 20 MHz
• DC sampling allowed
• High signal-to-noise ratio over a large analog input
frequency range (9.3 effective bits at 1.0 MHz full-scale
input at f
clk
= 20 MHz)
• In range (IR) CMOS output
• CMOS/TTL compatible digital inputs and outputs
• External reference voltage regulator
• Power dissipation only 53 mW (typical)
• Low analog input capacitance, no buffer amplifier
required
• Standby mode
• No sample-and-hold circuit required.
APPLICATIONS
High-speed analog-to-digital conversion for:
• Video data digitizing
• Camera
• Camcorder
• Radio communication.
GENERAL DESCRIPTION
The TDA8766 is a 10-bit high-speed analog-to-digital
converter (ADC) for professional video and other
applications. It converts with 2.7 to 5.25 V operation the
analog input signal into 10-bit binary-coded digital words at
a maximum sampling rate of 20 MHz. All digital inputs and
outputs are CMOS compatible. A standby mode allows
reduction of the device power consumption down to 4 mW.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DDA
analog supply voltage 2.7 3.3 5.25 V
V
DDD1
digital supply voltage 1 2.7 3.3 5.25 V
V
DDD2
digital supply voltage 2 2.7 3.3 5.25 V
V
DDO
output stages supply voltage 2.5 3.3 5.25 V
I
DDA
analog supply current − 7.5 10 mA
I
DDD
digital supply current − 7.5 10 mA
I
DDO
output stages supply current f
clk
= 20 MHz; CL= 20 pF;
ramp input
− 12mA
INL integral non-linearity f
clk
= 20 MHz; ramp input −±1±2 LSB
DNL differential non-linearity f
clk
= 20 MHz; ramp input −±0.25 ±0.7 LSB
f
clk(max)
maximum clock frequency 20 −−MHz
P
tot
total power dissipation V
DDA=VDDD=VDDO
= 3.3 V − 53 73 mW
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
TDA8766G LQFP32 plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm SOT401-1
1996 Mar 20 3
Philips Semiconductors Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
19
10
14
R
LAD
11
15
V
RB
V
SSA
V
SSD2
V
SSOVSSD1
V
RM
V
RT
V
I
18
V
DDD2
7
2
V
DDA
28
29
30
31
27 D4
D5
D6
D7
D8
26
25
1
6
D3
D2
23 D1
22
D0
D9
IN RANGE LATCH
CMOS
OUTPUTS
LATCHES
ANALOG -TO - DIGITAL
CONVERTER
CLOCK DRIVER
MLC853
CMOS
OUTPUT
5
CLK
16
OE
STDBY
TDA8766
20
V
DDO
9
analog
ground
digital
ground 2
321
output
ground
digital
ground 1
analog
voltage input
data outputs
LSB
MSB
4
V
DDD1
IR
output
1996 Mar 20 4
Philips Semiconductors Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
PINNING
SYMBOL PIN DESCRIPTION
D9 1 data output; bit 9 (MSB)
IR 2 in range data output
V
SSD1
3 digital ground 1
V
DDD1
4 digital supply voltage 1 (2.7 to 5.25 V)
CLK 5 clock input
STDBY 6 standby mode input
V
DDA
7 analog supply voltage (2.7 to 5.25 V)
n.c. 8 not connected
V
SSA
9 analog ground
V
RB
10 reference voltage BOTTOM input
V
RM
11 reference voltage MIDDLE
n.c. 12 not connected
n.c. 13 not connected
V
I
14 analog input voltage
V
RT
15 reference voltage TOP input
OE 16 output enable input
n.c. 17 not connected
V
DDD2
18 digital supply voltage 2 (2.7 to 5.25 V)
V
SSD2
19 digital ground 2
V
DDO
20 positive supply voltage for output
stage (2.5 to 5.25 V)
V
SSO
21 digital output ground
D0 22 data output; bit 0 (LSB)
D1 23 data output; bit 1
n.c. 24 not connected
D2 25 data output; bit 2
D3 26 data output; bit 3
D4 27 data output; bit 4
D5 28 data output; bit 5
D6 29 data output; bit 6
D7 30 data output; bit 7
D8 31 data output; bit 8
n.c. 32 not connected
SYMBOL PIN DESCRIPTION
Fig.2 Pin configuration.
handbook, full pagewidth
TDA8766
MLC854
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
index
corner
D9
IR
V
DDD1
V
SSD1
V
CLK
STDBY
DDA
V
DDD2
V
SSD2
V
DDO
V
SSO
n.c.
n.c.
D1
D0
n.c.
n.c.
D8
D7
D6
D5
D4
D3
D2
SSA
n.c.
n.c.
OE
V
RB
V
RM
V
I
V
RT
V
1996 Mar 20 5
Philips Semiconductors Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. The supply voltages V
DDA
, V
DDD
and V
DDO
may have any value between −0.3 V and +7.0 V provided that the supply
voltage differences ∆VDD are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DDA
analog supply voltage note 1 −0.3 +7.0 V
V
DDD1
, V
DDD2
digital supply voltages note 1 −0.3 +7.0 V
V
DDO
output stages supply voltage note 1 −0.3 +7.0 V
∆V
DD
supply voltage difference
V
DDA
− V
DDD
−1.0 +4.0 V
V
DDD
− V
DDO
−1.0 +4.0 V
V
DDA
− V
DDO
−1.0 +4.0 V
V
I
input voltage referenced to V
SSA
−0.3 +7.0 V
V
clk(p-p)
AC input voltage for switching
(peak-to-peak value)
referenced to V
SSD
− V
DDD
V
I
O
output current − 10 mA
T
stg
storage temperature −55 +150 °C
T
amb
operating ambient temperature −20 +75 °C
T
j
junction temperature − +150 °C
SYMBOL PARAMETER VALUE UNIT
R
th j-a
thermal resistance from junction to ambient in free air 90 K/W
1996 Mar 20 6
Philips Semiconductors Product specification
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
TDA8766
CHARACTERISTICS
V
DDA=V7
to V9= 3.3 V; V
DDD=V4
to V3=V18to V19= 3.3 V; V
DDO=V20
to V21= 3.3 V; V
SSA,VSSD
and V
SSO
short-circuited together; V
i(p-p)
= 1.83 V; CL= 20 pF; T
amb
=0to+70°C; typical values measured at T
amb
=25°C;
unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply
V
DDA
analog supply voltage 2.7 3.3 5.25 V
V
DDD1
digital supply voltage 1 2.7 3.3 5.25 V
V
DDD2
digital supply voltage 2 2.7 3.3 5.25 V
V
DDO
output stages supply voltage 2.5 3.3 5.25 V
∆V
DD
voltage difference
V
DDA
− V
DDD
−0.2 − +0.2 V
V
DDA
− V
DDO
−0.2 − +3.0 V
V
DDD
− V
DDO
−0.2 − +3.0 V
I
DDA
analog supply current − 7.5 10 mA
I
DDD
digital supply current − 7.5 10 mA
I
DDO
output stages supply current f
clk
= 20 MHz;
ramp input; CL=20pF
− 12 mA
Inputs
C
LOCK INPUT CLK (REFERENCED TO V
SSD
); see note 1
V
IL
LOW level input voltage 0 − 0.3V
DDD
V
V
IH
HIGH level input voltage 0.7V
DDD
− V
DDD
V
V
DDD
≤ 3.6 V 0.6V
DDD
− V
DDD
V
I
IL
LOW level input current V
clk
= 0.3V
DDD
−10+1µA
I
IH
HIGH level input current V
clk
= 0.7V
DDD
−−5µA
Z
I
input impedance f
clk
= 20 MHz − 4 − kΩ
C
I
input capacitance f
clk
= 20 MHz − 3 − pF
INPUTS OE AND STDBY (REFERENCED TO V
SSD
); see Table 3
V
IL
LOW level input voltage 0 − 0.3V
DDD
V
V
IH
HIGH level input voltage 0.7V
DDD
− V
DDD
V
V
DDD
≤ 3.6 V 0.6V
DDD
− V
DDD
V
I
IL
LOW level input current VIL= 0.3V
DDD
−1 −− µA
I
IH
HIGH level input current VIH= 0.7V
DDD
−−+1 µA
VI(ANALOG INPUT VOLTAGE REFERENCED TO V
SSA
)
I
IL
LOW level input current VI=V
RB
− 0 −µA
I
IH
HIGH level input current VI=V
RT
− 35 −µA
Z
I
input impedance fi= 1 MHz − 5 − kΩ
C
I
input capacitance fi= 1 MHz − 8 − pF
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