Philips TDA8766 Service Manual

INTEGRATED CIRCUITS

DATA SH EET

TDA8766

10-bit high-speed 2.7 to 5.25 V analog-to-digital converter

Product speciﬁcation Supersedes data of 1995 Mar 22 File under Integrated Circuits, IC02

1996 Mar 20

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V analog-to-digital converter

FEATURES

• 10-bit resolution

• 2.7 to 5.25 V operation

• Sampling rate up to 20 MHz

• DC sampling allowed

• High signal-to-noise ratio over a large analog input

frequency range (9.3 effective bits at 1.0 MHz full-scale input at f

• In range (IR) CMOS output

• CMOS/TTL compatible digital inputs and outputs

• External reference voltage regulator

• Power dissipation only 53 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• Standby mode

• No sample-and-hold circuit required.

= 20 MHz)

clk

TDA8766

APPLICATIONS

High-speed analog-to-digital conversion for:

• Video data digitizing

• Camera

• Camcorder

• Radio communication.

GENERAL DESCRIPTION

The TDA8766 is a 10-bit high-speed analog-to-digital converter (ADC) for professional video and other applications. It converts with 2.7 to 5.25 V operation the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 20 MHz. All digital inputs and outputs are CMOS compatible. A standby mode allows reduction of the device power consumption down to 4 mW.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V V V V I

DDA

I

DDD

I

DDO

DDA DDD1 DDD2 DDO

analog supply voltage 2.7 3.3 5.25 V digital supply voltage 1 2.7 3.3 5.25 V digital supply voltage 2 2.7 3.3 5.25 V output stages supply voltage 2.5 3.3 5.25 V analog supply current − 7.5 10 mA digital supply current − 7.5 10 mA output stages supply current f

= 20 MHz; CL= 20 pF;

clk

− 12mA

ramp input INL integral non-linearity f DNL differential non-linearity f f

clk(max)

P

tot

maximum clock frequency 20 −−MHz total power dissipation V

= 20 MHz; ramp input −±1±2 LSB

clk

= 20 MHz; ramp input −±0.25 ±0.7 LSB

clk

DDA=VDDD=VDDO

= 3.3 V − 53 73 mW

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8766G LQFP32 plastic low profile quad flat package; 32 leads; body 5 × 5 × 1.4 mm SOT401-1

1996 Mar 20 2

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V analog-to-digital converter

BLOCK DIAGRAM

handbook, full pagewidth

analog

voltage input

V

RT

V

RM

V

DDA

7

15

R

LAD

I

14

11

ANALOG -TO - DIGITAL

CONVERTER

CLK

5

CLOCK DRIVER

LATCHES

V

DDD2

18

TDA8766

OE 16

CMOS

OUTPUTS

6

1

D9 D8

31

D7

30

D6

29

D5

28 27 D4 26

D3

25

D2 23 D1 22

D0

TDA8766

STDBY

MSB

data outputs

LSB

V

10

RB

CMOS

OUTPUT

321

SSOVSSD1

digital

ground 1

9

V

analog ground

SSA

19 V

digital

ground 2

SSD2

IN RANGE LATCH

V

output

ground

20

MLC853

V

DDO

IR

2

4

output

V

DDD1

Fig.1 Block diagram.

1996 Mar 20 3

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V analog-to-digital converter

PINNING

SYMBOL PIN DESCRIPTION

D9 1 data output; bit 9 (MSB) IR 2 in range data output V

SSD1

V

DDD1

CLK 5 clock input STDBY 6 standby mode input V

DDA

n.c. 8 not connected V

SSA

V

RB

V

RM

n.c. 12 not connected n.c. 13 not connected V

I

V

RT

OE 16 output enable input n.c. 17 not connected

3 digital ground 1 4 digital supply voltage 1 (2.7 to 5.25 V)

7 analog supply voltage (2.7 to 5.25 V)

9 analog ground 10 reference voltage BOTTOM input 11 reference voltage MIDDLE

14 analog input voltage 15 reference voltage TOP input

TDA8766

SYMBOL PIN DESCRIPTION

V

DDD2

V

SSD2

V

DDO

V

SSO

D0 22 data output; bit 0 (LSB) D1 23 data output; bit 1 n.c. 24 not connected D2 25 data output; bit 2 D3 26 data output; bit 3 D4 27 data output; bit 4 D5 28 data output; bit 5 D6 29 data output; bit 6 D7 30 data output; bit 7 D8 31 data output; bit 8 n.c. 32 not connected

18 digital supply voltage 2 (2.7 to 5.25 V) 19 digital ground 2 20 positive supply voltage for output

stage (2.5 to 5.25 V)

21 digital output ground

handbook, full pagewidth

index

corner

D9

V

SSD1

V

DDD1

CLK

STDBY

V

DDA

n.c.

D8

D7

D6

D5

D4

D3

D2

32

31

30

29

28

27

26

25

1 2

IR

3 4

TDA8766

5 6 7 8

9

10

11

12

13

14

15

16

RT

OE

V

SSA

V

I

RB

RM

V

n.c.

V

n.c.

V

24 23 22 21 20 19 18 17

MLC854

n.c. D1 D0

V

SSO

V

DDO

V

SSD2

V

DDD2

n.c.

Fig.2 Pin configuration.

1996 Mar 20 4

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDA

V

DDD1

V

DDO

∆V

V

I

V

clk(p-p)

I

O

T

stg

T

amb

T

j

DD

, V

DDD2

analog supply voltage note 1 −0.3 +7.0 V digital supply voltages note 1 −0.3 +7.0 V output stages supply voltage note 1 −0.3 +7.0 V supply voltage difference

− V

V V V

DDA DDD DDA

− V

DDD DDO DDO

input voltage referenced to V AC input voltage for switching

referenced to V

SSA SSD

−1.0 +4.0 V

−0.3 +7.0 V

− V

DDD

(peak-to-peak value) output current − 10 mA storage temperature −55 +150 °C operating ambient temperature −20 +75 °C junction temperature − +150 °C

V

Note

1. The supply voltages V

DDA

, V

DDD

and V

may have any value between −0.3 V and +7.0 V provided that the supply

DDO

voltage differences ∆VDD are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 90 K/W

1996 Mar 20 5

Philips Semiconductors Product speciﬁcation

10-bit high-speed 2.7 to 5.25 V

TDA8766

analog-to-digital converter

CHARACTERISTICS

V

DDA=V7

short-circuited together; V unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DDA

V

DDD1

V

DDD2

V

DDO

∆V

I

DDA

I

DDD

I

DDO

DD

to V9= 3.3 V; V

DDD=V4

i(p-p)

to V3=V18to V19= 3.3 V; V

= 1.83 V; CL= 20 pF; T

DDO=V20

=0to+70°C; typical values measured at T

amb

to V21= 3.3 V; V

SSA,VSSD

and V

amb

SSO

=25°C;

analog supply voltage 2.7 3.3 5.25 V digital supply voltage 1 2.7 3.3 5.25 V digital supply voltage 2 2.7 3.3 5.25 V output stages supply voltage 2.5 3.3 5.25 V voltage difference

V V V

DDA DDA DDD

− V

DDD DDO DDO

−0.2 − +0.2 V

−0.2 − +3.0 V

analog supply current − 7.5 10 mA digital supply current − 7.5 10 mA output stages supply current f

= 20 MHz;

clk

− 12 mA

ramp input; CL=20pF

Inputs

C

LOCK INPUT CLK (REFERENCED TO V

V

IL

V

IH

I

IL

I

IH

Z

I

C

I

LOW level input voltage 0 − 0.3V HIGH level input voltage 0.7V

LOW level input current V HIGH level input current V input impedance f input capacitance f

); see note 1

SSD

INPUTS OE AND STDBY (REFERENCED TO V V

IL

V

IH

I

IL

I

IH

LOW level input voltage 0 − 0.3V HIGH level input voltage 0.7V

LOW level input current VIL= 0.3V

HIGH level input current VIH= 0.7V VI(ANALOG INPUT VOLTAGE REFERENCED TO V I

IL

I

IH

Z

I

C

I

LOW level input current VI=V

HIGH level input current VI=V

input impedance fi= 1 MHz − 5 − kΩ

input capacitance fi= 1 MHz − 8 − pF

); see Table 3

SSD

)

SSA

DDD

V

≤ 3.6 V 0.6V

DDD

= 0.3V

clk clk

= 20 MHz − 4 − kΩ

clk

= 20 MHz − 3 − pF

clk

V

DDD

= 0.7V

DDD

≤ 3.6 V 0.6V

DDD DDD

RB RT

DDD

−10+1µA

−−5µA

DDD DDD

−1 −− µA

−−+1 µA

− 0 −µA

− 35 −µA

− V

DDD DDD

DDD DDD DDD

V V V

1996 Mar 20 6