Philips TDA8764TS-8-C1, TDA8764TS-4-C1 Datasheet

DATA SH EET

Preliminary specification

1999 Jan 12

INTEGRATED CIRCUITS

TDA8764

10-bit high-speed low-power ADC
with internal reference regulator

1999 Jan 12 2

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

FEATURES

• 10-bit resolution (binary or gray code)

• Sampling rate up to 40 MHz (/4 version)

Sampling rate up to 80 MHz (/8 version)

• DC sampling allowed

• One clock cycle conversion only

• High signal-to-noise ratio over a large analog input

frequency range (9.5 effective bits at 5 MHz; full-scale
input at f

clk

= 40 MHz)

• No missing codes guaranteed

• In-Range (IR) CMOS output

• TTL and CMOS levels compatible digital inputs

• 2.7 to 3.6 V CMOS digital outputs

• Low-level AC clock input signal allowed

• Internal reference voltage regulator

• Power dissipation only 250 mW (typical for /4 version)

Power dissipation only 375 mW (typical for /8 version)

• Low analog input capacitance, no buffer amplifier
required

• No sample-and-hold circuit required.

APPLICATIONS

High-speed analog-to-digital conversion for:

• Video data digitizing

• Radar pulse analysis

• Transient signal analysis

• High energy physics research

•Σ∆ modulators

• Medical imaging.

GENERAL DESCRIPTION

The TDA8764 is a 10-bit high-speed low-power
Analog-to-Digital Converter (ADC) for professional video
and other applications. It converts the analog input signal
into 10-bit binary or gray coded digital words at a maximum
sampling rate of 40 MHz (/4 version) and 80 MHz
(/8 version). All digital inputs and outputs are TTL
compatible, although a low-level sine wave clock input
signal is allowed.

The device includes an internal voltage reference
regulator.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

SAMPLING

FREQUENCY (MHz)

NAME DESCRIPTION VERSION

TDA8764TS/4 SSOP28 plastic shrink small outline package; 28 leads;

body width 5.3 mm

SOT341-1 40
TDA8764TS/8 80
TDA8764HL/4 LQFP32 plastic low profile quad flat package; 32 leads;

body 5 × 5 × 1.4 mm

SOT401-1 40
TDA8764HL/8 80

1999 Jan 12 3

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 2.7 3.3 3.6 V

I

CCA

analog supply current

TDA8764TS/4; TDA8764HL/4 − 25 tbf mA
TDA8764TS/8; TDA8764HL/8 − 45 tbf mA

I

CCD

digital supply current

TDA8764TS/4; TDA8764HL/4 − 25 tbf mA
TDA8764TS/8; TDA8764HL/8 − 30 tbf mA

I

CCO

output stages supply current

TDA8764TS/4; TDA8764HL/4 f

clk

= 40 MHz; ramp input − 0 tbf mA

TDA8764TS/8; TDA8764HL/8 f

clk

= 80 MHz; ramp input − 0 tbf mA

INL integral non-linearity

TDA8764TS/4; TDA8764HL/4 f

clk

= 40 MHz; ramp input −±0.8 tbf LSB

TDA8764TS/8; TDA8764HL/8 f

clk

= 80 MHz; ramp input −±0.8 tbf LSB

DNL differential non-linearity

TDA8764TS/4; TDA8764HL/4 f

clk

= 40 MHz; ramp input −±0.25 tbf LSB

TDA8764TS/8; TDA8764HL/8 f

clk

= 80 MHz; ramp input −±0.25 tbf LSB

f

clk(max)

maximum clock frequency

TDA8764TS/4; TDA8764HL/4 40 −−MHz
TDA8764TS/8; TDA8764HL/8 80 −−MHz

P

tot

total power dissipation

TDA8764TS/4; TDA8764HL/4 f

clk

= 40 MHz; ramp input − 250 tbf mW

TDA8764TS/8; TDA8764HL/8 f

clk

= 80 MHz; ramp input − 375 tbf mW

1999 Jan 12 4

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

DGND2

R

LAD

V

RB

V

RM

V

RT

V

I

V

CCD2

V

CCA

D4

D5

D6

D7

D8

D3
D2

D1
D0

D9

IN-RANGE LATCH

CMOS

OUTPUTS

LATCHES

ANALOG-TO-DIGITAL

CONVERTER

CLOCK DRIVER

REFERENCE

VOLTAGE

REGULATOR

FCE099

CMOS

OUTPUT

CLKDEC

GRAY

TC

OE

TDA8764

V

CCO

AGND

9 (15)

3 (7) 5 (10) 1 (5) 10

(16)

15 (21)11 (17)

analog ground digital ground digital ground

DGND1OGND

output ground

analog

voltage input

data outputs

LSB

MSB

V

CCD1

IR output

7 (13)

6 (12)

4 (8) 12 (18) 14 (20) 27 (3)

28 (4)

26 (2)

13 (19)

16 (22)

17 (23)

18 (24)

19 (25)

20 (26)

21 (27)

22 (28)

23 (29)

24 (30)

25 (31)

2 (6)

8 (14)

The pin numbers given in parenthesis refer to the LQFP32 package.

1999 Jan 12 5

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

PINNING

SYMBOL

PINS

DESCRIPTION

SSOP28 LQFP32

CLK 1 5 clock input
TC 2 6 twos complement input (input active LOW)
V

CCA

3 7 analog supply voltage (+5 V)
AGND 4 8 analog ground
DEC 5 10 decoupling input
V

RB

6 12 reference voltage BOTTOM input
V

RM

7 13 reference voltage MIDDLE input
V

I

8 14 analog input voltage
V

RT

9 15 reference voltage TOP input
OE 10 16 output enable input (input active LOW)
V

CCD2

11 17 digital supply voltage 2 (+5 V)
DGND2 12 18 digital ground 2
V

CCO

13 19 supply voltage for output stages (2.7 to 3.6 V)
OGND 14 20 output ground
GRAY 15 21 gray code input (input active HIGH)
D0 16 22 data output; bit 0 (LSB)
D1 17 23 data output; bit 1
D2 18 24 data output; bit 2
D3 19 25 data output; bit 3
D4 20 26 data output; bit 4
D5 21 27 data output; bit 5
D6 22 28 data output; bit 6
D7 23 29 data output; bit 7
D8 24 30 data output; bit 8
D9 25 31 data output; bit 9 (MSB)
IR 26 2 in-range data output
DGND1 27 3 digital ground 1
V

CCD1

28 4 digital supply voltage 1 (+5 V)
n.c. − 1, 9, 11 and 32 not connected

1999 Jan 12 6

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

Fig.2 Pin configuration (SSOP28).

handbook, halfpage

CLK

D9

D7
D6

D8

D5
D4
D3
D2
D1
D0

1
2
3
4
5
6
7
8

9
10
11
12
13

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

TDA8764TS

FCE100

IR

DGND1

V

CCD1

V

CCA

AGND

V

CCD2

DGND2

OGND

GRAY

V

CCO

DEC
V

RB

V

I

V

RT

V

RM

TC

OE

Fig.3 Pin configuration (LQFP32).

handbook, full pagewidth

TDA8764HL

FCE125

1
2
3
4
5
6
7
8

24
23
22
21
20
19
18
17

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

n.c.

IR

DGND1

V

CCD1

CLK

TC

V

CCA

AGND

D3

D4

D5

D6

D7

D8

D9

n.c.

V

CCD2

DGND2

OGND

D2

D0
GRAY

D1

V

CCO

n.c.

DEC

n.c.

V

RB

V

I

V

RT

OE

V

RM

1999 Jan 12 7

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages V

CCA

, V

CCD

and V

CCO

may have any value between −0.3 V and +7.0 V provided that the supply

voltage differences ∆VCC are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage note 1 −0.3 +7.0 V

V

CCD

digital supply voltage note 1 −0.3 +7.0 V

V

CCO

output stages supply voltage note 1 −0.3 +7.0 V

∆V

CC

supply voltage difference

V

CCA

− V

CCD

−1.0 +1.0 V

V

CCA

− V

CCO

−1.0 +4.0 V

V

CCD

− V

CCO

−1.0 +4.0 V

V

I

input voltage referenced to AGND −0.3 +7.0 V

V

i(sw)(p-p)

AC input voltage for switching (peak-to-peak value) referenced to DGND − V

CCD

V

I

O

output current − 10 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature −40 +85 °C

T

j

junction temperature − 150 °C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air

SSOP28 110 K/W
LQFP32 90 K/W

1999 Jan 12 8

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

CHARACTERISTICS

The characteristics given refer to the SSOP28 package. V

CCA=V3

to V4= 4.75 to 5.25 V;

V

CCD=V11

to V12and V28to V27= 4.75 to 5.25 V; V

CCO=V13

to V14= 2.7 to 3.6 V; AGND and DGND shorted

together; T

amb

= 0 to 70 °C; typical values measured at V

CCA=VCCD

= 5 V and V

CCO

= 3.3 V; CL= 10 pF and

T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD1

digital supply voltage 1 4.75 5.0 5.25 V

V

CCD2

digital supply voltage 2 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 2.7 3.3 3.6 V

∆V

CC

supply voltage difference

V

CCA

− V

CCD

−0.20 − +0.20 V

V

CCA

− V

CCO

−0.20 − +2.55 V

V

CCD

− V

CCO

−0.20 − +2.55 V

I

CCA

analog supply current

TDA8764TS/4; TDA8764HL/4 − 25 tbf mA
TDA8764TS/8; TDA8764HL/8 − 45 tbf mA

I

CCD

digital supply current

TDA8764TS/4; TDA8764HL/4 − 25 tbf mA
TDA8764TS/8; TDA8764HL/8 − 30 tbf mA

I

CCO

output stages supply current

TDA8764TS/4; TDA8764HL/4 f

clk

= 40 MHz; ramp input − 0 tbf mA

TDA8764TS/8; TDA8764HL/8 f

clk

= 80 MHz; ramp input − 0 tbf mA

Inputs

C

LOCK INPUT; CLK (REFERENCED TO DGND); note 1

V

IL

LOW-level input voltage 0 − 0.8 V

V

IH

HIGH-level input voltage 2 − V

CCD

V

I

IL

LOW-level input current V

CLK

= 0.8 V −10+1µA

I

IH

HIGH-level input current V

CLK

=2V − 210µA

C

i

input capacitance − 2 − pF
INPUTS OE, TC AND GRAY(REFERENCED TO DGND); see Tables 3 and 4
V

IL

LOW-level input voltage 0 − 0.8 V
V

IH

HIGH-level input voltage 2 − V

CCD

V

I

IL

LOW-level input current VIL= 0.8 V −1 −−µA
I

IH

HIGH-level input current VIH=2V −−1µA

1999 Jan 12 9

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

VI(ANALOG INPUT VOLTAGE REFERENCED TO AGND)
I

IL

LOW-level input current

TDA8764TS/4; TDA8764HL/4 V

I=VRB

− 0 −µA

TDA8764TS/8; TDA8764HL/8 V

I=VRB

− 0 −µA

I

IH

HIGH-level input current

TDA8764TS/4; TDA8764HL/4 V

I=VRT

− 45 −µA

TDA8764TS/8; TDA8764HL/8 V

I=VRT

− 85 −µA

Y

i

input admittance

TDA8764TS/4; TDA8764HL/4

fi= 5 MHz; note 2

input resistance − 70 − kΩ
input capacitance 3 5 7 pF

input admittance

TDA8764TS/8; TDA8764HL/8

f

i

= 5 MHz; note 2

input resistance − 45 − kΩ

input capacitance 3 5 7 pF
Reference voltages for the resistor ladder using the internal voltage regulator; see Table 1
V

RB

reference voltage BOTTOM tbf 1.3 tbf V

V

RT

reference voltage TOP tbf 3.7 tbf V

V

diff(ref)

differential reference voltage
VRT− V

RB

tbf 2.4 tbf V

TC

Vdiff

temperature coefficient of
differential reference voltage

− tbf − mV/K

V

offset(B)

offset voltage BOTTOM note 3 − 161 − mV

V

offset(T)

offset voltage TOP note 3 − 161 − mV

V

I(p-p)

analog input voltage
(peak-to-peak value)

note 4 tbf 2.08 tbf V

Outputs

D

IGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND)

V

OL

LOW-level output voltage

TDA8764TS/4; TDA8764HL/4 I

OL

= 1 mA 0 − 0.5 V

TDA8764TS/8; TDA8764HL/8 I

OL

= 2 mA 0 − 0.5 V

V

OH

HIGH-level output voltage

TDA8764TS/4; TDA8764HL/4 I

OH

= −1mA V

CCO

− 0.5 − V

CCO

V

TDA8764TS/8; TDA8764HL/8 I

OH

= −2mA V

CCO

− 0.5 − V

CCO

V

I

OZ

output current in 3-state mode 0.5 V < Vo<V

CCO

−20 − +20 µA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Jan 12 10

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

Switching characteristics

CLOCK INPUT; CLK; see Fig.5; note 1
f

clk(max)

maximum clock frequency

TDA8764TS/4; TDA8764HL/4 40 −−MHz

TDA8764TS/8; TDA8764HL/8 80 −−MHz
t

CPH

clock pulse width HIGH

TDA8764TS/4; TDA8764HL/4 7 −−ns

TDA8764TS/8; TDA8764HL/8 5 −−ns
t

CPL

clock pulse width LOW

TDA8764TS/4; TDA8764HL/4 7 −−ns

TDA8764TS/8; TDA8764HL/8 5 −−ns

Analog signal processing

L

INEARITY

INL integral non-linearity

TDA8764TS/4; TDA8764HL/4 f

clk

= 40 MHz; ramp input −±0.8 tbf LSB

TDA8764TS/8; TDA8764HL/8 f

clk

= 80 MHz; ramp input −±0.8 tbf LSB

DNL differential non-linearity

TDA8764TS/4; TDA8764HL/4 f

clk

= 40 MHz; ramp input −±0.25 tbf LSB

TDA8764TS/8; TDA8764HL/8 f

clk

= 80 MHz; ramp input −±0.25 tbf LSB

E

offset

offset error middle code −±1−LSB

E

G

gain error (from device to device)
using internal reference voltage

note 5 − tbf − %

BANDWIDTH (f

clk

=40MHZ)/4 VERSION;

B analog bandwidth full-scale sine wave; note 6 − 20 − MHz

75% full-scale sine wave;
note 6

− 30 − MHz

small signal at mid-scale;
V

I

= ±10 LSB at code 512;

note 6

− 350 − MHz

t

stLH

analog input settling time
LOW-to-HIGH

full-scale square wave;
see Fig.7 and note 7

− tbf tbf ns

t

stHL

analog input settling time
HIGH-to-LOW

full-scale square wave;
see Fig.7 and note 7

− tbf tbf ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Jan 12 11

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

BANDWIDTH (f

clk

=80MHZ)/8VERSION;

B analog bandwidth full-scale sine wave; note 6 − 40 − MHz

75% full-scale sine wave;
note 6

− 60 − MHz

small signal at mid-scale;
V

i

= ±10 LSB at code 512;

note 6

− 700 − MHz

t

stLH

analog input settling time
LOW-to-HIGH

full-scale square wave;
see Fig.7 and note 7

− tbf tbf ns

t

stHL

analog input settling time
HIGH-to-LOW

full-scale square wave;
see Fig.7 and note 7

− tbf tbf ns

HARMONICS (f

clk

=40MHZ)/4VERSION;

H

all(FS)

harmonics (full-scale);
all components

fi= 5 MHz

second harmonics −−70 tbf dBc

third harmonics −−90 tbf dBc
SFDR spurious free dynamic range f

i

= 5 MHz − tbf − dBc

THD total harmonic distortion f

i

= 5 MHz −−70 − dB

HARMONICS (f

clk

=80MHZ)/8 VERSION;

H

all(FS)

harmonics (full-scale);
all components

fi= 5 MHz

second harmonics −−71 tbf dBc

third harmonics −−87 tbf dBc
SFDR spurious free dynamic range f

i

= 5 MHz − tbf − dBc

THD total harmonic distortion f

i

= 5 MHz −−70 − dB
SIGNAL-TO-NOISE RATIO; note 8
SNR

(FS)

signal-to-noise ratio (full-scale) without harmonics;

fi= 5 MHz

f

clk

= 40 MHz; /4 version tbf 58 − dB

f

clk

= 80 MHz; /8 version tbf 58 − dB
EFFECTIVE BITS; note 8
EB effective bits

TDA8764TS/4; TDA8764HL/4

f

clk

= 40 MHz

f

i

= 5 MHz tbf 9.5 tbf bits

f

i

= 7.5 MHz tbf 9.2 tbf bits

f

i

= 10 MHz tbf 9.0 tbf bits

f

i

= 20 MHz tbf tbf tbf bits

effective bits
TDA8764TS/8; TDA8764HL/8

f

clk

= 80 MHz

f

i

= 5 MHz tbf 9.5 tbf bits

f

i

= 10 MHz tbf tbf tbf bits

f

i

= 20 MHz tbf tbf tbf bits

f

i

= 40 MHz tbf tbf tbf bits

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Jan 12 12

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

TWO-TONE; note 9
TTID two-tone intermodulation distortion f

clk

= 40 MHz − tbf − dB

f

clk

= 80 MHz − tbf − dB
BIT ERROR RATE
BER bit error rate fi= 5 MHz; Vi= ±16 LSB at

code 512

f

clk

= 40 MHz − 10

−13

− times/

sample

f

clk

= 80 MHz − 10

−13

− times/

sample

Timing (f

clk

= 40 MHz; CL= 10 pF) /4 version; see Fig.5 and note 10

t

ds

sampling delay time −−2ns

t

h

output hold time 5 −−ns

t

d

output delay time V

CCO

= 2.7 V tbf 12 tbf ns

V

CCO

= 3.3 V tbf 11 tbf ns

C

L

digital output load capacitance −−10 pF

SR slew rate V

CCO

= 2.7 V; CL=10pF −−tbf V/µs

Timing (f

clk

= 80 MHz; CL= 10 pF) /8 version; see Fig.5 and note 10

t

ds

sampling delay time −−2ns

t

h

output hold time 4 −−ns

t

d

output delay time V

CCO

= 2.7 V tbf 8 tbf ns

V

CCO

= 3.3 V tbf 7 tbf ns

C

L

digital output load capacitance −−10 pF

SR slew rate V

CCO

= 2.7 V; CL=10pF −−tbf V/µs

3-state output delay times (f

clk

= 40 MHz) /4 version; see Fig.6

t

dZH

enable HIGH − tbf tbf ns

t

dZL

enable LOW − tbf tbf ns

t

dHZ

disable HIGH − tbf tbf ns

t

dLZ

disable LOW − tbf tbf ns

3-state output delay times (f

clk

= 80 MHz) /8 version; see Fig.6

t

dZH

enable HIGH − tbf tbf ns

t

dZL

enable LOW − tbf tbf ns

t

dHZ

disable HIGH − tbf tbf ns

t

dLZ

disable LOW − tbf tbf ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Jan 12 13

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.

2. The input admittance is

3. Analog input voltages producing code 0 up to and including code 1023:
a) V

offset(B)

(offset voltage BOTTOM) is the difference between the analog input which produces data equal to 00

and the reference voltage BOTTOM (VRB) at T

amb

=25°C.

b) V

offset(T)

(offset voltage TOP) is the difference between reference voltage TOP (VRT) and the analog input which

produces data outputs equal to code 1023 at T

amb

=25°C.

4. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.4.

a) The current flowing into the resistor ladder is and the full-scale input range at the converter,

to cover code 0 to code 1023, is

b) Since R

L

, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio

will be kept reasonably constant from device to device. Consequently variation of the output

codes at a given input voltage depends mainly on the difference V

RT

− VRB and its variation with temperature and
supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the
matching between each of them is then optimized.

5.

6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, nor any significant attenuation are observed in the reconstructed signal.

7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square wave signal) in order to sample the signal and obtain correct output data.

8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: SINAD = EB × 6.02 + 1.76 dB.

9. Intermodulation measured relative to either tone with analog input frequencies of 5 and 5.1 MHz. The two input
signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.

10. Output data acquisition: the output data is available after the maximum delay time of t

d(max)

. For the 80 MHz version

it is recommended to have the lowest possible output load.

V

i

1

R

i

-----

Cijw+





=

I

L

V

RTVRB

–

R

OBRLROT

++

------------------------------------------

=

V

I

RLIL×

R

L

R

OBRLROT

++

------------------------------------------

V

RTVRB

–()0.866 V

RTVRB

–()×=×==

R

L

R

OBRLROT

++

------------------------------------------

E

G

V

1023V0

–()V

ip p–()

–

V

ip p–()

----------------------------------------------------------- -

100×=

1999 Jan 12 14

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

Table 1 Output coding and input voltage (typical values; referenced to AGND); binary and gray codes

Table 2 Output coding and input voltage (typical values; referenced to AGND); binary and twos complement codes

STEP V

i(p-p)

IR

BINARY OUTPUT BITS GRAY OUTPUT BITS

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

U/F <tbf 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000000
0 tbf 100000000000000000000
1 ... 100000000010000000001

... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...

... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...

1022... 111111111101000000001
1023tbf 111111111111000000000
O/F >tbf 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0000000

STEP V

i(p-p)

IR

BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

U/F <tbf 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0000000
0 tbf 100000000001000000000
1 ... 100000000011000000001

... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...

... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...

1022... 111111111100111111110
1023tbf 111111111110111111111
O/F >tbf 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1111111

Fig.4 Explanation of note 4.

handbook, halfpage

R

LAD

R

OT

V

RT

V

RM

V

RB

R

OB

code 1023

code 0

MGD281

I

L

R

L

1999 Jan 12 15

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

Table 3 Mode selection

Table 4 Mode selection

TC OE D9 TO D0 IR

X 1 high impedance high impedance
0 0 active; two complement active
1 0 active; binary active

GRAY OE D9 TO D0 IR

X 1 high impedance high impedance
0 0 active; binary active
1 0 active; gray active

Fig.5 Timing diagram.

handbook, full pagewidth

ds

t

sample N + 1

sample N

CLK

MBG916

sample N + 2

0 V

50%

V

CCO

0 V

50%

V

CCO

V

l

DATA
D0 to D9

t

d

t

h

CPH

t

CPL

t

DATA

N + 1

DATA

N

DATA

N - 1

DATA

N - 2

1999 Jan 12 16

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

handbook, full pagewidth

output

data

output

data

OE

50%

50%

50%

10%

90%

LOW

LOW

HIGH

HIGH

t

dZH

t

dZL

t

dHZ

V

CCD

t

dLZ

TDA8764

3.3 kΩ

S1

OE

V

CCD

15 pF

FCE101

t

dLZ

TEST S1

t

dZL

t

dHZ

t

dZH

V

CCD

V

CCD

DGND
DGND

Fig.6 Timing diagram and test conditions of 3-state output delay time.

fOE= 100kHz.

Fig.7 Analog input settling time diagram.

MBE566

50%

STLH

t

2 ns

code 0

code 1023

I

50%

0.5 ns

50%

2 ns

STHL

t

50%

0.5 ns

CLK

V

1999 Jan 12 17

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

INTERNAL PIN CONFIGURATIONS

Fig.8 CMOS data and in range outputs.

handbook, halfpage

MBG915

V

CCO

OGND

D9 to D0

IR

Fig.9 Analog inputs.

handbook, halfpage

MGC040 - 1

AGND

V

CCA

V

I

Fig.10 OE, GRAY and TC inputs.

handbook, halfpage

FCE102

V

CCO

OGND

OE
TC

GRAY

Fig.11 VRB, VRM and VRT.

handbook, halfpage

R

LAD

MBE558 - 1

V

RB

V

RM

AGND

V

RT

V

CCA

REGULATOR

DEC

1999 Jan 12 18

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

Fig.12 CLK input.

handbook, halfpage

FCE103

1.5 V

V

CCD

DGND

CLK

1999 Jan 12 19

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

APPLICATION INFORMATION

Fig.13 Application diagram (SSOP28).

The analog and digital supplies should be separated and well decoupled.
An application note is available which describes the design and the realization of a demonstration board

that uses TDA8764HL in an application environment.
(1) V

RB

, VRM and VRT are decoupled to AGND.

(2) Decoupling capacitor for supplies; it must be placed close to the device.

handbook, full pagewidth

28

27

26

25

24

23

22

21

20

19

18

17

TDA8764TS

DGND1

D3

D4

D5

D6

D7

D8

D9

D2

D1

D0

GRAY

1

2

3

4

5

6

7

8

9

10

11

12

CLK

AGND

DEC

V

RB

(1)

V

CCA

V

RT

(1)

V

RM

(1)

V

CCD2

DGND2

OGND

V

CCO

V

I

FCE104

16

15

13

14

1 nF

1 nF

1 nF

IR

OE

TC

V

CCD1

AGND

4.7 nF

AGND

100 nF

100 nF

AGND

AGND

(2)

100 nF

(2)

(2)

100 nF

(2)

1999 Jan 12 20

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

Fig.14 Application diagram (LQFP32).

The analog and digital supplies should be separated and well decoupled.
An application note is available which describes the design and the realization of a demonstration board

that uses TDA8764HL in an application environment.
(1) V

RB

, VRM and VRT are decoupled to AGND.

(2) Decoupling capacitor for supplies; it must be placed close to the device.

handbook, full pagewidth

FCE126

32

124
223
322
421
520
619
718
817

9

31103011291228132714261525

16

100 nF

(2)

100 nF

(2)

100 nF

(2)

100 nF

(2)

TDA8764HL

n.c.

IR

DGND1

V

CCD1

CLK

V

CCA

AGND

1 nF

(1)

AGND

1 nF

(1)

AGND

1 nF

(1)

AGND

4.7 nF

AGND

D3D4D5D6D7D8D9n.c.

V

CCD2

DGND2

OGND

D2

D0
GRAY

D1

V

CCO

n.c.

DEC

n.c. V

RB

VIV

RT

V

RM

TC

OE

1999 Jan 12 21

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

PACKAGE OUTLINES

UNIT A1A2A3b

p

cD

(1)E(1) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

10.4

10.0

5.4

5.2

0.65 1.25

7.9

7.6

0.9

0.7

1.1

0.7

8
0

o
o

0.13 0.10.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

1.03

0.63

SOT341-1 MO-150AH

93-09-08
95-02-04

X

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

(A )

3

A

114

28 15

0.25

y

pin 1 index

0 2.5 5 mm

scale

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

SOT341-1

A

max.

2.0

1999 Jan 12 22

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

0.2

UNIT

A

max.

A

1A2A3bp

cE

(1)

eH

E

LL

p

Zywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

1.60

0.15

0.05

1.5

1.3

0.25

0.27

0.17

0.18

0.12

5.1

4.9

0.5

7.15

6.85

1.0

0.95

0.55

7
0

o
o

0.12 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT401-1

95-12-19
97-08-04

D

(1) (1)(1)

5.1

4.9

H

D

7.15

6.85

E

Z

0.95

0.55

D

b

p

e

E

B

8

D

H

b

p

E

H

v M

B

D

Z

D

A

Z

E

e

v M

A

X

1

32

25

24

17

16

9

θ

A

1

A

L

p

detail X

L

(A )

3

A

2

y

w M

w M

0 2.5 5 mm

scale

LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm

SOT401-1

c

pin 1 index

1999 Jan 12 23

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Jan 12 24

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO not recommended

(5)

suitable

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1999 Jan 12 25

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

NOTES

1999 Jan 12 26

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

NOTES

1999 Jan 12 27

Philips Semiconductors Preliminary specification

10-bit high-speed low-power ADC with
internal reference regulator

TDA8764

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1999 SCA61
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands 295002/750/01/pp28 Date of release: 1999Jan 12 Document order number: 9397 750 04632