Philips TDA8755T-C1 Datasheet

DATA SH EET

Product specification
Supersedes data of June 1994
File under Integrated Circuits, IC02

1995 Mar 09

INTEGRATED CIRCUITS

Philips Semiconductors

TDA8755

YUV 8-bit video low-power
analog-to-digital interface

1995 Mar 09 2

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

TDA8755

FEATURES

• 8-bit resolution

• Sampling rate up to 20 MHz

• TTL compatible digital inputs

• 3-state TTL outputs

• U, V two's complement outputs

• Y binary output

• Power dissipation of 550 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• High signal-to-noise ratio over a large analog input
frequency range

• Track-and-hold included

• Clamp functions included

• UV multiplexed ADC

• 4:1:1 output data encoder

• Stable voltage regulator included.

APPLICATIONS

• High speed analog-to-digital conversion for video signal
digitizing

• 100 Hz improved definition TV (IDTV).

GENERAL DESCRIPTION

The TDA8755 is a bipolar 8-bit video low-power
analog-to-digital conversion (ADC) interface for YUV
signals. The device converts the YUV analog input signal
into 8-bit coded digital words in a 4 : 1 : 1 format at a
sampling rate of 20 MHz. The U/V signals are converted in
a multiplexed manner. All analog signal inputs are digitally
clamped and a fast precharge is provided for start-up.
All digital inputs and outputs are TTL compatible. Frame
synchronization is supported in a multiplexed manner.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current − 46 55 mA

I

CCD

digital supply current − 55 66 mA

I

CCO

output stages supply current − 912mA

INL DC integral non-linearity f

clk

= 2 MHz −±0.4 ±1 LSB

DNL DC differential non-linearity f

clk

= 2 MHz −±0.3 ±0.5 LSB
EB effective bits − 7.1 − bits
f

clk(max)

maximum clock frequency 20 −−MHz

P

tot

total power dissipation − 550 700 mW

TYPE NUMBER

PACKAGE

PINS PIN POSITION MATERIAL CODE

TDA8755T 32 SO32L plastic SOT287-1

1995 Mar 09 3

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

TDA8755

BLOCK DIAGRAM

handbook, full pagewidth

MLA734 - 1

CLAMPUCLAMP

V

DIGITAL

MULTIPLEXER

TRACK

AND

HOLD

TRACK

AND

HOLD

ANALOG

MULTIPLEXER

TRACK

AND

HOLD

8-BIT

ADC

COMPARATOR

128

U AND V

DATA

ENCODER

TTL

I / O

TIMING GENERATOR

SUPPLY AND REFERENCE

VOLTAGE REGULATOR

CLAMP

LOGIC

8

TRACK

AND

HOLD

8-BIT

ADC

COMPARATOR

16

8-BIT

PIPELINE

TTL

I / O

8

CLAMP

Y

12

9

INV

CLPV

CLPU

11

7

INU

CLP

CLPY

INY

15

5

3

6 322310188 1

V

CCA

V

CCD

V

CCO AGND DGND SDN n.c.

192021

22

17

14

16

CLK

CE

HREF

2

D'0

D'1

D'2

D'3

U

V

2

D0

D7

Y

24

31

8

REG1 REG2 REG3

2413

8

TDA8755

Fig.1 Block diagram.

1995 Mar 09 4

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

TDA8755

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
REG1 2 decoupling input (internal

stabilization loop decoupling)
INY 3 Y analog voltage input
REG2 4 decoupling input (internal

stabilization loop decoupling)
CLPY 5 Y clamp capacitor connection
V

CCA

6 analog positive supply voltage

(+5 V)
INU 7 U analog voltage input
SDN 8 stabilizer decoupling node and

analog reference voltage (+3.35 V)
INV 9 V analog voltage input
AGND 10 analog ground
CLPU 11 U clamp capacitor connection
CLPV 12 V clamp capacitor connection
REG3 13 decoupling input (internal

stabilization loop decoupling)
CE 14 chip enable input (TTL level input

active LOW)
CLP 15 clamp control input
HREF 16 horizontal reference signal
CLK 17 clock input
DGND 18 digital ground
D'0 19 V data output; bit 0 (n−1)
D'1 20 V data output; bit 1 (n)
D'2 21 U data output; bit 0 (n−1)
D'3 22 U data output; bit 1 (n)
V

CCO

23 positive supply voltage for output

stages (+5 V)
D0 24 Y data output; bit 0 (LSB)
D1 25 Y data output; bit 1
D2 26 Y data output; bit 2
D3 27 Y data output; bit 3
D4 28 Y data output; bit 4
D5 29 Y data output; bit 5
D6 30 Y data output; bit 6
D7 31 Y data output; bit 7 (MSB)
V

CCD

32 digital positive supply voltage (+5 V)

Fig.2 Pin configuration.

handbook, halfpage

1
2
3
4
5
6
7
8

9
10
11
12

13
14
15
16

32
31
30
29
28
27

17

18

19

20

21

22

23

24

25

26

TDA8755

n.c.

REG1

INY

REG2

CLPY

V

CCA

INU

SDN

INV

AGND

CLPU
CLPV
REG3

CE

CLP

HREF CLK

DGND

D'0

D'1

D'2

D'3

V

CCO

D0

D1

D2

D3

D4

D5

D6

D7

V

CCD

MLA728 - 1

1995 Mar 09 5

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

TDA8755

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC134).

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage −0.3 +7.0 V

V

CCD

digital supply voltage −0.3 +7.0 V

V

CCO

output stages supply voltage −0.3 +7.0 V

∆V

CC

supply voltage difference between V

CCA

and V

CCD

−1.0 +1.0 V

supply voltage difference between V

CCO

and V

CCD

−1.0 +1.0 V

supply voltage difference between V

CCA

and V

CCO

−1.0 +1.0 V

V

I

input voltage referenced to AGND − +5.0 V

V

clk(p-p)

AC input voltage for switching (peak-to-peak value) referenced to DGND − V

CCD

V

I

O

output current − +6 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature 0 +70 °C

T

j

junction temperature − +150 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 70 K/W

1995 Mar 09 6

Philips Semiconductors Product specification

YUV 8-bit video low-power
analog-to-digital interface

TDA8755

CHARACTERISTICS

V

CCA=V6

to V10= 4.75 to 5.25 V; V

CCD=V32

to V18= 4.75 to 5.25 V; V

CCO=V23

to V18= 4.75 to 5.25 V;

AGND and DGND shorted together; V

CCA

to V

CCD

= −0.25 to +0.25 V; V

CCO

to V

CCD

= −0.25 to +0.25 V;

V

CCA

to V

CCO

= −0.25 to +0.25 V; T

amb

= 0 to +70 °C; typical values measured at V

CCA=VCCD=VCCO

= 5 V and

T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current − 46 55 mA

I

CCD

digital supply current − 55 66 mA

I

CCO

output stages supply current − 912mA

Inputs

CLK (

PIN 17)

V

IL

LOW level input voltage 0 − 0.8 V

V

IH

HIGH level input voltage 2.0 − V

CCD

V

I

IL

LOW level input current V

clk

= 0.4 V −400 −−µA

I

IH

HIGH level input current V

clk

= 2.7 V −−100 µA

Z

I

input impedance f

clk

=20MHz − 4 − kΩ

C

I

input capacitance f

clk

=20MHz − 4.5 − pF
CE, CLP AND HREF (PINS 14 TO 16)
V

IL

LOW level input voltage 0 − 0.8 V

V

IH

HIGH level input voltage 2.0 − V

CCD

V

I

IL

LOW level input current V

clk

= 0.4 V −400 −−µA

I

IH

HIGH level input current V

clk

= 2.7 V −−100 µA
CLPY (PIN 5)
V

5

clamp voltage for 16 output code − 3.725 − V

I

5

clamp output current −±50 −µA
CLPU AND CLPV (PINS 11 AND 12)
V

11, 12

clamp voltage for 128 output code − 3.30 − V
I

11, 12

clamp output current −±50 −µA
INY (PIN 3)
V

I(p-p)

input voltage, full range

(peak-to-peak value)

fi= 4.43 MHz 0.93 1.0 1.07 V

Z

I

input impedance fi= 6 MHz − 30 − kΩ
C

I

input capacitance fi= 6 MHz − 1 − pF