Philips TDA8752BH-8-C5 Datasheet

DATA SH EET

Preliminary specification
Supersedes data of 1999 Nov 11
File under Integrated Circuits, IC02

2000 Jan 10

INTEGRATED CIRCUITS

TDA8752B

Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)

2000 Jan 10 2

Philips Semiconductors Preliminary specification

Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)

TDA8752B

FEATURES

• Triple 8-bit ADC

• Sampling rate up to 110 MHz

• IC controllablevia a serial interface, which can be either

I2C-bus or 3-wire, selected via a TTL input pin

• IC analog voltage input from 0.4 to 1.2 V (p-p) to
produce a full-scale ADC input of 1 V (p-p)

• 3 clamps for programming a clamping code between

−63.5 and +64 in steps of1⁄2LSB

• 3 controllable amplifiers: gain controlled via the serial

interface to produce a full scale resolution of1⁄2LSB
peak-to-peak

• Amplifier bandwidth of 250 MHz

• Low gain variation with temperature

• PLL, controllable via the serial interface to generate the

ADC clock, which can be locked to a line frequency of
15 to 280 kHz

• Integrated PLL divider

• Programmable phase clock adjustment cells

• Internal voltage regulators

• TTL compatible digital inputs and outputs

• Chip enable high-impedance ADC output

• Power-down mode

• Possibility to use up to four ICs in the same system,

using the I2C-bus interface, or more, using the 3-wire
serial interface

• 1.1 W power dissipation.

APPLICATIONS

• R, G and B high-speed digitizing

• LCD panels drive

• LCD projection systems

• VGA and higher resolutions

• Using two ICs in parallel, higher display resolution can

be obtained; 200 MHz pixel frequency.

GENERAL DESCRIPTION

The TDA8752B is a triple 8-bit ADC with controllable
amplifiers and clamps for the digitizing of large bandwidth
RGB signals.

The clamp level, the gain and all of the other settings are
controlled via a serial interface (either I2C-bus or 3-wire
serial bus, selected via a logic input).

The IC also includes a PLL that can be locked to the
horizontal line frequency and generates the ADC clock.
The PLL jitter is minimized for high resolution PC graphics
applications. An external clock can also be input to the
ADC.

It is possible to set the TDA8752B serial bus address
between four fixed values, in the event that several
TDA8752B ICs are used in a system, using the I2C-bus
interface (for example, two ICs used in an odd/even
configuration).

ORDERING INFORMATION

TYPE NUMBER

PACKAGE SAMPLING

FREQUENCY

(MHz)

NAME DESCRIPTION VERSION

TDA8752BH/8 QFP100 plastic quad flat package; 100 leads (lead length

1.95 mm); body 14 × 20 × 2.8 mm

SOT317-2 110

2000 Jan 10 3

Philips Semiconductors Preliminary specification

Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)

TDA8752B

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage for R, G and B channels 4.75 5.0 5.25 V

V

DDD

logic supply voltage for I2C-bus and 3-wire 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage for R, G and B channels 4.75 5.0 5.25 V

V

CCA(PLL)

analog PLL supply voltage 4.75 5.0 5.25 V

V

CCO(PLL)

output PLL supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current − 120 − mA

I

DDD

logic supply current for I2C-bus and 3-wire − 1.0 − mA

I

CCD

digital supply current − 40 − mA

I

CCO

output stages supply current f

CLK

= 110 MHz;

ramp input

− 26 − mA

I

CCA(PLL)

analog PLL supply current − 28 − mA

I

CCO(PLL)

output PLL supply current − 5 − mA

f

CLK

maximum clock frequency TDA8752B/8 110 −−MHz

f

ref(PLL)

PLL reference clock frequency 15 − 280 kHz

f

VCO

VCO output clock frequency 12 − 110 MHz

INL DC integral non linearity from analog input to

digital output; full-scale;
ramp input;
f

CLK

= 110 MHz

−±0.5 ±1.5 LSB

DNL DC differential non linearity from analog input to

digital output; full-scale;
ramp input;
f

CLK

= 110 MHz

−±0.5 ±1.0 LSB

∆G

amp

/T amplifier gain stability as a function of

temperature

V

ref

= 2.5 V with

100 ppm/°C maximum

−−200 ppm/°C

B amplifier bandwidth −3 dB; T

amb

=25°C 250 −−MHz

t

set

settling time of the ADC block plus AGC input signal settling

time < 1 ns; T

amb

=25°C

−−6ns

DR

PLL

PLL divider ratio 100 − 4095

P

tot

total power consumption f

CLK

= 110 MHz;

ramp input

− 1.1 − W

j

PLL(rms)

maximum PLL phase jitter (RMS value) f

ref

= 66.67 kHz;

f

CLK

= 110 MHz

− 0.67 − ns

2000 Jan 10 4

Philips Semiconductors Preliminary specification

Triple high-speed Analog-to-Digital

Converter 110 Msps (ADC)

TDA8752B

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BLOCK DIAGRAM

handbook, full pagewidth

FCE467

SERIAL

INTERFACE

I

2

C-BUS

OR

3-WIRE

I

2

C/3W

I

2

C-bus; 1-bit

(H level)

REGULATOR

PLL

PWDWN

CP

CZ

CKREF

COAST

INV

CKEXT

CKREFO

CKAO

CKBO

CKADCO

B0 to B7
BOR

R0 to R7

OE

G0 to G7

BBOT

BCLP

RBOT

RCLP

GBOT

GCLP

DEC2DEC1HSYNCn.c.

HSYNCI

ADD2

BIN

BGAINC

BAGC

GAGC

V

ref

RDEC

RIN

RGAINC

RAGC

GDEC

GIN

GGAINC

BDEC

ADD1

SEN
SCL
SDA

DIS

BLUE CHANNEL

GREEN CHANNEL

TDA8752B

RED CHANNEL

ADC

GOR

ROR

MUX

CLAMP

OUTPUTS

6

V

CCAR

11

V

CCAG

19

V

CCAB

27

V

DDD

40

AGNDG

21

V

CCOG

69

V

CCOB

59

V

CCOR

79

V

CCD

95

V

CCA(PLL)

99

V

CCO(PLL)

85

CLP

89

AGNDR

13

V

SSD

41

AGNDB

29

OGNDG

60

OGNDR

70

AGNDPLL

96

OGNDB

48

DGND

86

OGNDPLL

82

12
10

3

22
24

28
26

20
18

14
16

33

34

38

TDO
TCK

35

36

42
39
37

90

1, 5, 30, 31, 43 , 44
50, 51, 100

4 2 88 97 98

32

8

9
7

71 to 78

45

17
15

61 to 68

87

46

25
23

49, 52 to 58

47

93
94

92

80

91

84
83
81

Fig.1 Block diagram.

2000 Jan 10 5

Philips Semiconductors Preliminary specification

Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)

TDA8752B

handbook, full pagewidth

CLP RAGC CLKADC

R0 to R7

ROR

RBOT

ADC

AGC

MUX

1

CLAMP

CONTROL

REGISTER

OUTPUTS

ADC

D ≥ R

R

D

V

CCAR

DAC

DAC

RCLP

RIN

V

ref

V

P

8

8

8

8

7

REGISTER

FINE GAIN ADJUST

5

I2C-bus; 5 bits

(Fr)

I

2

C-bus; 8 bits

(Or)

REGISTER

COARSE GAIN ADJUST

HSYNCI

I

2

C-bus; 7 bits

(Cr)

I

2

C-BUS

SERIAL

RGAINC

1

OE

150

kΩ

3
kΩ

45
kΩ

FCE468

Fig.2 Red channel diagram.

2000 Jan 10 6

Philips Semiconductors Preliminary specification

Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)

TDA8752B

FCE465

PHASE

FREQUENCY

DETECTOR

I2C-bus; 5 bits
(Ip, Up, Do)

I

2

C-bus; 1 bit

(V level)

I

2

C-bus; 12 bits (Di)

I

2

C-bus;

1 bit (Ckb)

phase selector A
I

2

C-bus;

5 bits (Pa)

I

2

C-bus;

1 bit (Cka)

edge selector
I

2

C-bus;
1 bit
(edge)

CLK

ADC

I

2

C-bus;

2 bits (VCO)

C

z

loop filter
I

2

C-bus;

3 bits (Z)

12 to

100 MHz

DIV N (100 to 4095)

0°/180°

MUX

SYNCHRO

C

p

CZ CP

COAST

CKEXT INV

VCO

CKADCO

Ckab

CKAO

CKREFO

CKREF

phase selector B

I

2

C-bus; 5 bits (Pb)

CKBO

MUX

MUX

NCKBO

I2C: 1bit

Fig.3 PLL diagram.

2000 Jan 10 7

Philips Semiconductors Preliminary specification

Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)

TDA8752B

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
DEC2 2 main regulator decoupling input
V

ref

3 gain stabilizer voltage reference input
DEC1 4 main regulator decoupling input
n.c. 5 not connected
RAGC 6 red channel AGC output
RBOT 7 red channel ladder decoupling input (BOT)
RGAINC 8 red channel gain capacitor input
RCLP 9 red channel gain clamp capacitor input
RDEC 10 red channel gain regulator decoupling input
V

CCAR

11 red channel gain analog power supply
RIN 12 red channel gain analog input
AGNDR 13 red channel gain analog ground
GAGC 14 green channel AGC output
GBOT 15 green channel ladder decoupling input (BOT)
GGAINC 16 green channel gain capacitor input
GCLP 17 green channel gain clamp capacitor input
GDEC 18 green channel gain regulator decoupling input
V

CCAG

19 green channel gain analog power supply
GIN 20 green channel gain analog input
AGNDG 21 green channel gain analog ground
BAGC 22 blue channel AGC output
BBOT 23 blue channel ladder decoupling input (BOT)
BGAINC 24 blue channel gain capacitor input
BCLP 25 blue channel gain clamp capacitor input
BDEC 26 blue channel gain regulator decoupling input
V

CCAB

27 blue channel gain analog power supply
BIN 28 blue channel gain analog input
AGNDB 29 blue channel gain analog ground
n.c. 30 not connected
n.c. 31 not connected
I2C/3W 32 selection input between I2C-bus (active HIGH) and 3-wire serial bus (active LOW)
ADD1 33 I2C-bus address control input 1
ADD2 34 I2C-bus address control input 2
TCK 35 scan test mode (active HIGH)

2000 Jan 10 8

Philips Semiconductors Preliminary specification

Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)

TDA8752B

TDO 36 scan test output
DIS 37 I2C-bus and 3-wire disable control input (disable at HIGH level)
SEN 38 select enable for 3-wire serial bus input (see Fig.10)
SDA 39 I2C-bus/3 W serial data input
V

DDD

40 logic I2C-bus/3 W digital power supply
V

SSD

41 logic I2C-bus/3 W digital ground
SCL 42 I2C-bus/3 W serial clock input
n.c. 43 not connected
n.c. 44 not connected
ROR 45 red channel ADC output bit out of range
GOR 46 green channel ADC output bit out of range
BOR 47 blue channel ADC output bit out of range
OGNDB 48 blue channel ADC output ground
B0 49 blue channel ADC output bit 0 (LSB)
n.c. 50 not connected
n.c. 51 not connected
B1 52 blue channel ADC output bit 1
B2 53 blue channel ADC output bit 2
B3 54 blue channel ADC output bit 3
B4 55 blue channel ADC output bit 4
B5 56 blue channel ADC output bit 5
B6 57 blue channel ADC output bit 6
B7 58 blue channel ADC output bit 7 (MSB)
V

CCOB

59 blue channel ADC output power supply
OGNDG 60 green channel ADC output ground
G0 61 green channel ADC output bit 0 (LSB)
G1 62 green channel ADC output bit 1
G2 63 green channel ADC output bit 2
G3 64 green channel ADC output bit 3
G4 65 green channel ADC output bit 4
G5 66 green channel ADC output bit 5
G6 67 green channel ADC output bit 6
G7 68 green channel ADC output bit 7 (MSB)
V

CCOG

69 green channel ADC output power supply
OGNDR 70 red channel ADC output ground
R0 71 red channel ADC output bit 0 (LSB)

SYMBOL PIN DESCRIPTION

2000 Jan 10 9

Philips Semiconductors Preliminary specification

Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)

TDA8752B

R1 72 red channel ADC output bit 1
R2 73 red channel ADC output bit 2
R3 74 red channel ADC output bit 3
R4 75 red channel ADC output bit 4
R5 76 red channel ADC output bit 5
R6 77 red channel ADC output bit 6
R7 78 red channel ADC output bit 7 (MSB)
V

CCOR

79 red channel ADC output power supply
CKREFO 80 reference output clock resynchronized horizontal pulse
CKAO 81 PLL clock output 3 (in phase with reference output clock) (CKAO or CKBO)
OGNDPLL 82 PLL digital ground
CKBO 83 PLL clock output 2
CKADCO 84 PLL clock output 1 (in phase with internal ADC clock)
V

CCO(PLL)

85 PLL output power supply
DGND 86 digital ground
OE 87 output enable not (when OE is HIGH, the outputs are in high-impedance)
PWDWN 88 power-down control input (IC is in power-down mode when this pin is HIGH)
CLP 89 clamp pulse input (clamp active HIGH)
HSYNC 90 horizontal synchronization input pulse
INV 91 PLL clock output inverter command input (invert when HIGH)
CKEXT 92 external clock input
COAST 93 PLL coast command input
CKREF 94 PLL reference clock input
V

CCD

95 digital power supply
AGNDPLL 96 PLL analog ground
CP 97 PLL filter input
CZ 98 PLL filter input
V

CCA(PLL)

99 PLL analog power supply
n.c. 100 not connected

SYMBOL PIN DESCRIPTION

2000 Jan 10 10

Philips Semiconductors Preliminary specification

Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)

TDA8752B

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

CKREFO
V

CCOR

R7
R6
R5
R4
R3
R2
R1
R0
OGNDR
V

CCOG

G7
G6
G5
G4
G3
G2
G1
G0
OGNDG
V

CCOB

B7
B6
B5
B4
B3
B2
B1
n.c.

n.c.

DEC2

V

ref

DEC1

n.c.

RAGC

RBOT

RGAINC

RCLP

RDEC

V

CCAR

RIN

AGNDR

GAGC
GBOT

GGAINC

GCLP

GDEC

V

CCAG

GIN

AGNDG

BAGC

BBOT

BGAINC

BCLP

BDEC

V

CCAB

BIN

AGNDB

n.c.

n.c.

I

2

C/3W

ADD1

ADD2

TCK

TDO

DIS

SEN

SDA

V

DDD

V

SSD

SCL

n.c.

n.c.

ROR

GOR

BOR

OGNDB

B0

n.c.

n.c.

V

CCA(PLL)

CZCPAGNDPLL

V

CCD

CKREF

COAST

CKEXT

INV

HSYNC

CLP

PWDWNOEDGND

V

CCO(PLL)

CKADCO

CKBO

OGNDPLL

CKAO

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

100

99

98

97

96

95

94

939291

90

89

88

87

86

85

848382

81

31

32

33

34

35

36

37

383940

41

42

43

44

45

46

474849

50

FCE469

TDA8752BH

Fig.4 Pin configuration.

2000 Jan 10 11

Philips Semiconductors Preliminary specification

Triple high-speed Analog-to-Digital
Converter 110 Msps (ADC)

TDA8752B

FUNCTIONAL DESCRIPTION

This triple high-speed 8-bit ADC is designed to convert
RGB signals, from a PC or work station, into data used by
a LCD driver (pixel clock up to 200 MHz, using 2 ICs).

IC analog video inputs

The video inputs are internally DC polarized. These inputs
are AC coupled externally.

Clamps

Three independent parallel clamping circuits are used to
clamp the video input signals on the black level and to
control the brightness level. The clamping code is
programmable between code −63.5 and +64 and
120 to 136 in steps of1⁄2LSB. The programming of the
clamp value is achieved via an 8-bit DAC. Each clamp
must be able to correct an offset from ±0.1 V to ±10 mV
within 300 ns, and correct the total offset in 10 lines.

The clamps are controlled by an external TTL positive
going pulse (pin CLP). The drop of the video signal is
<1 LSB.

Normally, the circuit operates with a 0 code clamp,
correspondingto the 0 ADC code. Thisclamp code canbe
changed from −63.5 to +64 as represented in Fig.7, in
steps of1⁄2LSB. The digitized video signal is always
between code 0 and code 255 of the ADC. It is also
possible to clamp from code 120 to code 136
corresponding to 120 ADC code to 136 ADC code. Then
clamping on code 128 of the ADC is possible.

Variable gain amplifier

Three independent variable gain amplifiers are used to
provide, to each channel, a full-scale input range signal to
the 8-bit ADC. The gain adjustment range is designed so
that, for an input range varying from 0.4 to 1.2 V (p-p), the
output signal corresponds to the ADC full-scale input of
1 V (p-p).

To ensure that the gain does not vary over the whole
operating temperature range, an external reference of

2.5 V DC, (V

ref

with a 100 ppm/°C maximum variation)
supplied externally, is used to calibrate the gain at the
beginning of each video line before the clamp pulse using
the following principle.

A differential of 0.156 V (p-p) (1⁄16V

ref

) reference signal is

generated internally from the reference voltage (V

ref

).

During the synchronization part of the video line, the
multiplexer, controlled by the TTL synchronization signal
(HSYNCI, coming from HSYNC; see Fig.1) with a width
equal to one of the video synchronization signals (e.g. the
signal coming from a synchronization separator), is
switched between the two amplifiers.

The output of the multiplexer is either the normal video
signal or the 0.156 V reference signal (during HSYNC).

The corresponding ADC outputs are then compared to a
preset value loaded in a register. Depending on the result
of the comparison, the gain of the variable gain amplifiers
is adjusted (coarse gain control; see Figs 2 and 8). The
three 7-bit registers receive data via a serial interface to
enable the gain to be programmed.

The preset value loaded in the 7-bit register is chosen
between approximately 67 codes to ensure the full-scale
inputrange (see Fig.8).A contrast controlcanbe achieved
using these registers. In this case care should be taken to
stay within the allowed code range (32 to 99).

Afinecorrection using three 5-bit DACs,alsocontrolledvia
the serial interface, is used to finely tune the gain of the
three channels (fine gain control; see Figs 2 and 9) and to
compensate the channel-to-channel gain mismatch.

With a full-scale ADC input, the resolution of the fine
register corresponds to1⁄2LSB peak-to-peak variation.

To use these gain controls correctly, it is recommended to
fix the coarse gain (to have a full-scale ADC input signal)
to within 4 LSB and then adjust it with the fine gain. The
gainis adjusted during HSYNC.During this time theoutput
signal is not related to the amplified input signal. The
outputs,when the coarse gainsystemisstable, are related
to the programmed coarse code (see Fig.8).

ADCs

The ADCs are 8-bit with a maximum clock frequency of
110 Msps. The ADCs input range is 1 V (p-p) full-scale.
One out of range bit exists per channel (ROR, GOR and
BOR). It will be at logic 1 when thesignal isout of range of
the full-scale of the ADCs.

Pipeline delay in the ADCs is 1 clock cycle from sampling
to data output.

The ADCs reference ladders regulators are integrated.