Philips TDA8752 Service Manual

INTEGRATED CIRCUITS

DATA SH EET

TDA8752

Triple high speed Analog-to-Digital
Converter (ADC)

Preliminary specification
Supersedes data of 1997 Apr 22
File under Integrated Circuits, IC02

1997 Jun 04

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

FEATURES

• Triple 8-bit ADC

• Sampling rate up to 80 MHz

• IC controllable via a serial interface, which can be either

I2C-bus or 3-wire, selected via a TTL input pin

• IC analog voltage input from 0.4 to 1.2 V (p-p) to
produce full-scale ADC input of 1 V (p-p)

• 3 clamps for programming a clamping code between

−63.5 and +64 in steps of1⁄2LSB

• 3 controllable amplifiers: gain controlled via the serial

interface to produce a full scale resolution of
peak-to-peak

• Amplifier bandwidth of 250 MHz

• Low gain variation with temperature

• PLL, controllable via the serial interface to generate the

ADC clock, which can be locked to a line frequency from
15 to 280 kHz

• Integrated PLL divider

• Programmable phase clock adjustment cells

• Internal voltage regulators

• TTL compatible digital inputs and outputs

• Chip enable high-impedance ADC output

• Power-off mode

• Possibility to use up to four ICs in the same system,

using the I2C-bus interface, or more, using the 3-wire
serial interface

• 1 W power dissipation.

1

⁄2LSB

TDA8752

GENERAL DESCRIPTION

The TDA8752 is a triple 8-bit ADC with controllable
amplifiers and clamps for the digitizing of large bandwidth
RGB signals.

The clamp level, the gain and all of the other settings are
controlled via a serial interface (either I
serial bus, selected via a logic input).

The IC also includes a PLL that can be locked on the
horizontal line frequency and generates the ADC clock.
The PLL jitter is minimized for high resolution PC graphics
applications. An external clock can also be input to the
ADC.

It is possible to set the TDA8752 serial bus address
between four fixed values, in the event that several
TDA8752 ICs are used in a system, using the I
interface (for example, two ICs used in an odd/even
configuration).

2

C-bus or 3-wire

2

C-bus

APPLICATIONS

• R, G and B high speed digitizing

• LCD panels drive

• LCD projection systems

• VGA and higher resolutions

• Using two ICs in parallel, higher display resolution can

be obtained; 160 MHz pixel frequency.

ORDERING INFORMATION

TYPE

NUMBER

TDA8752H/6
TDA8752H/8 80

1997 Jun 04 2

NAME DESCRIPTION VERSION

QFP100

plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm

PACKAGE SAMPLING

FREQUENCY

(MHz)

SOT317-2

60

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

DDD

V

CCD

V

CCO

V

CCA(PLL)

V

CCO(PLL)

I

CCA

I

DDD

I

CCD

I

CCO

I

CCA(PLL)

I

CCO(PLL)

f

CLK

f

ref(PLL)

f

VCO

INL DC integral non linearity from analog input to

DNL DC differential non linearity from analog input to

∆G

amp

B amplifier bandwidth −3 dB; T
t

set

j

PLL(rms)

DR

PLL

P

tot

analog supply voltage for R, G and B channels 4.75 5.0 5.25 V
logic supply voltage for I2C-bus and 3-wire 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage for R, G and B channels 4.75 5.0 5.25 V
analog PLL supply voltage 4.75 5.0 5.25 V
output PLL supply voltage 4.75 5.0 5.25 V
analog supply current − 120 − mA
logic supply current for I2C-bus and 3-wire − 1.0 − mA
digital supply current − 40 − mA
output stages supply current f

= 80 MHz;

CLK

− 6 − mA

ramp input
analog PLL supply current − 28 − mA
output PLL supply current − 5 − mA
maximum clock frequency TDA8752/6 60 −−MHz

TDA8752/8 80 −−MHz
PLL reference clock frequency 15 − 280 kHz
VCO output clock frequency 12 − 80 MHz

−±0.5 tbf LSB
digital output; full-scale;
ramp input;
f

=80MHz

CLK

−±0.5 tbf LSB
digital output; full-scale;
ramp input;

=80MHz

f

CLK

/T amplifier gain stability as a function of

temperature

settling time of the ADC block plus AGC input signal settling

V

= 2.5 V with

ref

100 ppm/°C maximum

=25°C 250 −−MHz

amb

time < 1 ns; T

amb

=25°C

−−200 ppm/°C

−−6ns

maximum PLL phase jitter (RMS value) − 0.2 − ns
PLL divider ratio without divide-by-2 15 − 2047
total power consumption f

= 80 MHz;

CLK

− 1.0 tbf W
ramp input

1997 Jun 04 3

Philips Semiconductors Preliminary specification

o

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

BLOCK DIAGRAM

RCLP

RBOT

R0 to R7

9

7

86

DGND

AGNDPLL

OGNDG

SSD

V

AGNDG

k, full pagewidth

CLP

CCA(PLL)

V

CCOB

V

CCOR

V

CCAB

V

CCAR

V

82

96

OGNDPLL

48

OGNDB

60
70

OGNDR

41
29

AGNDB

21
13

AGNDR

89

85

CCO(PLL)

99

V

95

CCD

V

59
69

CCOG

V

79

40

DDD

V

27
19

CCAG

V

11

6

71 to 78

CLAMP

8

12

TCK

TDO

353645

OUTPUTS

ADC

MUX

10

ROR

3

GBOT

G0 to G7

GCLP

17

15

61 to 68

RED CHANNEL

14

20

16

GOR

46

GREEN CHANNEL

18

BBOT

BCLP

OE

87

25

23

49, 52 to 58

B0 to B7

BOR

47

84

CKBO

CKADCO

83

CKAO

81

CKREFO

928091

CKEXT

PLL

TDA8752

BLUE CHANNEL

HSYNCI

22

24

28

26

REGULATOR

C-BUS

2

SERIAL

I

INTERFACE

3334384239

OR

COAST

INV

93

94

C-bus; 1-bit

2

(H level)

I

3-WIRE

32

37

CKREF

MGG363

CZ

CP

PWOFF

DEC2DEC1HSYNCn.c.

4 2 88 97 98

90

1, 5, 30, 31, 43 , 44

50, 51, 100

Fig.1 Block diagram.

RAGC

RIN

RGAINC

RDEC

ref

V

GAGC

GIN

GGAINC

GDEC

BAGC

1997 Jun 04 4

BIN

BGAINC

BDEC

ADD2

ADD1

SEN

SCL

SDA

DIS

C/3W

2

I

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

CLP RAGC CKAOUT

handbook, full pagewidth

RCLP

V

ref

RIN

V

P

150

kΩ

3
kΩ

45
kΩ

DAC

5

REGISTER

FINE GAIN ADJUST

I2C-bus; 5 bits

(Fr)

MUX

CLAMP

CONTROL

AGC

V

CCAR

ADC

ADC

8

D

D ≥ R

R

1

1

COARSE GAIN ADJUST

8

7

REGISTER

2

I

C-bus; 7 bits

(Cr)

DAC

8

REGISTER

2

I

C-bus; 8 bits

(Or)

OUTPUTS

SERIAL

2

I

C-BUS

TDA8752

ROR

8

R0 to R7

OE

RBOT

HSYNCI

RGAINC

Fig.2 Red channel diagram.

1997 Jun 04 5

MGG364

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

CKREF

edge selector

2

I

C-bus;
1 bit
(edge)

2

I

C-bus; 1 bit

(V level)

COAST

PHASE

FREQUENCY

DETECTOR

2

I

C-bus; 5 bits

(Ip, Up, Do)

DIV N (15 to 2047)

2

I

C-bus; 11 bits (Di)

C

z

CZ CP

loop filter

2

I

C-bus;

3 bits (Z)

÷ 2

2 bits (VCO)

C

p

VCO

2

I

C-bus;

12 to

80 MHz

phase selector A

2

I

C-bus;

5 bits (Pa)

phase selector B

2

I

C-bus; 5 bits (Pb)

CKEXT INV

MUX

2

I

C-bus;

1 bit (Cka)

0°/180°

CLK

ADC

TDA8752

2

C-bus;

I

1 bit (Ckb)

CKADCO

CKBO

CKAO

Fig.3 PLL diagram.

SYNCHRO

CKREFO

MGG370

1997 Jun 04 6

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
DEC2 2 main regulator decoupling input
V

ref

DEC1 4 main regulator decoupling input
n.c. 5 not connected
RAGC 6 red channel AGC output
RBOT 7 red channel ladder decoupling input (BOT)
RGAINC 8 red channel gain capacitor input
RCLP 9 red channel gain clamp capacitor input
RDEC 10 red channel gain regulator decoupling input
V

CCAR

RIN 12 red channel gain analog input
AGNDR 13 red channel gain analog ground
GAGC 14 green channel AGC output
GBOT 15 green channel ladder decoupling input (BOT)
GGAINC 16 green channel gain capacitor input
GCLP 17 green channel gain clamp capacitor input
GDEC 18 green channel gain regulator decoupling input
V

CCAG

GIN 20 green channel gain analog input
AGNDG 21 green channel gain analog ground
BAGC 22 blue channel AGC output
BBOT 23 blue channel ladder decoupling input (BOT)
BGAINC 24 blue channel gain capacitor input
BCLP 25 blue channel gain clamp capacitor input
BDEC 26 blue channel gain regulator decoupling input
V

CCAB

BIN 28 blue channel gain analog input
AGNDB 29 blue channel gain analog ground
n.c. 30 not connected
n.c. 31 not connected
I2C/3W 32 selection input between I2C-bus (active HIGH) and 3-wire serial bus (active LOW)
ADD1 33 I2C-bus address control input 1
ADD2 34 I2C-bus address control input 2
TCK 35 scan test mode (active HIGH)

3 gain stabilizer voltage reference input

11 red channel gain analog power supply

19 green channel gain analog power supply

27 blue channel gain analog power supply

1997 Jun 04 7

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

SYMBOL PIN DESCRIPTION

TDO 36 scan test output
DIS 37 I2C and 3W disable control input (disable at HIGH level)
SEN 38 select enable for 3-wire serial bus input (see Fig.9)
SDA 39 I2C/3W serial data input
V

DDD

V

SSD

SCL 42 I
n.c. 43 not connected
n.c. 44 not connected
ROR 45 red channel ADC output bit overflow
GOR 46 green channel ADC output bit overflow
BOR 47 blue channel ADC output bit overflow
OGNDB 48 blue channel ADC output ground
B0 49 blue channel ADC output bit 0 (LSB)
n.c. 50 not connected
n.c. 51 not connected
B1 52 blue channel ADC output bit 1
B2 53 blue channel ADC output bit 2
B3 54 blue channel ADC output bit 3
B4 55 blue channel ADC output bit 4
B5 56 blue channel ADC output bit 5
B6 57 blue channel ADC output bit 6
B7 58 blue channel ADC output bit 7 (MSB)
V

CCOB

OGNDG 60 green channel ADC output ground
G0 61 green channel ADC output bit 0 (LSB)
G1 62 green channel ADC output bit 1
G2 63 green channel ADC output bit 2
G3 64 green channel ADC output bit 3
G4 65 green channel ADC output bit 4
G5 66 green channel ADC output bit 5
G6 67 green channel ADC output bit 6
G7 68 green channel ADC output bit 7 (MSB)
V

CCOG

OGNDR 70 red channel ADC output ground
R0 71 red channel ADC output bit 0 (LSB)

40 logic I2C/3W digital power supply
41 logic I2C/3W digital ground

2

C/3W serial clock input

59 blue channel ADC output power supply

69 green channel ADC output power supply

TDA8752

1997 Jun 04 8

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

SYMBOL PIN DESCRIPTION

R1 72 red channel ADC output bit 1
R2 73 red channel ADC output bit 2
R3 74 red channel ADC output bit 3
R4 75 red channel ADC output bit 4
R5 76 red channel ADC output bit 5
R6 77 red channel ADC output bit 6
R7 78 red channel ADC output bit 7 (MSB)
V

CCOR

CKREFO 80 reference output clock
CKAO 81 PLL clock output 3 (in phase with reference output clock)
OGNDPLL 82 PLL digital ground
CKBO 83 PLL clock output 2
CKADCO 84 PLL clock output 1 (in phase with internal ADC clock)
V

CCO(PLL)

DGND 86 digital ground
OE 87 output enable not (when OE is HIGH, the outputs are in high-impedance)
PWOFF 88 power off control input (IC is in power-down mode when this pin is HIGH)
CLP 89 clamp pulse input (clamp active HIGH)
HSYNC 90 horizontal synchronization input pulse
INV 91 PLL clock output inverter command input (invert when HIGH)
CKEXT 92 external clock input
COAST 93 PLL coast command input
CKREF 94 PLL reference clock input
V

CCD

AGNDPLL 96 PLL analog ground
CP 97 PLL filter input
CZ 98 PLL filter input
V

CCAPLL

n.c. 100 not connected

79 red channel ADC output power supply

85 PLL output power supply

95 digital power supply

99 PLL analog power supply

TDA8752

1997 Jun 04 9

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

n.c.

DEC2

V

DEC1

n.c.

RAGC

RBOT

RGAINC

RCLP

RDEC

V

CCAR

RIN

AGNDR

GAGC

GBOT

GGAINC

GCLP

GDEC

V

CCAG

GIN

AGNDG

BAGC
BBOT

BGAINC

BCLP

BDEC

V

CCAB

BIN

AGNDB

n.c.

ref

CCA(PLL)

n.c.

V

CZCPAGNDPLL

99989796959493929190898887868584838281

100

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CCD

V

CKREF

COAST

CKEXT

INV

HSYNC

TDA8752

CLP

PWOFFOEDGND

CCO(PLL)

V

CKADCO

CKBO

OGNDPLL

CKAO

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52

51

CKREFO
V

CCOR

R7
R6
R5
R4
R3
R2
R1
R0
OGNDR

V

CCOG

G7
G6
G5
G4
G3
G2
G1
G0
OGNDG

V

CCOB

B7
B6
B5
B4
B3
B2
B1
n.c.

TDA8752

31323334353637383940414243444546474849

n.c.

C/3W

2

I

ADD1

ADD2

TCK

TDO

DIS

SEN

SDA

V

Fig.4 Pin configuration.

1997 Jun 04 10

DDD

SSD

V

SCL

n.c.

n.c.

ROR

GOR

BOR

B0

OGNDB

50

n.c.

MGG362