INTEGRATED CIRCUITS
TDA8716
8-bit high-speed analog-to-digital converter
Product specification |
1996 Aug 26 |
Supersedes data of April 1993
File under Integrated Circuits, IC02
Philips Semiconductors |
Product specification |
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8-bit high-speed analog-to-digital
TDA8716
converter
FEATURES
∙8-bit resolution
∙Sampling rate up to 120 MHz
∙ECL (10 K family) compatible digital inputs and outputs
∙Overflow/Underflow output
∙Low power dissipation
∙Low input capacitance (13 pF typ.).
APPLICATIONS
∙High speed analog-to-digital convertion
∙Video signal digitizing
∙Radar pulse analysis
∙Transient signal analysis
∙High energy physics research
∙Medical systems
∙Industrial instrumentation.
QUICK REFERENCE DATA
GENERAL DESCRIPTION
The TDA8716 is an 8-bit high-speed Analog-to-Digital Converter (ADC) designed for HDTV and professional applications. The device converts the analog input signal into 8-bit binary coded digital words at a sampling rate of 120 MHz. All digital outputs are ECL compatible.
Measured over full voltage and temperature ranges, unless otherwise specified.
SYMBOL |
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PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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VEEA |
analog supply voltage |
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−5.45 |
−5.2 |
−4.95 |
V |
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VEED |
digital supply voltage |
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−5.45 |
−5.2 |
−4.95 |
V |
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IEEA |
analog supply current |
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− |
50 |
55 |
mA |
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IEED |
digital supply current |
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− |
100 |
110 |
mA |
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IEEO |
output supply current |
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RL = 2.2 kΩ |
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20 |
25 |
mA |
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VRB |
reference voltage BOTTOM |
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−3.130 |
− |
V |
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VRT |
reference voltage TOP |
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− |
−1.870 |
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V |
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ILE |
DC integral linearity error |
see Fig.8 |
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±0.5 |
±1 |
LSB |
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DLE |
DC differential linearity error |
see Fig.9 |
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±0.25 |
±0.45 |
LSB |
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EB |
effective bit |
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fi = 20 MHz; |
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7 |
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bits |
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fCLK = 100 MHz |
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fCLK |
maximum clock frequency |
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120 |
− |
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MHz |
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Ptot |
total power dissipation |
excluding load |
− |
780 |
900 |
mW |
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ORDERING INFORMATION |
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TYPE NUMBER |
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PACKAGE |
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NAME |
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DESCRIPTION |
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VERSION |
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TDA8716 |
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DIP24 |
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plastic dual in-line package; 24 leads (600 mil) |
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SOT101-1 |
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TDA8716T |
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SO32L |
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plastic small outline package; 32 leads; body width 7.5 mm |
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SOT287-1 |
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1996 Aug 26 |
2 |
Philips Semiconductors |
Product specification |
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8-bit high-speed analog-to-digital converter |
TDA8716 |
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BLOCK DIAGRAM |
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analog input |
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8 |
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voltage |
10 |
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7 |
reference top |
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voltage |
9 |
LSB ANALOG |
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MSB ANALOG |
11 |
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PROCESSING |
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reference middle |
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PROCESSING |
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6 |
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voltage |
folding and interpolation |
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reference bottom |
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5 |
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SAMPLE LATCHES |
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DIGITAL PROCESSING |
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CLK input |
1 |
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CLOCK |
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13 |
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LATCHES |
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24 |
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BUFFER |
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2 |
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CLK input |
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12 |
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LSB BINARY |
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MSB BINARY |
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ENCODER |
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ENCODER |
4 |
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6 |
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3 |
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OUTPUT LATCHES |
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TDA8716 |
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ECL BUFFERS |
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19 |
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14 |
15 |
16 |
17 |
18 |
20 |
21 |
22 |
23 |
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MCD265 - 2 |
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digital outputs |
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IN range |
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D0 to D7 |
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analog ground
analog negative supply voltage (– 5.2 V)
digital ground
digital negative supply voltage (– 5.2 V)
two's complement output select
output ground supply voltage (0 V)
Fig.1 Block diagram; TDA8716.
1996 Aug 26 |
3 |
Philips Semiconductors |
Product specification |
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8-bit high-speed analog-to-digital converter |
TDA8716 |
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PINNING TDA8716
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SYMBOL |
PIN |
DESCRIPTION |
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1 |
complementary clock input |
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CLK |
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CLK |
2 |
clock input |
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VEED1 |
3 |
digital negative supply voltage |
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(−5.2 V) |
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CPLT2 |
4 |
two's complement output select |
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(active HIGH) |
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VEEA |
5 |
analog negative supply voltage |
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(−5.2 V) |
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VRB |
6 |
reference voltage BOTTOM |
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AGND1 |
7 |
analog ground 1 |
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VI |
8 |
analog input |
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VRM |
9 |
reference voltage MIDDLE |
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decoupling |
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VRT |
10 |
reference voltage TOP |
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AGND2 |
11 |
analog ground 2 |
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VEED2 |
12 |
digital negative supply voltage |
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(−5.2 V) |
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DGND1 |
13 |
digital ground 1 |
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D0 |
14 |
digital output (LSB) |
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D1 |
15 |
digital output |
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D2 |
16 |
digital output |
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D3 |
17 |
digital output |
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D4 |
18 |
digital output |
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OGND |
19 |
output ground supply voltage (0 V) |
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D5 |
20 |
digital output |
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D6 |
21 |
digital output |
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D7 |
22 |
digital output (MSB) |
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IR |
23 |
IN range |
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DGND2 |
24 |
digital ground 2 |
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handbook, halfpage
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1 |
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24 |
DGND2 |
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CLK |
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CLK |
2 |
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23 |
IR |
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V |
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D7 |
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EED1 |
3 |
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22 |
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C PLT2 |
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D6 |
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4 |
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21 |
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V EEA |
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5 |
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20 |
D5 |
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VRB |
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6 |
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19 |
OGND |
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AGND1 |
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TDA8716 |
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D4 |
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7 |
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18 |
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V |
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D3 |
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I |
8 |
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17 |
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V |
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D2 |
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RM |
9 |
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16 |
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VRT |
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10 |
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15 |
D1 |
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AGND2 |
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D0 |
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11 |
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14 |
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VEED2 |
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DGND1 |
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12 |
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13 |
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MCD259 |
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Fig.2 Pin configuration; TDA8716.
1996 Aug 26 |
4 |
Philips Semiconductors |
Product specification |
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8-bit high-speed analog-to-digital converter |
TDA8716 |
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PINNING TDA8716T
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SYMBOL |
PIN |
DESCRIPTION |
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1 |
complementary clock input |
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CLK |
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CLK |
2 |
clock input |
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VEED1 |
3 |
digital negative supply voltage |
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(−5.2 V) |
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n.c. |
4 |
not connected |
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n.c. |
5 |
not connected |
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CPLT2 |
6 |
two's complement output select |
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(active HIGH) |
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VEEA |
7 |
analog negative supply voltage |
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(−5.2 V) |
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VRB |
8 |
reference voltage BOTTOM |
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AGND1 |
9 |
analog ground 1 |
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VI |
10 |
analog input |
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VRM |
11 |
reference voltage MIDDLE |
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decoupling |
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n.c. |
12 |
not connected |
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n.c. |
13 |
not connected |
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VRT |
14 |
reference voltage TOP |
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AGND2 |
15 |
analog ground 2 |
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VEED2 |
16 |
digital negative supply voltage |
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(−5.2 V) |
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DGND1 |
17 |
digital ground 1 |
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D0 |
18 |
digital output (LSB) |
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D1 |
19 |
digital output |
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n.c. |
20 |
not connected |
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n.c. |
21 |
not connected |
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D2 |
22 |
digital output |
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D3 |
23 |
digital output |
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D4 |
24 |
digital output |
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OGND |
25 |
output ground supply voltage (0 V) |
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D5 |
26 |
digital output |
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D6 |
27 |
digital output |
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n.c. |
28 |
not connected |
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n.c. |
29 |
not connected |
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D7 |
30 |
digital output (MSB) |
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IR |
31 |
IN range |
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DGND2 |
32 |
digital ground 2 |
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handbook, halfpage |
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CLK |
1 |
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32 |
DGND2 |
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CLK |
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2 |
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31 |
IR |
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VEED1 |
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3 |
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30 |
D7 |
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n.c. |
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n.c. |
4 |
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29 |
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n.c. |
5 |
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28 |
n.c. |
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C PLT2 |
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D6 |
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6 |
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27 |
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VEEA |
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7 |
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26 |
D5 |
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V RB |
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8 |
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25 |
OGND |
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AGND1 |
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TDA8716T |
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9 |
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24 |
D4 |
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V I |
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D3 |
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10 |
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23 |
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VRM |
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11 |
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22 |
D2 |
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n.c. |
12 |
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21 |
n.c. |
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n.c. |
13 |
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20 |
n.c. |
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VRT |
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14 |
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19 |
D1 |
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AGND2 |
15 |
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18 |
D0 |
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V EED2 |
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16 |
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17 |
DGND1 |
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MBC742 - 2 |
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Fig.3 Pin configuration; TDA8716T.
1996 Aug 26 |
5 |
Philips Semiconductors |
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Product specification |
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8-bit high-speed analog-to-digital converter |
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TDA8716 |
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LIMITING VALUES |
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In accordance with the Absolute Maximum Rating System (IEC 134). |
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SYMBOL |
PARAMETER |
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CONDITIONS |
MIN. |
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MAX. |
UNIT |
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VEEA |
analog supply voltage |
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−7.0 |
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+0.3 |
V |
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VEED1,VEED2 |
digital supply voltage |
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−7.0 |
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+0.3 |
V |
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VEEA − VEED1; |
supply voltage differences |
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−1 |
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+1 |
V |
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VEEA − VEED2 |
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VI |
input voltage |
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referenced to |
VEEA |
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0 |
V |
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AGND |
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VCLK; |
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input voltage for differential clock drive |
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note 1 |
− |
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2.0 |
V |
CLK(p-p) |
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(peak-to-peak value) |
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IO |
output current (each output stage) |
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− |
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10 |
mA |
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Tstg |
storage temperature |
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−55 |
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+150 |
°C |
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Tamb |
operating ambient temperature |
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0 |
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+70 |
°C |
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Tj |
junction temperature |
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− |
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+150 |
°C |
Note
1.The circuit has two clock inputs: CLK and CLK. Sampling takes place on the rising edge of the clock input signal: CLK and CLK are two's complementary ECL signals.
THERMAL CHARACTERISTICS
SYMBOL |
PARAMETER |
CONDITIONS |
VALUE |
UNIT |
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Rth j-a |
from junction to ambient |
in free air |
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SOT101 |
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35 |
K/W |
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SOT287 (see Fig.4) |
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65 |
K/W |
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HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.
1996 Aug 26 |
6 |
Philips Semiconductors |
Product specification |
|
|
8-bit high-speed analog-to-digital converter |
TDA8716 |
|
|
CHARACTERISTICS
VEEA = −4.95 to −5.45 V; VEED1, VEED2 = −4.95 to −5.45 V; AGND, DGND and OGND shorted together;
Tamb = 0 to +70 °C; unless otherwise specified. (Typical values taken at VEEA = −5.2 V; VEED1, VEED2 = −5.2 V; Tamb = 25 °C).
SYMBOL |
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PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Supply |
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VEEA |
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analog supply voltage |
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−5.45 |
−5.2 |
−4.95 |
V |
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VEED1,VEED2 |
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digital supply voltage |
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−5.45 |
−5.2 |
−4.95 |
V |
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IEEA |
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analog supply current |
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− |
50 |
55 |
mA |
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IEED1,IEED2 |
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digital supply current |
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− |
100 |
110 |
mA |
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IEE |
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output supply current |
RL = 2.2 kΩ |
− |
20 |
25 |
mA |
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Vdiff |
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supply voltage differential |
VEEA − VEED1; VEEA − VEED2 |
−0.5 |
0 |
+0.5 |
V |
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Reference voltages for the resistor ladder |
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VRB |
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reference voltage BOTTOM |
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−3.5 |
−3.13 |
− |
V |
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VRT |
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reference voltage TOP |
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− |
−1.87 |
−1.5 |
V |
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Vref |
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reference voltage differential |
VRT − VRB |
− |
1.26 |
− |
V |
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VOB |
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voltage offset BOTTOM |
note 1 |
− |
130 |
− |
mV |
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VOT |
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voltage offset TOP |
note 1 |
− |
130 |
− |
mV |
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VI(p-p) |
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input voltage amplitude |
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0.95 |
1.0 |
1.5 |
V |
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(peak-to-peak value) |
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Iref |
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reference current |
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− |
15 |
− |
mA |
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RLAD |
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resistor ladder |
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− |
85 |
− |
Ω |
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TCRL |
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temperature coefficient of the |
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− |
0.18 |
− |
Ω/K |
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resistor ladder |
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Inputs |
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CLK and |
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input |
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CLK |
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VIL |
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LOW level input voltage |
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−1850 |
−1770 |
−1650 |
mV |
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VIH |
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HIGH level input voltage |
|
−960 |
−880 |
−810 |
mV |
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IIL |
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LOW level input current |
VCLK = −1.77 V |
− |
1 |
− |
μA |
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IIH |
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HIGH level input current |
VCLK = −0.88 V |
− |
10 |
− |
μA |
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RI |
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input resistance |
|
− |
20 |
− |
kΩ |
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CI |
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input capacitance |
|
− |
2 |
− |
pF |
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VCLK(p-p) |
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differential clock input |
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− |
900 |
− |
mV |
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VCLK − V |
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CLK |
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(peak-to-peak value) |
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Analog input; note 2 |
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IIB |
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input current BOTTOM |
VRB = −3.13 V |
− |
0 |
− |
μA |
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IIT |
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input current TOP |
VRT = −1.87 V |
− |
170 |
− |
μA |
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RI |
|
input resistance |
|
− |
7 |
− |
kΩ |
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CI |
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input capacitance |
|
− |
13 |
20 |
pF |
1996 Aug 26 |
7 |