Philips tda8083 DATASHEETS

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TDA8083

Satellite Demodulator and Decoder (SDD3)

Product speciﬁcation File under Integrated Circuits, IC02

1999 Jul 28

Philips Semiconductors Product speciﬁcation

Satellite Demodulator and Decoder (SDD3)

FEATURES

• One chip Digital Video Broadcasting (DVB) (ETS300421)compliantdemodulatorand concatenated Viterbi and Reed-Solomon decoder with de-interleaver and de-randomizer

• 3.3 V supply voltage

• Relevant outputs are 5 V tolerant to ease interface to

5 V environment

• Few external components for full application

• On-chip crystal oscillator (4 MHz) and Phase-Locked

Loop (PLL) for internal clock generation

• Power-on reset module

• QPSK/BPSK demodulator:

– Different modulation schemes: Quadrature Phase

Shift Keying (QPSK) and Binary Phase Shift Keying (BPSK)

– Interpolator and internal anti-aliasing filter to handle

variable symbol rates – Tuner Automatic Gain Control (AGC) control – Two on-chip matched 7-bit Analog-to-Digital

Converters (ADCs) – Square-root raised-cosine Nyquist – Maximum symbol frequency of 30 Msymbols/s – Can be used at low channel Signal-to-Noise Ratio

(S/R) – Internal full digital carrier recovery, clock recovery

and AGC loops with programmable loop filters – Two carrier recovery loops enabling optimum phase

noise suppression – S/R estimation.

• Viterbi decoder: – Rate1⁄2convolutional code based – Constraint length K = 7 with G1= 171

G2= 133

– Supported puncturing code rates:1⁄2,2⁄3,3⁄4,4⁄5,5⁄6,

⁄7,7⁄8and8⁄

– 4-bit ‘soft decision’ inputs for both I and Q – Truncation length of 144 – Automatic synchronization to detect puncturing rate

and spectral inversion

– Channel Bit Error Rate (BER) estimation from

10−2to 10

– Differential decoding optional.

oct

−8

oct

and

TDA8083

• Reed-Solomon (RS) decoder: – (204, 188, T = 8) Reed-Solomon code – Automatic synchronization of bytes, transport

packets and frames

– Internal convolutional de-interleaving (I = 12; using

internal memory)

– De-randomizer based on Pseudo Random Binary

Sequence (PRBS)

– External indication of uncorrectable error (transport

error indicator is set) – Indication of the number of lost blocks – Indication of the number of corrected blocks.

• Interface: –I2C-bus interface initializes and monitors the

demodulator and Forward Error Correction (FEC) decoder; a default mode is defined

– 6-bit I/O expander for flexibleaccess to and from the

I2C-bus –I2C-bus configurable interrupt input – Switchable I2C-busloop-through tosuppress I2C-bus

crosstalk in the tuner – Digital Satellite Equipment Control (DiSEqC) 1.X,

tone burst generation and tone mode with a

22 or 44 kHz carrier – Parallel or serial output mode for MPEG transport

stream (3-state mode also possible) – Standby mode for reduced power consumption.

• Package: QFP100

• Boundary scan test.

APPLICATIONS

• Digital satellite TV: demodulation and FEC.

1999 Jul 28 2

Philips Semiconductors Product speciﬁcation

Satellite Demodulator and Decoder (SDD3)

GENERAL DESCRIPTION

This document specifies a DVB compliant demodulator and forward error correction decoder IC for reception of QPSK or BPSK modulated signals for satellite applications. The Satellite Demodulator and Decoder (SSD) can handle variable symbol rates without adapting the analog filters within the tuner. Typical applications for this device are:

• MCPC (Multi-Channel Per Carrier): one QPSK or BPSK modulated signal in a single satellite channel (transponder)

• Simul-cast: QPSK or BPSK modulated signal together with a Frequency Modulated (FM) signal in a single satellite channel (transponder).

The TDA8083 can handle variable symbol rates in the range of 12 to 30 Msymbols/s with a minimum number of low cost and non-critical external components.

TheTDA8083 hasminimal interfaceswith thetuner. Itonly requires the demodulated analog I and Q baseband input signals and provides a tuner AGC control signal. Analog-to-digital conversion is done internally by two matched 7-bit ADCs.

TDA8083

The TDA8083 has a double carrier loop configuration which has excellent capabilities of tracking phase noise. Synchronization of the FEC unit is done completely internally, thereby minimizing I2C-bus communication. The output of the TDA8083allows different outputmodes (parallel or serial) to interface to a demultiplexer, descrambler or MPEG-2 decoder including a 3-state mode. For evaluation of the TDA8083, demodulator and Viterbi decoder outputs can be made available externally.

The SDDcan be controlled andmonitored by the I2C-bus. A 5-bit bidirectional I/O expanderand an interrupt line are available. By sending an interrupt signal, the SDD can inform the microcontroller of its internal status. Separate resets are available for logic only, logic plus the I2C-bus andcarrier loops.A switchableI2C-busloop-through tothe tuner is implemented to switch off the I2C-bus connection to thetuner. This reducesphase noise in thetuner in case of I2C-bus crosstalk.

Furthermore, for dish control applications hardware supports DiSEqC 1.X and tone burst generation via I2C-buscontrol. A 22 or a 44 kHzcarrier canbegenerated (tone mode).

The TDA8083 runs on a low frequency crystal which is upconverted to a clock frequency bymeans of an internal PLL. Furthermore, the TDA8083has an internal anti-alias filter, which can cover the range of symbol frequencies without the need to switch external (SAW) filters.

1999 Jul 28 3

Philips Semiconductors Product speciﬁcation

Satellite Demodulator and Decoder

TDA8083

(SDD3)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DDA

DDD

DD(tot)

clk(int)

IL implementation loss note 2 − 0.3 − dB S/R signal-to-noise ratio locking the SDD in

tot

stg

amb

Notes

1. Typical value is specified fora symbol rate of 27.5 Msymbols/s, a puncture rate of3⁄4and a supply voltage of3.3 V.

Maximum value isspecified for a symbolrate of 30 Msymbols/s, a puncturerate of7⁄8, a supplyvoltage of 3.6 V and using a 4 MHz crystal.

2. Implementationloss atthe demodulatoroutput andminimumSNR tolock theTDA8083 aremeasured includingtuner

in a laboratory environment at a symbol rate of 27.5 MS/s.

analog supply voltage 3.0 3.3 3.6 V digital supply voltage 3.0 3.3 3.6 V total supply current note 1 − 270 340 mA internal clock frequency −−64 MHz symbol rate 12 − 30 Msymbols/s Nyquist roll-off − 35 − %

2 −−dB

QPSK mode; note 2

total power dissipation T

=70°C; note 1 − 890 1220 mW

amb

storage temperature −55 − +150 °C ambient temperature 0 − 70 °C junction temperature T

=70°C −−125 °C

amb

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8083H QFP100 plastic quad ﬂat package; 100 leads (lead length 1.95 mm); body

14 × 20 × 2.8 mm

SOT317-2

1999 Jul 28 4

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1999 Jul 28 5

BLOCK DIAGRAM

Philips Semiconductors Product speciﬁcation

Satellite Demodulator and Decoder

(SDD3)

I0 to I6

AGC

Q0 to Q6

99, 100, 1, 2, 6, 7, 8

9, 11, 12, 13, 14, 16, 17

SDA SCL

I2C-BUS

CONTROL

ADC

COARSE

AGC

ADC

INTERRUPT

CONTROL

MUX

SCLT TDI

SDAT

C-BUS

I TUNER SWITCH

DIGITAL

PHASE

ROTATOR

DTO

CONTROL

GENERAL PURPOSE

P0 to P5

64 71

DATA I/O

EXPANDER

SQUARE-ROOT RAISED-COSINE

Σ∆ CONVERTER

TDO

24, 23, 22, 21, 27, 26

BOUNDARY SCAN TEST

TDA8083

ANTI-ALIASING FILTERING

INTERPOLATION

CLOCK

RECOVERY

ANTI-ALIASING FILTERING

INTERPOLATION

CARRIER RECOVERY

(AFC LOOP)

POWER-ON

RESET

TCK63TMS69TRST

DISEQC AND

TONE BURST

FINE AGC

FINE AGC CONTROL

DIGITAL

PHASE

ROTATOR

DTO

CONTROL

XTALO

XTALI

OSCILLATOR

AND PLL

CARRIER RECOVERY

(PHASE LOOP)

LOCK

DETECTORS

SYNCHRONIZATION

DE-INTERLEAVER

VITERBI DECODER

REED-SOLOMON DECODER

DLOCK

VLOCK

RSLOCK

PDOCLK

48 49

PDOSYNC

PDO0 to PDO7

PDOERR PDOVAL

TEST TPLL

PRESET

FCE353

29, 30, 31, 33, 34, 35,

38, 45

ENERGY DISPERSAL REMOVAL

INT

OUTSD

POR

DISCTRL

Fig.1 Block diagram.

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TDA8083

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