Philips TDA8050T-C1 Datasheet

DATA SH EET

Product specification
Supersedes data of 1999 Jun 21
File under Integrated Circuits, IC02

1999 Dec 14

INTEGRATED CIRCUITS

TDA8050

QPSK transmitter

1999 Dec 14 2

Philips Semiconductors Product specification

QPSK transmitter TDA8050

FEATURES

• Programmable gain

• PLL controlled carrier frequency

• 3-wire transmission bus

• 5 V supply voltage.

APPLICATIONS

• QPSK modulation.

GENERAL DESCRIPTION

The QuadraturePhaseShift Keying(QPSK) transmitter is
a monolithic bipolar IC dedicated for quadrature
modulation of the I and Q signals. It includes:

• Two double-balanced mixers

• Symmetrical Voltage Controlled Oscillator (VCO) with

0 to 90 degree signal generation for modulation

• Phase-Locked Loop (PLL) for IF frequency control

• Conversion mixer

• PLL for RF frequency control

• Gain controlled output amplifier

• 3-wire bus and an output buffer.

Two PLLs are incorporated, the first PLL includes:

• Fixed main divider

• Crystal oscillator and its programmable reference

divider

• Phase/frequency detector combined with afixed charge
pump.

The second PLL includes:

• Divide-by-four preamplifier

• 12-bit programmable divider

• Crystal oscillator and its programmable reference

divider

• Phase/frequency detector combined with a ‘clever’
chargepump which drivesthe tuning amplifier,including
9 V output.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

CC

supply voltage 4.75 5.00 5.25 V

f

c

output centre frequency 5 − 40 MHz

V

o(max)

maximum output level − 55 − dBmV

f

xtal

crystal frequency 1 − 4 MHz

f

ref(MOD)

reference frequency for modulator synthesizer − 250 − kHz

f

step

frequency step size for convertor synthesizer 50 − 500 kHz

T

amb

operating ambient temperature 0 − 70 °C

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8050T SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1

1999 Dec 14 3

Philips Semiconductors Product specification

QPSK transmitter TDA8050

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BLOCK DIAGRAM

handbook, full pagewidth

FCE181

1/2

90° 0°

×

×

Σ

27

×

TDA8050

MODULATOR CONVERTER

2524 28

1
3

2

30 31

RF_OUT

OUTEN

BUF_OUT

BUF_OUTC

26

AVCC1

4

AGND2

18

DVCC13DGND

9

AGND1

32

SW_CAP

29

AVCC2

8

7

6

5

CLK

I_IN

I_INC

Q_IN

Q_INC

15

14

DATA

16

EN

RF_OUTC

RF_INIF_FILT

RF_INCIF_FILTC

FIXED

MAIN DIVIDER

DAC

3-WIRE BUS TRANCEIVER

DIGITAL

PHASE

COMPARATOR

DIGITAL

PHASE

COMPARATOR

CHARGE

PUMP

PROGRAM-

MABLE

CHARGE

PUMP

PROGRAMMABLE

REF DIVIDER

PROGRAMMABLE

MAIN DIVIDER

PROGRAMMABLE

REF DIVIDER

101211 17 22 21

20 19

CP_MOD

TKAMOD

TKBMOD TKACONV

OSC_IN TKBCONV

TUNECONV CP_CONV

23

LOCK

Fig.1 Block diagram.

1999 Dec 14 4

Philips Semiconductors Product specification

QPSK transmitter TDA8050

PINNING

SYMBOL PIN DESCRIPTION

OUTEN 1 output enable
BUF_OUT 2 output amplifier balanced output
BUF_OUTC 3 output amplifier balanced output
AGND2 4 converter analog ground 2
I_IN 5 I balanced input
I_INC 6 I balanced input
Q_IN 7 Q balanced input
Q_INC 8 Q balanced input
AGND1 9 modulator analog ground 1
TKAMOD 10 modulator VCO tank circuit input 2
TKBMOD 11 modulator VCO tank circuit input 1
CP_MOD 12 modulator charge pump output for

PLL loop filter
DVCC 13 digital supply voltage
CLK 14 3-wire bus serial control clock
DATA 15 3-wire bus serial control data input
EN 16 3-wire bus serial control enable
OSC_IN 17 crystal oscillator input
DGND 18 digital ground
CP_CONV 19 converter charge pump output for

PLL loop filter
TUNECONV 20 tuning voltage output for converter

VCO
TKBCONV 21 converter VCO tank circuit input 1
TKACONV 22 converter VCO tank circuit input 2
LOCK 23 lock detect signal
IF_FILT 24 IF balanced output to filter
IF_FILTC 25 IF balanced output to filter
AVCC1 26 modulator analog supply voltage
RF_OUTC 27 RF balanced output to filter
RF_OUT 28 RF balanced output to filter
AVCC2 29 converter analog supply voltage
RF_IN 30 RF balancedinputto programmable

amplifier
RF_INC 31 RF balanced input toprogrammable

amplifier
SW_CAP 32 switch capacitor

Fig.2 Pin configuration.

handbook, halfpage

TDA8050

FCE182

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

OUTEN

BUF_OUT

BUF_OUTC

AGND2

I_IN

I_INC

Q_IN

Q_INC

AGND1
TKAMOD
TKBMOD
CP_MOD

DVCC

CLK

SW_CAP
RF_INC
RF_IN
AVCC2

RF_OUTC
AVCC1

RF_OUT

IF_FILTC
IF_FILT
LOCK
TKACONV
TKBCONV
TUNECONV
CP_CONV

DATA

DGND
OSC_IN

EN

1999 Dec 14 5

Philips Semiconductors Product specification

QPSK transmitter TDA8050

FUNCTIONAL DESCRIPTION

The I and Q are balanced analog signals at a level of
400 mV (p-p). These are mixed by two double balanced
mixers with the output signal generated by a first local
oscillator providing the modulated signal.

The modulated signal is then filtered by an IF filter. This
filteredsignal together with asignalgenerated by asecond
local oscillator is converted by a balanced mixer to
produce the QPSK signal.

TheQPSK signal isamplified by again controlled amplifier
to a level suitable for transmission. The gain of the
controlled amplifier is buscontrolled and this amplifier can
be disabled when not transmitting to provide signal
attenuation.

The amplified signal is applied to an on-chip amplifier
having two balanced outputs (open collector) linked totwo
chip resistors (values 150 Ω), and 9 V. The balanced
outputs are designed to drive a 2 : 1 transformer
(Siemens V944) with a 75 Ω load giving an output level
of 55 dBmV.The output frequencyrange of the transmitter
is 5 to 40 MHz.

The frequency of the first local oscillator operates at twice
the frequency (i.e. 280 MHz) fixed by a Phase-Locked
Loop (PLL) implemented in the circuit.

Thefrequencyof the second localoscillatoroperatesin the
bandwidth 145 to 180 MHz and programmable due to a
PLL implemented in the circuit.

The VCO of both first and secondlocal oscillatorsrequires
an external LC tank circuit with two varicap diodes.

The data to the PLL is loaded in bursts framed by the
signal EN. Programming rising clock edges and their
appropriate data bits are ignored until EN goes active
(LOW). The internal latches are updated with the latest
programming data when EN returns inactive (HIGH).
The last 14 bits are stored in the programming register.

No check is made on the number of clock pulses received
during the time programming is enabled. A wrong active

clock edge will be generated causing a shift of data
bits, if EN goes HIGH while CLK is still LOW. At power

up, EN should beHIGH. The lock detector output LOCK is
HIGH when both PLLs are in lock.

The main divider ratio and the reference divider ratios are
provided via the serial bus. A control register controls the
Digital-to-Analog Converter (DAC), the output amplifier
and the charge pump currents (Tables 1, 2 and 3).

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

CC

supply voltage −0.3 +6.0 V

t

sc

short-circuit time (every pin to VCCor GND) − 10 s

V

max

voltage on all pins except BUF_OUT, BUF_OUTC and TUNECONV −0.3 V

CC

V

V

o(tune)

output tuning voltage −0.3 +30 V

V

o(buf)

output buffer voltage on pins BUF_OUTand BUF_OUTC − 10 V

P

tot

maximum power dissipation − 800 mW

T

amb

operating ambient temperature 0 70 °C

T

stg

storage temperature −40 +150 °C

T

j(max)

junction temperature − 150 °C

1999 Dec 14 6

Philips Semiconductors Product specification

QPSK transmitter TDA8050

THERMAL CHARACTERISTICS

HANDLING

Human Body Model (HBM): The IC pins withstand 2 kV except pins 27 and 28 (1750 V).
Machine Model (MM): The IC pins withstand 100 V.

CHARACTERISTICS

Measured in application circuit (see Fig.9) with the following conditions: V

CC

=5V; T

amb

=25°C; all AC units are RMS

values; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 63 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA(mod)

modulator analog supply voltage 4.75 5 5.25 V

I

CCA(mod)

modulator analog supply current − 41 − mA

V

CCA(conv)

converter analog supply voltage 4.75 5 5.25 V

I

CCA(conv)

converter analog supply current − 48 − mA

I

CC(buf)

buffer output supply current − 44 − mA

V

CCD

digital supply voltage 4.75 5 5.25 V

I

CCD

digital supply current − 22 − mA

V

CC(tune)

tuning supply voltage −−9V

Quadrature modulator I and Q inputs

V

I(DC)

input DC level over the complete range of

temperature

− 0.5VCC− V

V

i(p-p)

signal input level (balanced)
(peak-to-peak value)

indicative − 400 500 mV

f

i(max)

I and Q maximum input frequency indicative − 10 − MHz

Z

i(dif)

differential input impedance − 4.4 − kΩ

B

(1dB)

1 dB amplifier bandwidth indicative − 10 − MHz
MODULATOR
f

c

output centre frequency −−140 MHz

∆A amplitude imbalance see Fig.3 −−±1dB
∆Φ phase imbalance −−±2 deg

LO

(sup)

LO suppression see Fig.3 −−28 − dBc
Z

o(dif)

differential output impedance − 1.8 − kΩ
MODULATOR VOLTAGE CONTROLLED OSCILLATOR
f

osc(mod)

oscillation frequency VCO −−280 MHz

1999 Dec 14 7

Philips Semiconductors Product specification

QPSK transmitter TDA8050

Converter output

V

o

output level fi= 30 MHz; V

i(dif)

= 100 mV

at I and Q inputs

37.5 40 42.5 dBmV

∆V

o

output flatness fi= 5 to 40 MHz;

V

i(dif)

= 100 mV at I and Q

inputs

−−2dB

f

c

output centre frequency 5 − 40 MHz
Z

o(dif)

differential output impedance − 150 −Ω
IM3 3rd-order intermodulation distortion see Fig.4 −−−35 dBc
H

2

2nd-order harmonic of 5 to 40 MHz

signal

fi= 10 to 80 MHz;
V

i(dif)

= 100 mV at I and Q

inputs

−−−45 dBc

H

3

3rd-order harmonic of 5 to 40 MHz

signal

fi= 15 to 120 MHz;
V

i(dif)

= 100 mV at I and Q

inputs

−−−45 dBc

S

o

mixer spurious outputs of

5 to 40 MHz signal

fi= 5 to 40 MHz;
V

i(dif)

= 100 mV at I and Q

inputs

−−−50 dBc

Converter voltage controlled oscillator

f

osc(min)

minimum oscillation frequency −−145 MHz
f

osc(max)

maximum oscillation frequency 180 −−MHz
Programmable gain and output buffer; note 1
Z

i(dif)

differential input impedance − 5.6 − kΩ

∆G output level step size −−2dB
∆Buf

o

output level adjust range Vi= 30 dBmV sine wave;

40 MHz at pin
RF_IN and RF_INC;
DAC = 0 to 31

32 −−dB

V

o

output level − 55 − dBmV
∆V

o

output flatness fi= 5 to 40 MHz;

Vi= 30 dBmV sine wave;
DAC = 28

−−2dB

V

O(ENL)

output controlled enable LOW output buffer on −−0.8 V
V

O(ENH)

output controlled enable HIGH output buffer off 2.4 −−V
ISO disable isolation V

i(dif)

= 100 mV;
Vo= 55 dBmV; DAC = 28;
fi= 40 MHz; OE = 0.5

−35 −−dBc

G

(max)

maximum gain see Fig.5 − 22 − dB

V

o(1dB)

1 dB compression point see Fig.5 60 −−dBmV

H

2

2nd-order harmonic of 5 to 40 MHz
signal

see Fig.6

f

i

=10to40MHz −−−45 dBc

f

i

= 54 to 120 MHz −−−35 dBc

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Dec 14 8

Philips Semiconductors Product specification

QPSK transmitter TDA8050

H

3

3rd-order harmonic of 5 to 40 MHz
signal

Fig.6

f

i

=15to40MHz −−−45 dBc

f

i

= 54 to 120 MHz −−−35 dBc

Overall; note 1

Φ

osc

phase noise note 2;

at 10 kHz −−70 − dBc/Hz
at 100 kHz −−90 − dBc/Hz

S

o

spurious signals of 5 to 40 MHz
signal

fi= 5 to 40 MHz;
V

i(dif)

= 100 mV at I and Q
inputs; Vo= 30 to 55 dBmV

−−−50 dBc

ISO

tot

total isolation at I/Q mid-range see Fig.7 −−−65 dBc

C/N carrier to noise ratio at final output

at 2 MHz from carrier

V

i(dif)

= 100 mV
Vo= 35 to 55 dBmV;
fi= 26.5 MHz

− 113 − dBc/Hz

Crystal oscillator

f

xtal

crystal frequency note 3 1 − 4 MHz

Z

i

input impedance f

xtal

= 4 MHz 600 1200 −Ω

V

I(DC)

DC input level − 2.9 − V

Modulator synthesizer

f

ref(mod)

reference frequency − 250 − kHz

RDR1 reference divider ratio

programmable

4 − 16

ND1 fixed main divider ratio − 1120 −
I

cp

charge-pump current fixed − 0.30 − mA

Converter synthesizer

f

step

frequency step size 50 − 500 kHz
RD2 fixed reference divider ratio − 2 −
RDR2 reference divider ratio

programmable

see Table 4 4 − 160

ND2 fixed main divider ratio − 4 −
NDR2 programmable main divider ratio see Table 4 290 − 3600

Three wire bus

V

IL

LOW-level input voltage −−0.8 V
V

IH

HIGH-level input voltage 2.4 −−V

Lock detect pin

V

o(lock)

output voltage (lock) − 5 − V
V

o(unlock)

output voltage (unlock) − 0.02 − V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT