Philips TDA8044AH Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA8044

Satellite demodulator and decoder

Product speciﬁcation Supersedes data of 1998 Nov 17 File under Integrated Circuits, IC02

2000 Feb 21

Philips Semiconductors Product speciﬁcation

Satellite demodulator and decoder TDA8044

FEATURES

• General features: – One-chip Digital Video Broadcasting (DVB)

compliant Quadrature Phase Shift Keying (QPSK) and Binary Phase Shift Keying (BPSK) demodulator and concatenated Viterbi/Reed-Solomon decoder with de-interleaver and de-randomizer

(ETS 300 421) – 3.3 V supply voltage (input pads are 5 V tolerant) – Standby mode for low power dissipation – Internal clock PLL to allow low frequency crystal

application and selectable clock frequencies – Power-on reset module – Package: QFP100 – Boundary scan test.

• QPSK/BPSK demodulator: – Interpolator and anti-alias filter to handle a large

range of symbol rates without additional external filtering

– On-chip AGC of the analog input I and Q baseband

signals or tuner AGC control

– Two on-chip matched Analog-to-Digital Converters

(ADCs; 7 bits)

– Half Nyquist (square root raised-cosine) filter with

selectable roll-off factor

– Large range of symbol frequencies:

0.5 to 45 Msymbols/s for TDA8044 and

0.5 to 30 Msymbols/s for TDA8044A, including Single Carrier Per Channel (SCPC) function

– Can be used at low channel Signal-to-Noise ratio

(S/N)

– Internal carrier recovery, clock recovery and AGC

loops with programmable loop filters

– Two loop carrierrecovery enabling phase tracking of

the incoming symbols

– Software carrier sweep for low symbol rate

applications – Signal-to-noise ratio estimation – External indication of demodulator lock.

• Viterbi decoder: – Rate1⁄2convolutional code based – Constraint length K = 7 with G1= 171

G2= 133

⁄2,2⁄3,3⁄4,4⁄5,5⁄6,6⁄7,7⁄8and8⁄

; supported puncturing code rates:

oct

and

– 4 bits input for ‘soft decision’ for both I and Q

– Truncation length: 144 – Automatic synchronization – Channel Bit Error Rate (BER) estimation – External indication of Viterbi sync lock – Differential decoding optional.

• Reed-Solomon (RS) decoder: – (204, 188, T = 8) Reed-Solomon code – Automatic (I2C-bus configurable) synchronization of

bytes, transport packets and frames

– Internal convolutional de-interleaving (I = 12; using

internal memory)

– De-randomizer based on Pseudo Random Bit

Sequence (PRBS)

– External indication of Register Select (RS) decoder

sync lock

– External indication of uncorrectable error (transport

error indicator is set) – External indication of corrected byte – Indication of the number of lost blocks – Indication of the number of corrected blocks.

• Interface: –I2C-bus interface to initialize and monitor the

demodulator and Forward Error Correction (FEC) decoder; when no I2C-bus usage, default mode is

defined – Programmable interrupt facility – 6 bitsI/O expander forflexible access to andfrom the

I2C-bus – SwitchableI2C-busloop-through to suppress I2C-bus

crosstalk in the tuner – DiSEqC level 1.X support for dishcontrol applications – 3-state mode for transport stream outputs.

APPLICATIONS

• Digital satellite TV: demodulation and Forward Error Correction (FEC).

2000 Feb 21 2

Philips Semiconductors Product speciﬁcation

Satellite demodulator and decoder TDA8044

GENERAL DESCRIPTION

This document gives preliminary information about the TDA8044and TDA8044A, which arethesuccessors of the TDA8043. The TDA8044A is only specified where the product deviates from the TDA8044, all other references arethe same. TheTDA8044 is backwards compatiblewith the TDA8043, with respect to pinning and the I2C-bus software. The TDA8044 is a DVB compliant demodulator anderror correction decoder ICfor reception of QPSKand BPSK modulated signals for satellite applications. It can handle variable symbol rates in the range of

0.5 to 45 Msymbols/s (0.5 to 30 Msymbols/s for TDA8044A) with a minimum number of low cost and non-critical external components. Typical applications for this device are Multi Channel Per Carrier (MCPC), Single Channel Per Carrier (SCPC) and simulcast. In these applications one satellite transponder contains respectively one broadQPSK carrier, several small QPSK carriers and one small QPSK carrier together with one or two FM carriers.

TheTDA8044 has minimum interface withthetuner, it only requires the demodulated analog I and Q baseband input signals. Analog-to-digital conversion is performed internally by two matched 7-bit ADCs. Since all the loops (AGC, clock and carrier recovery) are internal, no feedback to the tuner is needed. However, for maximum tuner flexibility, there is the possibility to close the AGC and carrier recovery loop externally via the tuner.

Thenumberof external components required for operation of the TDA8044 is very low. Moreover the external components are low cost and non-critical. This gives an easy and low cost application. The TDA8044 operates on a low frequency crystal which is upconverted to a clock frequency by means of an internal PLL. Different clock frequenciescanbeselectedwith the PLL without changing the crystal. This allows for maximum flexibility concerning symbol rate range combined with minimum power consumption.

The TDA8044 alsohas internal anti-alias filters, whichcan cover a large range of symbol frequencies (approximately one decade) without the need to switch external (SAW) filters. To cover the whole range of 0.5 to 45 Msymbols/s switching of clock frequency (internally) and filtering (externally) is necessary.

The TDA8044 has a double carrier loop configuration which has excellent capabilities of tracking phase noise. Synchronization of the FEC unit is done completely internally, thereby minimizing I2C-bus communication. The output of the TDA8044 is highly flexible, allowing different output modes to interface to a demultiplexer/descrambler/MPEG-2 decoder including a 3-state mode. For evaluation of the TDA8044, demodulator and Viterbi outputs can be made available externally.

Interfacing to the TDA8044 has been extended compared to the TDA8043. Separate resets are available for logic only, logic plus I2C-bus and carrier loops. A Power-on reset module has been implemented which gives a reset signal at power-up. This signal can be used to reset the TDA8044 in order to guarantee correct starting of the IC. Two extra general purpose I/O pins (I/O expanders) have been added. A switchable I2C-bus loop-through to the tuner is implemented to switch-off the I2C-bus connection to the tuner. This reduces phase noise in the tuner in the event of I2C-bus crosstalk. The transport stream outputs can be put in 3-state mode. DiSEqC level 1.X support is integrated for dish control applications. The power consumption in standby mode has been decreased considerably.

2000 Feb 21 3

Philips Semiconductors Product speciﬁcation

Satellite demodulator and decoder TDA8044

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DDA

DDD

DD(tot)

clk

tot

IL implementation loss note 5 − 0.3 − dB S/N signal-to-noise ratio for locking

analog supply voltage 3.05 3.3 3.55 V digital supply voltage 3.05 3.3 3.55 V total supply current V

DDD

= 3.3 V TDA8044 note 1 − 320 480 mA TDA8044A notes 1 and 2 −−350 mA

internal clock frequency CFS = 0 or CFS = 1;

= 4 MHz

xtal

TDA8044 note 1 10.7 − 96 MHz TDA8044A notes 1 and 2 10.7 − 64 MHz

symbol rate note 3

TDA8044 0.5 − 45 Msymbols/s TDA8044A 0.5 − 30 Msymbols/s

total power dissipation T

=70°C; note 4

amb

TDA8044 − 1150 1700 mW TDA8044A −−1250 mW

note 5 2 −−dB

the TDA8044

Notes

1. Programmable internal frequencies possible: a) Values 10.7, 16, 32 or 64 MHz for CFS = 0. b) Values 16, 24, 48 or 96 MHz for CFS = 1.

2. CFS is set to logic 0.

3. Without switching internal clock frequencies, a range of 1 decade can be covered. To cover the full range of symbol frequencies, internal clock frequencies and external (SAW) filters must be switched. Details can be found in the application note.

4. Maximum value is specified for asymbol rate of45 Msymbols/s, a puncturing rate of7⁄8, a clock frequency of 96 MHz and a 3.55 V power supply. The typical value is specified for a symbol rate of 27.5 Msymbols/s, a puncture rate of3⁄ and a clock frequency of 64 MHz.

5. Implementation loss at the demodulator output andminimum S/N to lock the TDA8044 are measured including tuner in a laboratory environment at a symbol rate of 27.5 Msymbols/s and a clock frequency of 64 MHz.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA8044H QFP100 plastic quad ﬂat package; 100 leads (lead length 1.95 mm); TDA8044AH

body 14 × 20 × 2.8 mm

PACKAGE

SOT317-2

2000 Feb 21 4

Philips Semiconductors Product speciﬁcation

Satellite demodulator and decoder TDA8044

PINNING

SYMBOL PIN I/O DESCRIPTION

I2 1 I digital I-input bit 2 (ADC bypass) I3 2 I digital I-input bit 3 (ADC bypass) V

SSD1

CFS 4 I clock frequency selection (remains at logic 0 for TDA8044A) V

SSD2

I4 6 I digital I-input bit 4 (ADC bypass) I5 7 I digital I-input bit 5 (ADC bypass) I6 8 I digital I-input bit 6 (ADC bypass: MSB) Q0 9 I digital Q-input bit 0 (ADC bypass: LSB) V

DDD1

Q1 11 I digital Q-input bit 1 (ADC bypass) Q2 12 I digital Q-input bit 2 (ADC bypass) Q3 13 I digital Q-input bit 3 (ADC bypass) Q4 14 I digital Q-input bit 4 (ADC bypass) V

SSD3

Q5 16 I digital Q-input bit 5 (ADC bypass) Q6 17 I digital Q-input bit 6 (ADC bypass: MSB) V

SSD4

DDD2

PRESET 20 I set device into default mode P3 21 I/O quasi-bidirectional I/O port (bit 3) P2 22 I/O quasi-bidirectional I/O port (bit 2) P1 23 I/O quasi-bidirectional I/O port (bit 1) P0 24 I/O quasi-bidirectional I/O port (bit 0) V

DDD3

P5 26 I/O quasi-bidirectional I/O port (bit 5) P4 27 I/O quasi-bidirectional I/O port (bit 4) PDOCLK 28 O output clock for transport stream bytes PDO0 29 O parallel data output (bit 0) PDO1 30 O parallel data output (bit 1) PDO2 31 O parallel data output (bit 2) V

SSD5

PDO3 33 O parallel data output (bit 3) PDO4 34 O parallel data output (bit 4) PDO5 35 O parallel data output (bit 5) V

SSD6

SSD7

PDO6 38 O parallel data output (bit 6) POR 39 I Power-on reset [can be connected to PRESET (pin 20)] V

DDD4

3 − digital ground 1

5 − digital ground 2

10 − digital supply voltage 1

15 − digital ground 3

18 − digital ground 4 19 − digital supply voltage 2

25 − digital supply voltage 3

32 − digital ground 5

36 − digital ground 6 37 − digital ground 7

40 − digital supply voltage 4

2000 Feb 21 5

Philips Semiconductors Product speciﬁcation

Satellite demodulator and decoder TDA8044

SYMBOL PIN I/O DESCRIPTION

DDD5

SSD8

DDD6

DDD7

PDO7 45 O parallel data output (bit 7) n.c. 46 − not connected V

SSD9

PDOERR 48 0 transport error indicator PDOVAL 49 O data valid indicator PDOSYNC 50 0 transport packet synchronization signal V

SSD10

SCL 52 I serial clock input of I SDA 53 I/O serial data of I INT 54 O interrupt output (active LOW) A0 55 I I RSLOCK 56 O Reed-Solomon lock indicator VLOCK 57 O Viterbi lock indicator DLOCK 58 O demodulator lock indicator V

DDD8

DDD9

TEST 61 I test pin (normally connected to ground) TRST 62 I BST optional asynchronous reset (normally connected to ground) TCK 63 I BST dedicated test clock (normally connected to ground) SCLT 64 I serial clock of I SDAT 65 I/O serial data of I V

DDD10

SSD11

SSD12

TMS 69 I BST input control signal (normally connected to ground) TDO 70 O BST serial test data output TDI 71 I BST serial test data in (normally connected to ground) V

DDD11

SSD13

SSD(AD)

DDD(AD)

ref(B)

SSA1

QA 78 − analog input Q V

ref(Q)

IA 80 I analog input I V

SSA2

41 − digital supply voltage 5 42 − digital ground 8 43 − digital supply voltage 6 44 − digital supply voltage 7

47 − digital ground 9

51 − digital ground 10

C-bus

C-bus hardware address

59 − digital supply voltage 8 60 − digital supply voltage 9

C-bus loop-through

C-bus loop-through 66 − digital supply voltage 10 67 − digital ground 11 68 − digital ground 12

72 − digital supply voltage 11 73 − digital ground 13 74 − digital ground ADC 75 − digital supply ADC 76 O bottom reference voltage for ADC 77 − analog ground 1

79 O AGC decoupling - Q path

81 − analog ground 2

2000 Feb 21 6

+ 14 hidden pages