Philips TDA4887PS Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA4887PS

160 MHz bus-controlled monitor video preamplifier

Product speciﬁcation File under Integrated Circuits, IC02

2001 Oct 19

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video preampliﬁer

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION

7.1 Signal input stage

7.2 Electronic potentiometer stages

7.3 Output stage

7.4 Pedestal blanking

7.5 Output clamping and feedback references

7.6 Clamping and blanking pulses

7.7 On Screen Display insertion and OSD contrast

7.8 Subcontrast adjustment, contrast modulation and beam current limiting

7.9 I2C-bus control

7.10 I2C-bus data buffer

8 LIMITING VALUES 9 THERMAL CHARACTERISTICS

TDA4887PS

10 CHARACTERISTICS 11 I2C-BUS PROTOCOL 12 TEST AND APPLICATION INFORMATION

12.1 Test board

12.2 Application boardwith monolithic post amplifier

12.3 Building the application board

12.4 Application hints 13 INTERNAL CIRCUITRY 14 PACKAGE OUTLINE 15 SOLDERING

15.1 Introduction to soldering through-hole mount packages

15.2 Soldering by dipping or by solder wave

15.3 Manual soldering

15.4 Suitability of through-hole mount IC packages for dipping and wave soldering methods

16 DATA SHEET STATUS 17 DEFINITIONS 18 DISCLAIMERS 19 PURCHASE OF PHILIPS I2C COMPONENTS

2001 Oct 19 2

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video preampliﬁer

1 FEATURES

• 160 MHz pixel rate

• 2.7 ns rise time, 3.6 ns fall time

• I2C-bus control

• I2C-bus data buffer for synchronization of adjustments

• 8-bit Digital-to-Analog Converters (DACs)

• 200 ns input clamping pulse

• 4.6 V (p-p) output signal

• Brightness control with grey scale tracking for

user-friendly performance (4 dB more than TDA4885 and TDA4886)

• Brightness control without grey scale tracking for easy alignment

• On Screen Display (OSD) mixing with 50 MHz pixel rate

• OSD contrast

• Negative feedback for DC-coupled cathodes

• Especially for AC-coupled cathodes

– Bus controlled black level adaptable to post amplifier

type – Internal positive feedback – DAC outputs for black level restoration

• Integrated black level storage capacitors

• Beam current limiting

• Subcontrast/contrast modulation

• Adjustable pedestal blanking

• Sync clipping.

TDA4887PS

2 GENERAL DESCRIPTION

The TDA4887PS is a monolithic integrated RGB preamplifier for colour monitor systems (e.g. 15" and 17") with I2C-bus control and OSD. In addition to bus control, beam current limiting and contrast modulation are possible. The IC offers brightness control with or without grey scale tracking for easy alignment. The signals are amplified to drive commonly used video modules or discrete solutions. A choice can be made between individual black level control with negative feedback from the cathode (DC coupling), or black level control with positive feedback and three DAC outputs for external cut-off control (AC coupling).

The circuit can be used with special advantages in conjunction with the TDA485x monitor deflection IC family.

3 ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA4887PS SDIP24 plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1

2001 Oct 19 3

PACKAGE

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

TDA4887PS

preampliﬁer

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

P(n)

i(n)(b-w)

o(n)(b-w)(max)

o(n)

o(n)(source)(M)

o(n)(sink)(M)

bl(n)(ref)

r(n)

f(n)

δV

o(n)

ct(f)

∆G

track

δG gain control related to maximum gain −13.5 − 0dB ∆V

bl(n)

∆V

DA(n)

supply voltage (pin 7) 7.6 8.0 8.8 V supply current (pin 7) − 25 30 mA supply voltage; channels 1, 2 and 3

7.6 8.0 8.8 V

(pins 21, 18 and 15) supply current; channels 1, 2 and 3

− 20 25 mA

(pins 21, 18 and 15) input voltage; channels 1, 2 and 3

− 0.7 1.0 V

(pins 6, 8 and 10) (black-to-white value) maximum output voltage swing

(black-to-white value); channels 1, 2 and 3 (pins 22, 19 and 16)

output voltage level (pins 22,

maximum contrast; maximum gain; V

= 0.7 V; RL=2kΩ

i(n)(b-w)

4.2 4.6 4.9 V

0.1 − V

− 1V

P(n)

19 and 16) peak output source current

(pins 22, 19 and 16) peak output sink current

(pins 22, 19 and 16) black level reference voltage

during fast positive signal transients

during fast negative signal transients

typical values

−40 −− mA

−−20 mA

(pins 22, 19 and 16)

DC coupling control bit FPOL = 0 0.5 − 2.0 V AC coupling control bit FPOL = 1;

0.53 − 1.89 V

no pedestal blanking

rise time of fast transients at signal

− 2.7 − ns

outputs (pins 22, 19 and 16) fall time of fast transients at signal

− 3.6 − ns

outputs (pins 22, 19 and 16) overshoot/undershoot at signal outputs

(pins 22, 19 and 16)

input rise/fall times = 1 ns; maximum colour signal

−−10 %

crosstalk suppression by frequency f = 50 MHz 25 −− dB contrast control: colour signal related to

−45 − 0dB

maximum colour signal tracking of output colour signals of

channels 1, 2 and 3

brightness control (difference between

contrast control from

− 0 0.5 dB

maximum to minimum

control bit BRI = 0 −10 − +33 % video black level and reference black level at signal outputs related to maximum colour signal)

brightness control range (DAC output voltages for AC coupling or internal feedback reference voltage for DC

from maximum to

minimum; control bit

BRI=1

−1.4 − 0V

coupling)

2001 Oct 19 4

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

TDA4887PS

preampliﬁer

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

FB/Rn

OSDn(max)

DAC output voltage range without brightness control (for black level restoration) (pins 23, 20 and 17)

maximum OSD colour signal related to maximum colour signal (pins 22, 19 and 16)

OSD colour signal related to maximum OSD colour signal

control bit FPOL = 1;

control bit BRI = 0

maximum OSD contrast;

maximum gain

OSD contrast control from

maximum to minimum

3.95 − 5.75 V

− 96 − %

−12 − 0dB

2001 Oct 19 5

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2001 Oct 19 6

SDA SCL

12 13

DISO DISV FPOL BRI

I2C-BUS

8-BIT

DAC

4 8 8 8 8

4-BIT DAC

8-BIT

DAC

ook, full pagewidth

8-BIT

DAC

8-BIT

DAC

2-BIT

DAC

3-BIT

DAC

8 8

8-BIT

DAC

8-BIT

DAC

8-BIT

DAC

5 BLOCK DIAGRAM

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

preampliﬁer

LIM

INPUT

input clamping

CLAMPING BLANKING

INPUT CLAMPING BLANKING

blanking

DISO

fast

FBL OSD1OSD2OSD

SUBCONTRAST

CONTRAST MODULATION

LIMITING

CONTRAST

OSD INPUT

1234

OSD

CONTRAST

OSD

CONTRAST

OSD

CONTRAST

BRIGHTNESS

SWITCH

BRIGHTNESS

BLANKING

INPUT CLAMPING

VERTICAL BLANKING

BRI

GAIN

PEDESTAL BLANKING

AC BLACK

LEVEL

FPOL

CHANNEL 1

REFERENCE

FPOL

CHANNEL 2

REFERENCE

FPOL

CHANNEL 3

REFERENCE

TDA4887PS

FPOL

blankingblanking

BLANKING

OUTPUT CLAMPING

511

output clamping

DISV

HFBCLI

FPOL

SUPPLY

GND

MHB943

FB/R

FB/R V

FB/R

GNDX

TDA4887PS

Fig.1 Block diagram.

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video preampliﬁer

6 PINNING

SYMBOL PIN DESCRIPTION

FBL 1 fast blanking input for OSD insertion OSD

OSD

CLI 5 input clamping and vertical blanking

GND 9 ground V

HFB 11 output clamping and blanking input SDA 12 I SCL 13 I GNDX 14 ground signal, channels 1, 2 and 3 V

FB/R

LIM 24 subcontrast adjustment, contrast

2 OSD input, channel 1 3 OSD input, channel 2 4 OSD input, channel 3

input 6 signal input, channel 1 7 supply voltage 8 signal input, channel 2

10 signal input, channel3

C-bus serial data input/output

C-bus clock input

15 supply voltage, channel 3 16 signal output, channel 3 17 feedback input/reference voltage

output channel 3

18 supply voltage, channel 2 19 signal output, channel 2 20 feedback input/reference voltage

output, channel 2

21 supply voltage, channel 1 22 signal output, channel 1 23 feedback input/reference voltage

output, channel 1

modulation and beam current

limiting input

handbook, halfpage

FBL

OSD

CLI

TDA4887PS

GND

HFB

SDA

MHB919

Fig.2 Pin configuration.

TDA4887PS

LIM

FB/R

GNDX

SCL

2001 Oct 19 7

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video preampliﬁer

7 FUNCTIONAL DESCRIPTION

Referalsotoblockdiagram(Fig.1)anddefinitionsoflevels and signals (Chapter 10).

7.1 Signal input stage

The RGB input signals are capacitively coupled into the TDA4887PS from a low-ohmic source (75 Ω recommended) and actively clamped to the internal reference black level during signal black level. The signal amplitude is 0.7V high-ohmicinputimpedanceoftheTDA4887PSallowsthe coupling capacitor to be relatively small (10 nF recommended).Thecouplingcapacitoralsofunctionsasa storage capacitor between clamping pulses. Very small input currents will discharge the coupling capacitor resulting in black output signals for missing input clamping pulses.

Composite signals will not disturb normal operation because a clipping circuit cuts all signal parts below black level.

and should not exceed 1 V. The

i(b-w)

TDA4887PS

ThebrightnesssettingisalsovalidforOSDsignals.During blanking and output clamping the video black level will be blanked to the reference black level (brightness blanking). The brightness information is inserted before the gain potentiometers, background colour temperature will not change with brightness setting (grey scale tracking).

7.2.2.2 Brightness control without grey scale tracking

Brightness control without grey scale tracking is selected when control bit BRI = 1.

The brightness information will be mixed with the DAC outputs for external black level restoration (FPOL = 1, AC-coupled cathodes) or internal feedback reference voltages (FPOL = 0, DC-coupled cathodes). This allows a simplebus-controlledbrightnesssettingwithoutgreyscale tracking. With AC-coupled cathodes this is equivalent to brightness control via grid G1.

7.2.3 GAIN CONTROL AND GREY SCALE TRACKING The gain control is driven by an 8-bit DAC via the I2C-bus.

A fast signal blanking circuit included in the input stage is driven by several blanking pulses (see Section 7.6) and control bit DISV = 1. During the off condition the internal reference black level is inserted instead of the input signals.

7.2 Electronic potentiometer stages

7.2.1 CONTRAST CONTROL The contrast control is driven by an 8-bit DAC via the

I2C-bus. The input signals related to the internal reference black level can be adjusted simultaneously by contrast control with a control range of 32 dB (typical). The nominal setting is for maximum contrast.

7.2.2 BRIGHTNESS CONTROL

7.2.2.1 Brightness control with grey scale tracking

The brightness control is driven by an 8-bit DAC via the I2C-bus; brightness control with grey scale tracking is selected when control bit BRI = 0.

With brightness control, the video black level is shifted in relation to the reference black level simultaneously for all three channels. With a negative setting (up to 10% of the maximum signal amplitude) dark signal parts will be lost in ultrablack;forpositivesettings(upto33%of the maximum signal amplitude) the background will alter from black to grey. At nominal brightness setting (40H) there is no shift.

Gain control is used for white point adjustment (correction for different voltage-to-light amplification of the three colour channels) and therefore individually for R, G and B. The video signals related to the reference black level can be gain-controlled within a range of 14 dB (typical). This range is large enough to accommodate the maximum output amplitude for different applications. The nominal setting is maximum gain. The gain setting is also valid for OSD signals and brightness shift (BRI = 0), therefore the complete ‘grey scale’ is effected by gain control.

7.3 Output stage

In the output stage the nominal input signal will be amplifiedtoprovide a 4.6 V (typical) output colour signal at maximumcontrastandmaximumgainsettings.Reference or pedestal black levels are adjusted by output clamping. In order to achieve fast rise and fall times of the output signals with minimum crosstalk between the channels, each signal stage has its own supply voltage pin.

2001 Oct 19 8

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video preampliﬁer

7.4 Pedestal blanking

The pedestal blanking is driven by a 2-bit DAC via the I2C-bus. Pedestal blanking inserts a negative output level related to the reference black level (should always correspond to the ‘extended cut-off voltage’ at the cathode) during blanking and output clamping. In this way retrace lines during vertical flyback are suppressed (blanking to spot cut-off). The depth of pedestal blanking (voltage difference between reference black level and pedestal black level) is bus-controlled (2 bits, 0 to 13.5% of the maximum colour signal) and does not change with any other control or adjustment. The pedestal blanking level is used for output clamping instead of the reference black level (see Section 7.5). If the pedestal blanking level is the most negative output signal and if the application is for AC-coupled cathodes, a very simple black level restoration with a DC diode clamp can be used.

7.5 Output clamping and feedback references

Theaimoftheoutputclampingistosetthereferenceblack level of the signal outputs to a value which corresponds to the ‘extended cut-off voltage’ of the CRT cathodes. With missing output clamping pulses the integrated storage capacitors will be discharged resulting in output signals going to switch-off voltage. If using pedestal blanking, the pedestal black level will be controlled by output clamping (see Fig.5). It is therefore not allowed to change the pedestal depth after black level adjustment of the monitor.

Feedback references are driven via the I2C-bus and controlled by an 8-bit DAC for DC feedback references or by a 3-bit DAC for AC feedback references:

1. DC-coupled cathodes (control bit FPOL = 0) Thecathodevoltageisdividedbyavoltage divider and

fed back to the IC (pins FB/R1, FB/R2and FB/R3). During the output clamping pulse it is compared with a bus-controlled feedback reference voltage with a range of approximately 5.75 to 3.95 V. Any difference will lead to a reference black level correction (subaddress 0BH = 00H) or pedestal black level correction (subaddress 0BH ≠ 00H) by charging or discharging the integrated capacitors that store the black level information between the output clamping pulses. The DC voltages of the output stages should be designed in such a way that the reference black level/pedestal black level is within the range of

0.5 to 2.4 V at the preamplifier output.

TDA4887PS

For correct operation it is necessary that there is enough headroom for ultra black signals (negative brightnesssettingandpedestalblanking). Any clipping with the video supply voltage at the cathode can disturb the signal rise/fall times or the black level stabilization.

After power-on, the control bit FPOL is set to logic 1 and all alignment registers are set to logic 0 resulting in the reference black level at its lowest level (0.53 V) with no output signal. Normal operation starts after all data registers have been refreshed via the I2C-bus.

Brightness control with grey scale tracking (control bit BRI = 0) can be used as well as brightness control without grey scale tracking (control bit BRI = 1) using the mixing function of bus-controlled brightness offset (0 to −1.4 V) to feedback reference voltages (see Section 7.2).

2. AC-coupled cathodes (control bit FPOL = 1) For applications with AC-coupled cathodes the signal

outputs are fed back internally. During the output clamping pulse they are compared with a bus controlled feedback reference voltage (0.5 to 1.9 V). These values ensure a good adaptability to both discrete and integrated post amplifiers.

For black level restoration, the DAC outputs (FB/R1, FB/R2and FB/R3) with a range of approximately

3.95 to 5.75 V can be used. Pedestal blanking is recommended because it allows use of a simple restoration circuit. After power-on, the DAC outputs will be at maximum output voltage (register value logic 0),sowhenusinganon-invertingamplifierforthe reference voltages the monitor will start with black.

Brightness control with grey scale tracking (control bit BRI = 0) can be used as well as simple brightness control without grey scale tracking (control bit BRI = 1) using the mixing function of bus controlled brightness offset (0 to −1.4 V) to DAC output voltages (see Section 7.2).

2001 Oct 19 9

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video preampliﬁer

7.6 Clamping and blanking pulses

There are two pins for clamping and blanking purposes (pins CLI and HFB):

1. Pin CLI (input clamping, vertical blanking) The pin CLI of TDA4887PS can be connected directly

to pin CLBL of e.g. TDA4855 sync processor for input clamping pulses and vertical blanking pulses.

Input clamping pulses and blanking pulses are completely separated from the sandcastle input, that means there is normally (outside detected vertical blanking) no blanking during input clamping and the clamping pulse is not suppressed during vertical blanking.

The input pulse is scanned with two thresholds: a) 1.4 V (typical) for vertical blanking b) 3 V (typical) for input clamping. In order to separate the vertical blanking pulse from

the sandcastle pulse it is necessary that the input clamping pulse has rise/fall times faster than 75 ns/V during the transition from 1.2 to 3.5 V and vice versa. Theleadingedgeoftheinternalverticalblankingpulse is delayed by typically 270 ns (after the end of an input clampingpulseorthebeginningofaseparateblanking pulse), the trailing edge is delayed by typically 115 ns.

During the vertical blanking pulse signal blanking, brightness blanking and pedestal blanking will be activated. In buffered mode, the leading edge of the internal vertical blanking pulse is used to synchronize data transmitted via the I2C-bus (see Section 7.10.1).

For correct input clamping the input signals have to be at black level during the input clamping pulse.

2. Pin HFB (output clamping and blanking) The input pulse (e.g. horizontal flyback pulse) is

scanned with two thresholds. If the input pulse exceeds the first threshold (typically 1.4 V) signal blanking, brightness blanking and pedestal blanking will be activated. If the input pulse exceeds the second threshold (typically 3 V) output clamping will be activated additionally.

Especially for applications with DC-coupled cathodes (FPOL = 0), it is useful that the leading edge of the (internal) clamping pulse is slightly delayed with respect to the leading edge of the (internal) blanking pulse in order to avoid initial misclamping due to the delay of the feedback signal from the cathodes.

TDA4887PS

7.7 On Screen Display insertion and OSD contrast

On Screen Display (OSD) insertion and OSD contrast are controlled by a 4-bit DAC driven via the I2C-bus.

If the fast blanking input signal at pin FBL exceeds the threshold (typically 1.4 V) the input signals are blanked (signal blanking) and OSD signals are enabled. Then, any signal at pins OSD1, OSD2 or OSD3 exceeding the same threshold will create an insertion signal with an amplitude of 100% of the maximum colour signal. The amplitude can becontrolled by OSD contrast (driven via the I2C-bus)with a range of 12 dB. The OSD signals are inserted at the samepoint as the contrast-controlled input signals andwill be treated with brightness and gain control as with normal input signals.

Identical pulses at OSD signal input pins and FBL have to be handled very carefully. Each difference in pulse delay at the inputs will produce glitches at pulse edges at signal outputs.

When control bit DISO = 1 the OSD signal insertion and fast blanking (pin FBL) are disabled.

7.8 Subcontrast adjustment, contrast modulation and beam current limiting

The pin LIM is a linear contrast control pin which allows subcontrastsetting,contrastmodulationandbeamcurrent limiting. The maximum contrast is defined by the actual I2C-bus setting. Input signals at pin LIM act on video and OSD signals and do not affect the contrast bit resolution. If the pin is not used it should be decoupled with a capacitor or tied to the supply voltage.

7.8.1 BEAM CURRENT LIMITING

The open-circuit voltage is approximately 5 V, contrast reduction starts at input voltages <4.4 V (typical) and signal amplification will be reduced with descending input voltages. The input resistance of pin LIM is very high to makeitpossibletochooseatimeconstant sufficient for the open-circuit voltage to recover through the application.

7.8.2 SUBCONTRAST

In order to fit the maximum signal amplification to the post amplifier gain, an input voltage of <4.4 V can be used.

7.8.3 CONTRAST MODULATION

To achieve brightness uniformity over the screen, scan dependent contrast modulation is possible. The nominal input voltage should be <4.4 V having enough margin for positive and negative modulation.

2001 Oct 19 10

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video preampliﬁer

7.9 I2C-bus control

The TDA4887PS contains an I2C-bus receiver for several control functions:

• Contrast register with control bits BRI, FPOL, DISV and DISO

• Brightness control with 8-bit DAC

• Contrast control with 8-bit DAC

• OSD contrast control with 4-bit DAC

• Gain control for each channel with 8-bit DAC

• Internal feedback reference and external reference

voltage control for each channel with 8-bit DAC

• Black level for AC coupling with 3-bit DAC

• Depth of pedestal blanking with 2-bit DAC.

After power-up and after internal power-on reset of the I2C-bus, the registers are set to the following values (for most applications these settings guarantee a blackscreen after power-up):

• Control bit FPOL set to logic 1

• Control bits BRI, DISVand DISO set to logic 0

• All other alignment registers set to logic 0 (minimum

value for control registers).

After an intermediate power dip, all registers are set to theirinitial values and an internal Power-on reset bit will be set with the consequence that the device will give no acknowledge on the data byte after being first addressed. The Power-on reset bit will be reset if the control register is addressed. It is recommended to then refresh all registers by using the auto-increment function.

TDA4887PS

7.10 I2C-bus data buffer

7.10.1 BUFFERED MODE Adjustmentsvia the I2C-busare synchronized with vertical

blanking pulse at CLI:

• Most significant bit (MSB) of subaddress is set to logic 1

• Only one I2C-bus transmission in buffered mode is

accepted before the start of the vertical blanking pulse; following transmissions receive no acknowledge

• Received data is stored in one internal 8-bit buffer

• Adjustments will take effect with detection of the first

vertical blanking pulse after the end of the acknowledged I2C-bus transmission

• Waiting for vertical blanking pulse in buffered mode can be interrupted by Power-on reset

• Auto-increment is not possible

• Buffered mode should be used for user adjustments

such as contrast, OSD contrast and brightness when a picture is visible on the monitor.

7.10.2 DIRECT MODE

Adjustments via the I2C-bus take effect immediately:

• Most significant bit (MSB) of subaddress is set to logic 0

• Number of I2C-bus transmissions in direct mode is

unlimited

• Adjustments take effect directly at the end of each I2C-bus transmission

• Direct mode can be used for all adjustments but large changes of control values may appear as visual disturbances in the picture on the monitor

• Auto-increment is possible

• Vertical blanking pulse is not necessary.

2001 Oct 19 11

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

TDA4887PS

preampliﬁer

8 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

P(n)

i(n)

ext

o(n)(av)

o(n)(M)

tot

stg

amb

ESD

supply voltage (pin 7) 0 8.8 V supply voltage; channels 1, 2 and 3

0 8.8 V

(pins 21, 18 and 15) input voltage; channels 1, 2 and 3

−0.1 V

(pins 6, 8 and 10) external DC voltage applied to

pins 1 to 4 −0.1 V pins 5 and 11 −0.1 V pins 12 and 13 −0.1 V pins 23, 20 and 17 −0.1 V

+ 0.7 V

P P

+ 0.7 V

pins 22, 19 and 16 note 1 note 1 pin 24 −0.1 V

averageoutput current; channels 1, 2 and 3

− 20 mA

(pins 22, 19 and 16) peak output current channels 1, 2 and 3

− 50 mA

(pins 22, 19 and 16) total power dissipation − 1400 mW storage temperature −25 +150 °C ambient temperature −20 +70 °C junction temperature −25 +150 °C electrostatic handling voltage for all pins

machine model note 2 −250 +250 V human body model note 3 −3000 +3000 V

Notes

1. No external voltages.

2. Equivalent to discharging a 200 pF capacitor via a 0.75 µH inductance (

3. Equivalent to discharging a 100 pF capacitor via a 1500 Ω series resistor (

“SNW-FQ-302B”

“SNW-FQ-302A”

9 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R R

th(j-a) th(j-c)

thermal resistance from junction to ambient in free air 55 K/W thermal resistance from junction to case 5 K/W

2001 Oct 19 12

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

TDA4887PS

preampliﬁer

10 CHARACTERISTICS

All voltages and currents are measured in a dedicated test circuit (see Fig.17) optimized for best high frequency performance; all voltages are measured with respect to GND (pins 9 and 14); VP=V T

=25°C; nominal input signals [0.7 V (p-p) at pins 6, 8 and 10]; maximum colour signals at signal outputs (pins 22,

amb

19 and 16); reference black level (V

) approximately 0.7 V; nominal setting for brightness; maximum settings for

bl(ref)

OSD contrast, contrast and gain; no subcontrast, modulation of contrast or limiting (V (pin 1 connected to ground); notes 1 to 3; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V V

P P(SO)

supply voltage (pin 7) 7.6 8.0 8.8 V supply voltage threshold at

note 1 6.8 7.0 7.2 V pin 7 at which signal outputs are switched off

P(n)

supply current (pin 7) note 4 − 25 30 mA supply voltage; channels 1,

7.6 8.0 8.8 V

2 and 3 (pins 21, 18 and 15)

P(n)

supply current; channels 1, 2 and 3 (pins 21, 18 and 15)

pins 22, 19 and 16

open-circuit;

bl(n)(ref)

= 0.7 V;

− 20 25 mA

notes 4 and 5

Input clamping and vertical blanking input, validation of buffered I

CLI

input clamping and vertical blanking input signal

notes 6 and 7

no vertical blanking,

C-bus data (CLI; pin 5)

−0.1 − +1.2 V

no input clamping vertical blanking,

1.6 − 2.6 V

no input clamping input clamping,

3.5 − V

no vertical blanking

CLI

input current V

=1V −−0.2 −µA

CLI

pin 5 connected to ground;

−80 −45 −30 µA

note 8

= −0.1 V; note 8 −250 −135 −100 µA

CLI

r/f5

rise/fall time for input

note 6; see Fig.7 −−75 ns/V clamping pulse; disable for vertical blanking

W(CLI)

width of input clamping

200 −− ns

pulse

W(I2C)(valid)

d(I2C)(valid)

width of vertical blanking pulse for validation of buffered I2C-bus data

delay between leading edge of vertical blanking pulse and validation of buffered I2C-bus data

leading and trailing edge

threshold V

CLI

= 1.4 V;

note 7

I2C-bus buffered mode

transmission completed;

leading edge threshold

= 1.4 V; note 7;

CLI

10 −− µs

−−2µs

see Fig.7

= 8 V (pins 7, 21, 18 and 15);

P1,2,3

≥ 5 V); no OSD fast blanking

LIM

2001 Oct 19 13

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

TDA4887PS

preampliﬁer

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

dead(I2C)

dl5

dt5

Output clamping and blanking input (HFB; pin 11)

HFB

W(HFB)

Video signal inputs; channels 1, 2 and 3 (pins 6, 8 and 10)

i(n)(b-w)

i(n)

Signal blanking

ct(blank)

I2C-bus receiver dead time after synchronizing vertical blanking pulse following a completed I2C-bus buffered mode transmission

delay between leading edges of vertical blanking input pulse and signal blanking at signal outputs

delaybetween trailing edges of vertical blanking input pulse and signal blanking at signal outputs

output clamping and blanking input signal

input current V

width of output clamping pulse

input voltage; black-to-white value (pins 6, 8 and 10)

DC input current (pins 6, 8 and 10)

crosstalk suppression from input to output during blanking

leading edge threshold

= 1.4 V; note 7

CLI

< 0.8 V; input pulse

HFB

15 −− µs

− 270 − ns rising and falling edges = 50 ns/V; threshold for vertical blanking with rising edge V

= 1.4 V; threshold

CLI

for vertical blanking with falling edge V

CLI

=3V;

see Fig.7 V

< 0.8 V; input pulse

HFB

− 115 − ns falling edge = 50 ns/V; threshold V

CLI

= 1.4 V;

see Fig.7

note 9

no blanking, no output

−0.1 − +0.8 V

clamping blanking, no output

2 − 2.6 V

clamping blanking, output clamping 3.5 − V

= 0.8 V −−0.4 −µA

HFB

pin 11 connected to ground;

−80 −45 −30 µA

note 8 V

= −0.1 V; note 8 −250 −135 −100 µA

HFB

=3V 1 −− µs

HFB

− 0.7 1.0 V

no input clamping; V

i(n)=Vi(n)(clamp)

= −20 to +70 °C

amb

;

during input clamping; V

i(n)=Vi(n)(clamp)

±0.7 V

control bit DISV = 1;

0.02 0.20 0.35 µA

±350 ±420 ±500 µA

20 −− dB

f = 80 MHz control bit DISV = 1;

10 −− dB

f = 120 MHz

2001 Oct 19 14

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

TDA4887PS

preampliﬁer

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Clipping of negative input signals (measured at signal outputs)

∆V

clipp

offset during sync clipping related to maximum colour signal

Contrast control; see Fig.8 and note 11

colour signal related to maximum colour signal

∆G

track

tracking of output colour signals of channels 1,

2 and 3 Fast blanking (pin 1) and OSD signal insertion; channels 1, 2 and 3 (pins 2, 3 and 4); note 13 V

FBL

fast blanking input signal

(pin 1)

OSDn

OSD input signal

(pins 2, 3 and 4)

r(OSDn)

rise time of OSD colour

signals (pins 22, 19 and 16) t

f(OSDn)

fall time of OSD colour

signals (pins 22, 19 and 16) t

g(n)(CO)

width of (negative going)

OSD signal insertion glitch,

leading edge

(pins 22, 19 and 16) t

g(n)(OC)

width of (negative going)

OSD signal insertion glitch,

trailing edge (pins 22, 19

and 16) δV

OSDn

overshoot/undershoot of

OSD colour signal related to

actual OSD output pulse

amplitude (pins 22, 19

and 16) V

OSDn(max)

maximumOSD colour signal

related to maximum colour

signal (pins 22, 19 and 16)

i(n)=Vi(n)(clamp)

;

− 0.6 1.2 % sync amplitude = 0.3 V; note 10; see Fig.3

FFH (maximum) − 0 − dB 00H (minimum) −−45 − dB FFH to 40H; note 12 − 0 0.5 dB

no video signal blanking;

0 − 1.1 V OSD signal insertion disabled

video signal blanking;

1.7 − V

OSD signal insertion enabled

> 1.7 V

FBL

no internal OSD signal

0 − 1.1 V

insertion internal OSD signal

1.7 − V

insertion

10 to 90% amplitude; pulse

− 34 ns

leading edge = 1.2 ns/V 90 to 10% amplitude; pulse

− 47 ns

falling edge = 1.2 ns/V identical pulses at fast

046ns blanking input (pin 1) and OSD signal inputs (pins 2, 3 and 4)

identical pulses at fast

056ns blanking input (pin 1) and OSD signal inputs (pins 2, 3 and 4)

pulse with 1.2 ns/V at OSD

− 610 % signal inputs (pins 2, 3 and 4)

maximum OSD contrast;

90 96 110 %

maximum gain

2001 Oct 19 15

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

TDA4887PS

preampliﬁer

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

OSD contrast control; see Fig.9 and note 14

OSD colour signal related to maximum OSD colour signal

Subcontrast adjustment, contrast modulation and beam current limiting (pin 24); see Fig.8 and note 15 V

LIM(nom)

LIM(start)

nominal input voltage pin 24 open-circuit 4.7 5.0 5.3 V starting voltage for linear

contrast and OSD contrast reduction

LIM(stop)

stop voltage for linear contrast and OSD contrast reduction

LIM

bandwidth of contrast modulation

LIM(max)

maximum input current V Brightness control; see Figs 10, 12 and 14 and notes 16 and 17 ∆V

bl(n)

difference between video

black level and reference

black level at signal outputs

related to maximum colour

signal ∆V

DA(n)

DAC output voltage shift

(pins 23, 20 and 17)

Gain control; see Fig.11 and note 18

video signal related to video

signal at maximum gain Pedestal blanking; see Fig.5 and note 19

∆V

bl(n)(PED-VID)

difference between pedestal

black level and video black

level at nominal brightness,

measured at signal outputs

(pins 22, 19 and 16) related

to maximum colour signal

0FH (maximum) − 0 − dB 00H (minimum) −14 −12 −10 dB

4.2 4.4 4.8 V

−40 dB below maximum

1.5 2.0 2.5 V colour signal (contrast setting FFH)

−3dB 4 −− MHz

=0V −1 − +1 µA

LIM

FFH (maximum); BRI = 0 28 33 38 % 40H (nominal); BRI = 0 −2 0 +2 % 00H (minimum); BRI = 0 −12 −10 −8%

FPOL = 1, see DAC output voltages for AC coupling or feedback reference voltage shift; FPOL = 0, see internal feedback reference voltage for DC coupling

FFH (maximum); BRI = 1 −−1.4 − V 00H (minimum); BRI = 1 − 0 − V

FFH (maximum) − 0 − dB 00H (minimum) −15 −13.5 −12.5 dB

03H (maximum) −12 −13.5 − % 02H −8 −9 − % 01H −4 −4.5 − % 00H (minimum) − 0 − %

2001 Oct 19 16

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

TDA4887PS

preampliﬁer

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Signal outputs; channels 1, 2 and 3 (pins 22; 19 and 16)

o(n)(min)

minimum output voltage level (pins 22, 19 and 16)

o(n)(max)

maximum output voltage level (pins 22, 19 and 16)

arbitrary input signals, contrast, brightness and gain adjustments; without load

o(n)(source)(max)

maximum output source current (pins 22, 19 and 16)

o(n)

output resistance (pins 22, 19 and 16)

o(n)(b-w)(max)

maximum output voltage swing (black-to-white value); channels 1, 2 and 3

maximum contrast; maximum gain; V

= 0.7 V; RL=2kΩ

i(n)(b-w)

(pins 22, 19 and 16)

o(n)(source)(M)

o(n)(sink)(M)

peak output source current (pins 22, 19 and 16)

peak output sink current (pins 22, 19 and 16)

during fast positive signal transients

during fast negative signal transients

S/N signal-to-noise ratio note 20 48 −− dB

Frequency response at signal outputs; channels 1, 2 and 3 (pins 22, 19 and 16)

r(n)

rise time of fast transients (pins 22, 19 and 16)

input rise time=1ns; 10 to 90% amplitude; RL=10kΩ; notes 21, 22 and 23;

2.8 V (p-p) signal amplitude; C

=5pF

4.5 V (p-p) signal amplitude; C

=5pF

4.5 V (p-p) signal

f(n)

fall time of fast transients (pins 22, 19 and 16)

amplitude; C

input fall time = 1 ns; 90 to 10% amplitude;

=11pF

RL=10kΩ; notes 21, 22 and 23;

2.8 V (p-p) signal amplitude; C

=5pF

4.5 V (p-p) signal amplitude; C

=5pF

4.5 V (p-p) signal amplitude; C

=11pF

0.01 0.05 0.1 V

− 2 − V

P(n)

− 1V

P(n)

−15 −− mA

65 75 90 Ω

4.2 4.6 4.9 V

−40 −− mA

−−20 mA

− 2.7 3.8 ns

− 3.2 4.2 ns

− 3.8 4.5 ns

− 3.6 4.5 ns

− 56 ns

2001 Oct 19 17

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

TDA4887PS

preampliﬁer

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

δV

o(n)

Crosstalk at signal outputs; channels 1, 2 and 3 (pins 22, 19 and 16)

ct(tr)(n)

ct(f)

Internal feedback reference voltage for DC coupling; see Fig.12 and note 26 V

ref(DC)

Output clamping, feedback inputs for DC coupling; FB/R1, FB/R2 and FB/R3 (pins 23, 20 and 17)

overshoot of output signal pulse related to actual output pulse amplitude (pins 22, 19 and 16)

undershoot of output signal pulse related to actual output pulse amplitude (pins 22, 19 and 16)

transient crosstalk suppression (pins 22, 19 and 16)

crosstalk suppression by frequency

internal reference voltage for negative feedback polarity (without brightness control)

internal reference voltage for negative feedback polarity (with brightness control, see also brightness control ∆V

DA(n)

)

input rise time=1ns;

−−10 % maximum colour signal

input fall time = 1 ns;

−−10 % maximum colour signal

input rise/fall time = 1 ns;

10 −− dB

note 24

f = 50 MHz; note 25 25 −− dB f = 100 MHz; note 25 10 −− dB

FFH; FPOL = 0; BRI = 0 3.7 3.95 4.1 V 00H; FPOL = 0; BRI = 0 5.6 5.75 5.9 V

FFH; FPOL = 0; BRI = 1;

2.3 2.55 2.7 V maximum brightness

00H; FPOL = 0; BRI = 1;

5.6 5.75 5.9 V minimum brightness

FB/Rn(max)

bl(n)(ref)(min)

bl(n)(ref)(max)

∆V

bl(CRT)

∆V

bl(n)(lf)

maximum input current (pins 23, 20 and 17)

during output clamping; V

HFB

> 3.5 V;V

FB/Rn

= 0.5 V;

−500 −200 −60 nA

FPOL = 0

minimum reference black

> 3.5 V; FPOL = 0 0.01 0.1 0.5 V

HFB

level/minimum pedestal black level (pins 22, 19 and 16)

maximum reference black

> 3.5 V; FPOL = 0 2.0 2.8 4.0 V

HFB

level/maximum pedestal black level (pins 22, 19 and 16)

black level variation at CRT FPOL = 0; note 27 −−200 mV black level decrease

between clamping pulses

FPOL = 0; f δ = 10%

= 60 kHz;

line

− 0.1 − %

related to maximum colour signal (pins 22, 19 and 16)

2001 Oct 19 18

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

TDA4887PS

preampliﬁer

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Output clamping; internal feedback (of signal outputs) reference voltage for AC coupling;

see Fig.13 and note 28 V

bl(n)(ref)

reference black level voltage/pedestal black level voltage (pins 22, 19 and 16)

DAC output voltages for AC coupling; FB/R

FB/Rn

DAC output voltage (without brightness control)

DAC output voltage (with brightness control, see also brightness control ∆V

FB/Rn

FB/Rn(sink)(max)

FB/Rn(source)(max)

C-bus inputs; SDA (pin 12), SCL (pin 13); note 30

SCL

SDA(ack)

output resistance FPOL = 1 − 100 −Ω maximum sink current FPOL = 1 −−400 µA maximum source current FPOL = 1 −−200 −µA

SCL clock frequency −−100 kHz LOW-level input voltage 0 − 1.5 V HIGH-level input voltage 3 − 5V LOW-level input current VIL=0V −10 −− µA HIGH-level input current VIH=5V −10 −− µA LOW-level output voltage during acknowledge 0 − 0.4 V SDA output current (pin 12)

DA(n)

during acknowledge

o(f)

th(POR)(r)

th(POR)(f)

output fall time V

threshold for Power-on resetonrising supply voltage − 1.5 2.0 V

threshold for Power-on reset off

> 3.5 V; FPOL = 1

HFB

00H (minimum) 0.47 0.53 0.59 V 0FH (maximum) 1.83 1.89 1.95 V

, FB/R2 and FB/R3 (pins 23, 20 and 17); see Fig.14 and note 29

FFH; FPOL = 1; BRI = 0 3.7 3.95 4.1 V 00H; FPOL = 1; BRI = 0 5.6 5.75 5.9 V FFH; FPOL = 1; BRI = 1;

2.3 2.55 2.7 V maximum brightness

)

00H; FPOL = 1; BRI = 1;

5.6 5.75 5.9 V minimum brightness

VOL= 0.4 V 3 −− mA V

= 0.6 V 6 −− mA

= 3 to 1.5 V; bus

SDA

capacitance C

SDA

= 400 pF

−−250 ns

falling supply voltage − 3.5 − V rising supply voltage −−7V falling supply voltage − 1.5 − V

2001 Oct 19 19

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

TDA4887PS

preampliﬁer

Notes to the characteristics

1. Definition of levels (see Figs 3 to 5) Reference black level:this is the level to which the input level is clamped during the input clamping pulse

> 3.5 V). It is used internally as a reference for the gain settings. It can be observed on the outputs:

CLI

a) When the input is at black and the brightness setting is nominal (subaddress 01H = 40H) or control bit BRI = 1 b) During output blanking and clamping (V

(subaddress 0BH = 00H).

Video black level:this is the black level of the actual video. At the input it is still equal to the reference black level.

At the output it may deviate from it according to the brightness setting. Contrast setting leaves the video black level unaltered. Gain setting biases the video black level due to its influence on brightness. This is important for correct

grey scale tracking. It can be observed at the outputs when the input is at black outside output blanking and clamping pulses (V

HFB

< 0.8 V).

Pedestal black level: this is anultra black level which deviates from the reference black level by a bus controlled

amount. It can be observed at the output during output blanking and clamping (V 0BH ≠ 00H).

Switch-off voltage: this is the lowest signal voltage at outputs. The signals will be switched off by discharging the internalblack level storage capacitors if thesupply voltage is less than V

the input is at black, the brightness setting is nominal and VP< 6.8 V (subaddress 01H = 40H). Blanking level: this level equals reference black (subaddress 0BH 1= 00H) or pedestal black. It can be observed at

the outputs during output blanking and clamping (V

2. Explanation to black level adjustment:

The three reference black levels are aligned correctly when they are made equal to the ‘extended cut-off levels’ of the three cathodes. Full raster and spot cut-off can only beachieved by enabling the pedestalblanking or by applying a negative pulse to the grid G1.

Negative feedback for DC-coupled cathodes (control bit FPOL = 0): the actual blanking level on the outputs depends on the external feedback application for output clamping. The loop will function correctly only if it is within the control range of V

bl(n)(ref)(min)

to V

bl(n)(ref)(max)

blanking in a given application will not affect the blanking level, but instead shifts the video (and needs re-alignment of the three black levels).

Positive feedback for AC-coupled cathodes (control bit FPOL = 1): the feedback loop for output clamping is closed internally. The actual blanking level is bus controlled between 0.53 and 1.89 V (subaddress 0AH). It should be noted that changing pedestal blanking will not affect the blanking level, but instead shifts the video (and re-alignment of the three black levels is needed).

3. Definition of output signals (see Fig.6):

Colour signal: all positive voltages are referenced to black level at signal outputs. Maximum colour signal:colour signal with nominal input signal 0.7V

gain setting.

Video signal: all positive voltages referred to reference black level at signal outputs. The video signal is the superimposing of the brightness information (∆Vbl) and the colour signal.

4. The total supply current I

P(tot)=IP+IP1+IP2+IP3

4.4 mA/V and varies in the temperature range from −20 to +70 °C by approximately ±5% (V

5. The channel supply current IP1,IP2,IP3depends on the signal output current IO1,IO2,IO3, the channel supply voltage

P1,VP2,VP3

P(n)IPxIO(n)

and the signal output voltage VO1,VO2,VO3. With IPx=I

4.4 mA/V V

8V–()× 1 mA/V V

P(n)

> 3.5 V) if the pedestal blanking depth is set to zero

HFB

> 3.5 V; subaddress

HFB

.It can be observed at theoutputs when

P(SO)

> 3.5 V).

HFB

at pins 22, 19 and 16. It should be noted that changing pedestal

, maximum contrast setting and maximum

i(b-w)

depends on the supply voltage with a factor of approximately

= 0.7 V).

O(n)

at I

P(n)

0.7 V–()×–++≈

O(n)

= 0, V

= 8 V and V

P(n)

O(n)

= 0.7 V:

2001 Oct 19 20

Philips Semiconductors Product speciﬁcation

160 MHz bus-controlled monitor video

TDA4887PS

preampliﬁer

6. Pin 5should be used for input clamping and blanking during verticalretrace (signal blanking, brightness blanking and

pedestal blanking). With a fast clamping pulse (transition between V 75 ns/V) no blanking will occur during input clamping.

For 75 ns/V < t

≤ 280 ns/V the generation of the internal blanking pulse is uncertain. For t

r/f5

internal blanking pulse will be generated. If pin 5 is open-circuit, it will activate permanent input clamping and undefined blanking.

7. Pin 5 can be used to synchronize all adjustments via the I2C-bus (one by one). With a completed I2C-bus

transmission in buffered mode, only the leading edge of a vertical blanking pulse activates an adjustment (see also Section 7.10).

After the adjustment has been activated (validation of buffered I2C-bus data) the I2C-bus will be reset and further transmissions in direct or buffered mode are enabled.

I2C-bus transmissions in direct mode need no synchronization pulses.

8. Input voltages less than −0.1 V can produce internal substrate currents which disturb the leakage currents at the

signal inputs. An internal protection circuit creates a current for pin voltages of approximately 0 V or with negative voltage. Feeding clamping and blanking pulses via a resistor (several kΩ) protects the pin from negative voltages.

9. Pin 11shouldbeusedforoutput clamping and/or blanking. If pin 11 is open-circuit, it will activate permanent blanking

and output clamping.

10. Composite signals will not disturb normal operations because an internal clipping circuit cuts all signal parts below

input reference black level (see Fig.3).

11. Contrast control acts on internal colour signals under I

C-bus control; subaddress 02H (bit resolution 0.4% of

contrast range).

= 1.2 to 3.5 V and 3.5 to 1.2 V in less than

CLI

> 280 ns/V the

r/f5

∆G

12.

track

: colour signal output amplitude in channel n = 1, 2 or 3 at any contrast setting.

: colour signal output amplitude in channel n = 1, 2 or 3 at maximum contrast setting and same gain setting.

20 maximum of

× dB=



log

 



-------- -



-------- A

log

13. When OSD fast blanking is active and OSD inputs OSD



-------- -



-------- A

, OSD2and OSD3are HIGH (V



log

-------- -



-------- A

> 1.7 V, V

FBL

OSD(n)

> 1.7 V) the OSD colour signals will be inserted in front of the gain potentiometers. This ensures a correct grey scale of all video signals. The amplitudes of the inserted OSD signals can be controlled simultaneously by OSD contrast via the I2C-bus.

The inserted black level change (∆Vbl) due to brightness control is not affected by OSD fast blanking.

14. OSD contrast control acts on inserted OSD colour signals under I2C-bus control; subaddress 03H (bit resolution

6.7% of OSD contrast range).

15. This pin can be used for subcontrast adjustment, beam current limiting and contrast modulation. Both the video and OSD contrast are reduced simultaneously (see Figs 8 and 9). Because of the high-ohmic input impedance the pin should be tied to a voltage of more than 5 V or decoupled with a capacitor (several nF) if not used.

16. Brightness control adds an I2C-bus controlled DC offset to the internal colour signal; subaddress 01H (bit resolution

0.4% of brightness range). When control bit BRI = 1 the internal gain dependent brightness control is switched off and the feedback reference voltages (control bit FPOL = 0) or DAC output voltages for DC restoration (control bit FPOL = 1) at the cathodes are shifted with brightness control.

17. The voltage difference between video black level and reference black level is related to the colour signal (see note 3) with nominal 0.7 V (p-p) input signal, at maximum contrast (subaddress 02H = FFH) and for any gain setting. This voltage difference (in Volts) is proportional to the gain setting (grey scale tracking). Therefore ∆Vbl(in percent) is constant for any gain setting.The given values of ∆Vblare valid only for video blacklevels higher than the minimum output voltage level V

o(n)(min)

2001 Oct 19 21

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