Philips TDA4856-V2 Datasheet

DATA SH EET

Product speciﬁcation Supersedes data of 1998 Oct 02 File under Integrated Circuits, IC02

1999 Jul 13

INTEGRATED CIRCUITS

TDA4856

C-bus autosync deflection

controller for PC monitors

1999 Jul 13 2

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

FEATURES Concept features

• Full horizontal plus vertical autosync capability

• Extended horizontal frequency range from

15 to 130 kHz

• Comprehensive set of I2C-bus driven geometry adjustments and functions, including standby mode

• Very good vertical linearity

• Moire cancellation

• Start-up and switch-off sequence for safe operation of

all power components

• X-ray protection

• Power dip recognition

• Flexible switched mode B+ supply function block for

feedback and feed forward converter

• Internally stabilized voltage reference

• Drive signal for focus amplifiers with combined

horizontal and vertical parabola waveforms

• DC controllable inputs for Extremely High Tension (EHT) compensation

• SDIP32 package.

Synchronization

• Can handle all sync signals (horizontal, vertical, composite and sync-on-video)

• Output for video clamping (leading/trailing edge selectable by the I2C-bus), vertical blanking and protection blanking

• Output for fast unlock status of horizontal synchronization and blanking on grid 1 of picture tube.

Horizontal section

• I2C-bus controllable wide range linear picture position, pin unbalance and parallelogram correction via horizontal phase

• Frequency-lockedloopforsmoothcatchingofhorizontal frequency

• Simple frequency preset of f

min

and f

max

by external

resistors

• Low jitter

• Soft start for horizontal and B+ control drive signals.

Vertical section

• I2C-bus controllable vertical picture size, picture position, linearity (S-correction) and linearity balance

• Outputfor the I2C-buscontrollable vertical sawtooth and parabola (for pin unbalance and parallelogram)

• Vertical picture size independent of frequency

• Differential current outputs for DC coupling to vertical

booster

• 50 to 160 Hz vertical autosync range.

East-West (EW) section

• I2C-bus controllable output for horizontal pincushion, horizontal size, corner and trapezium correction

• Optional tracking of EW drive waveform with line frequency selectable by the I2C-bus.

Focus section

• I2C-bus controllable output for horizontal and vertical parabolas

• Verticalparabolaisindependentoffrequencyandtracks with vertical adjustments

• Horizontal parabola independent of frequency

• Adjustable pre-correction of delay in focus output stage.

1999 Jul 13 3

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

GENERAL DESCRIPTION

The TDA4856 is a high performance and efficient solution for autosync monitors. All functions are controllable by the I2C-bus.

The TDA4856 provides synchronization processing, horizontal and vertical synchronization with full autosync capability and very short settling times after mode changes. External power components are given a great deal of protection. The IC generates the drive waveforms for DC-coupled vertical boosters such as the TDA486x and TDA835x.

The TDA4856 provides extended functions e.g. as a flexible B+ control, an extensive set of geometry control facilities, and a combined output for horizontal and vertical focus signals.

Together with the I2C-bus driven Philips TDA488x video processor family, a very advanced system solution is offered.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

supply voltage 9.2 − 16 V

supply current − 70 − mA

CC(stb)

supply current during standby mode − 9 − mA VSIZE vertical size 60 − 100 % VGA VGA overscan for vertical size − 16.8 − % VPOS vertical position −±11.5 − % VLIN vertical linearity (S-correction) −2 −−46 % VLINBAL vertical linearity balance −±1.25 − % V

HSIZE

horizontal size 0.13 − 3.6 V V

HPIN

horizontal pincushion (EW parabola) 0.04 − 1.42 V V

HEHT

horizontal size modulation 0.02 − 0.69 V V

HTRAP

horizontal trapezium correction −±0.5 − V V

HCORT

horizontal corner correction at top of picture −0.64 − +0.2 V V

HCORB

horizontal corner correction at bottom of picture −0.64 − +0.2 V HPOS horizontal position −±13 − % HPARAL horizontal parallelogram −±1.5 − % HPINBAL EW pin unbalance −±1.5 − % T

amb

operating ambient temperature −20 − +70 °C

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA4856 SDIP32 plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1

1999 Jul 13 4

Philips Semiconductors Product speciﬁcation

C-bus autosync deﬂection controller for

PC monitors

TDA4856

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BLOCK DIAGRAM

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VERTICAL

SYNC INPUT

AND POLARITY

CORRECTION

VERTICAL

SYNC

INTEGRATOR

VERTICAL

OSCILLATOR

AND AGC

EW OUTPUT

HORIZONTAL PINCUSHION HORIZONTAL CORNER HORIZONTAL TRAPEZIUM HORIZONTAL SIZE

VERTICAL LINEARITY VERTICAL LINEARITY

BALANCE

EHT COMPENSATION

HORIZONTAL AND

VERTICAL SIZE

ASYMMETRIC

EW-CORRECTION

OUTPUT

HORIZONTAL

AND VERTICAL

I2C-BUS

RECEIVER

HUNLOCK

OUTPUT

VERTICAL POSITION VERTICAL SIZE AND

VERTICAL OVERSCAN

VIDEO CLAMPING

AND

VERTICAL BLANK

SUPPLY

AND

REFERENCE

HORIZONTAL OSCILLATOR

PLL1 AND

HORIZONTAL

POSITION

PLL2, PARALLELOGRAM,

PIN UNBALANCE AND

SOFT START

COINCIDENCE DETECTOR

FREQUENCY DETECTOR

I2C-BUS REGISTERS

PROTECTION

AND SOFT START

X-RAY

PROTECTION

HORIZONTAL

OUTPUT

B+

CONTROL

22 kΩ

3.3 kΩ

100 nF

8.2 nF

150

(1%)

10 nF

HBUF

(2%)

HREF

(1%)

(1)

B+ CONTROL APPLICATION

(2)

(TTL level)

9.2 to 16 V

(video)

clamping blanking

23 22 21 31

100

(5%)

VOUT2

VOUT1

ASCOR

32 FOCUS

BDRV BSENS BOP BIN

HDRV

19 18

6 4 3 5

28 29

12 nF

30 1

TDA4856

H/C SYNC INPUT

AND POLARITY

CORRECTION

MGS272

VERTICAL OUTPUT

FOCUS

SDA SCL

HSYNC

SGND

PGND

CLBL

VSYNC

EWDRV

VSMODVAGCVCAPVREF HSMOD

7 V

1.2 V

EHT compensation

via horizontal size

EHT compensation

via vertical size

HFLB

HPLL2HCAPHREFHBUFHPLL1

XSEL XRAY

HUNLOCK

Fig.1 Block diagram and application circuit.

(1) For the calculation of fH range see Section“Calculation of line frequency range”. (2) See Figs 22 and23.

1999 Jul 13 5

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

PINNING

SYMBOL PIN DESCRIPTION

HFLB 1 horizontal ﬂyback input XRAY 2 X-ray protection input BOP 3 B+ control OTA output BSENS 4 B+ control comparator input BIN 5 B+ control OTA input BDRV 6 B+ control driver output PGND 7 power ground HDRV 8 horizontal driver output XSEL 9 select input for X-ray reset V

10 supply voltage EWDRV 11 EW waveform output VOUT2 12 vertical output 2 (ascending sawtooth) VOUT1 13 vertical output 1 (descending sawtooth) VSYNC 14 vertical synchronization input HSYNC 15 horizontal/composite synchronization input CLBL 16 video clamping pulse/vertical blanking output HUNLOCK 17 horizontal synchronization unlock/protection/vertical blanking output SCL 18 I2C-bus clock input SDA 19 I2C-bus data input/output ASCOR 20 output for asymmetric EW corrections VSMOD 21 input for EHT compensation (via vertical size) VAGC 22 external capacitor for vertical amplitude control VREF 23 external resistor for vertical oscillator VCAP 24 external capacitor for vertical oscillator SGND 25 signal ground HPLL1 26 external ﬁlter for PLL1 HBUF 27 buffered f/v voltage output HREF 28 reference current for horizontal oscillator HCAP 29 external capacitor for horizontal oscillator HPLL2 30 external ﬁlter for PLL2/soft start HSMOD 31 input for EHT compensation (via horizontal size) FOCUS 32 output for horizontal and vertical focus

1999 Jul 13 6

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction

HSYNC (pin 15) is the input for horizontal synchronization signals, which can be DC-coupled TTL signals (horizontal or composite sync) and AC-coupled negative-going video sync signals. Video syncs are clamped to 1.28 V and sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to top sync.

For DC-coupled TTL signals the input clamping current is limited. The slicing level for TTL signals is 1.4 V.

The separated sync signal (either video or TTL) is integrated on an internalcapacitor to detect and normalize the sync polarity.

Normalized horizontal sync pulses are used as input signals for the vertical sync integrator, the PLL1 phase detector and the frequency-locked loop.

Vertical sync integrator

Normalized composite sync signals from HSYNC are integrated on an internal capacitor in order to extract vertical sync pulses. The integration time is dependent on the horizontal oscillator reference current at HREF (pin 28). The integrator output directly triggers the vertical oscillator.

Vertical sync slicer and polarity correction

Vertical sync signals (TTL) applied to VSYNC (pin 14) are sliced at 1.4 V. The output signal of the sync slicer is integrated on an internalcapacitor to detect and normalize the sync polarity. The output signals of vertical sync integrator and sync normalizer are disjuncted before they are fed to the vertical oscillator.

Video clamping/vertical blanking generator

The video clamping/vertical blanking signal at CLBL (pin 16) is a two-level sandcastle pulse which is especially suitableforvideoICs such as the TDA488x family, but also for direct applications in video output stages.

The upper level is the video clamping pulse, which is triggeredbythehorizontalsyncpulse.Either the leading or trailing edge can be selected by setting control bit CLAMP via the I2C-bus. The width of the video clamping pulse is determined by an internal single-shot multivibrator.

The lower level of the sandcastle pulse is the vertical blanking pulse, which is derived directly from the internal oscillator waveform. It is started by the vertical sync and stopped with the start of the vertical scan. This results in optimum vertical blanking. Two different vertical blanking times are accessible, by control bit VBLK, via the I2C-bus.

Blanking will be activated continuously if one of the following conditions is true:

Soft start of horizontal and B+ drive [voltage at HPLL2 (pin 30) pulled down externally or by the I2C-bus]

PLL1 is unlocked while frequency-locked loop is in search mode

No horizontal flyback pulses at HFLB (pin 1) X-ray protection is activated Supply voltage at VCC (pin 10) is low (see Fig.24).

Horizontal unlock blanking can be switched off, by control bit BLKDIS, via the I2C-bus while vertical blanking is maintained.

Fig.2 Pin configuration.

handbook, halfpage

TDA4856

MGS273

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

HFLB

XRAY

BOP

BSENS

BIN

BDRV PGND HDRV

XSEL

EWDRV

VOUT2 VOUT1 VSYNC

FOCUS HSMOD HPLL2 HCAP

HBUF HPLL1

HREF

SGND VCAP VREF VAGC VSMOD ASCOR SDA

HSYNC

CLBL

SCL HUNLOCK

1999 Jul 13 7

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Frequency-locked loop

The frequency-locked loop can lock the horizontal oscillatorover a wide frequencyrange. This is achievedby a combined search and PLL operation. The frequency range is preset by two external resistors and the

recommended maximum ratio is

This can, for instance, be a range from 15.625 to 90 kHz with all tolerances included.

Without a horizontal sync signal the oscillator will be free-running at f

min

. Any change of sync conditions is detected by the internal coincidence detector. A deviation of more than 4% between horizontal sync and oscillator frequency switches the horizontal section into search mode.This means that PLL1control currents are switched off immediately. The internal frequency detector then starts tuning the oscillator. Very small DC currents at HPLL1 (pin 26) are used to perform this tuning with a well defined change rate. When coincidence between horizontal sync and oscillator frequency is detected, the search mode is first replaced by a soft-lock mode which lasts for the first part of the next vertical period. The soft-lock mode is then replaced by a normal PLL operation. This operation ensures smooth tuning and avoids fast changes of horizontal frequency during catching.

In this concept it is not allowed to load HPLL1. The frequency dependent voltage at this pin is fed internally to HBUF (pin 27) via a sample-and-hold and buffer stage. The sample-and-hold stage removes all disturbances caused by horizontal sync or composite vertical sync from the buffered voltage. An external resistorconnectedbetweenpins HBUFand HREF defines the frequency range.

Out-of-lock indication (pin HUNLOCK)

Pin HUNLOCK is floating during search mode, or if a protection condition is true. All this can be detected by the microcontroller if a pull-up resistor is connected to its own supply voltage.

For an additional fast vertical blanking at grid 1 of the picture tube a 1 V signal referenced to ground is available at this output. The continuous protection blanking (see Section“Videoclamping/verticalblankinggenerator”) is also available at this pin. Horizontal unlock blanking can be switched off, by control bit BLKDIS via the I2C-bus while vertical blanking is maintained.

Horizontal oscillator

The horizontal oscillator is of the relaxation type and requires a capacitor of 10 nF at HCAP (pin 29). For optimum jitter performance the value of 10 nF must not be changed.

The minimum oscillator frequency is determined by a resistor from HREF to ground. A resistor connected between pins HREF and HBUF defines the frequency range.

The reference current at pin HREF also defines the integration time constant of the vertical sync integration.

Calculation of line frequency range

The oscillator frequencies f

min

and f

max

must first be calculated. This is achieved by adding the spread of the relevant components to the highest and lowest sync frequencies f

sync(min)

and f

sync(max)

. The oscillator is driven

by the currents in R

HREF

and R

HBUF

The following example is a 31.45 to 90 kHz application:

Table 1 Calculation of total spread

Thus the typical frequency range of the oscillator in this example is:

The resistors R

HREF

and R

HBUFpar

can be calculated using

the following formulae:

The resistor R

HBUFpar

is calculated as the value of R

HREF

and R

HBUF

in parallel.

max

min

----------

6.5 1

------- -

spread of for f

max

for f

min

IC ±3% ±5% C

HCAP

±2% ±2%

HREF

, R

HBUF

±2% ±2%

Total ±7% ±9%

maxfsync max()

1.07× 96.3 kHz==

min

sync min()

1.09

-----------------------

28.4 kHz==

HREF

78 kHz k××Ω

min

0.0012 f

min

×+ kHz[]

-----------------------------------------------------------------

2.61 kΩ==

HBUFpar

78 kHz k××Ω

max

0.0012 f

max

×+ kHz[]

--------------------------------------------------------------------

726 Ω==

1999 Jul 13 8

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Theformulae for R

HBUF

alsotakesinto account the voltage

swing across this resistor:

PLL1 phase detector

The phase detector is a standard type using switched current sources, which are independent of horizontal frequency. It compares the middle of horizontal sync with a fixed point on the oscillator sawtooth voltage. The PLL1 loop filter is connected to HPLL1 (pin 26).

See also Section “Horizontal position adjustment and corrections”.

Horizontal position adjustment and corrections

A linear adjustment of the relative phase between the horizontal sync and the oscillator sawtooth (in PLL1 loop) is achieved via register HPOS.Once adjusted, the relative phase remains constant over the whole frequency range.

Correctionof pin unbalance and parallelogramis achieved by modulating the phase between oscillator sawtooth and horizontal flyback (in loop PLL2) via registers HPARAL and HPINBAL. If those asymmetric EW corrections are performed in the deflection stage, both registers can be disconnected from the horizontal phase via control bit ACD. This does not change the output at pin ASCOR.

Horizontal moire cancellation

To achieve a cancellation of horizontal moire (also known as ‘video moire’), the horizontal frequency is divided-by-two to achieve a modulation of the horizontal phase via PLL2. The amplitude is controlled by register HMOIRE. To avoid a visible structure on screen the polarity changes with half of the vertical frequency. Control bit MOD disables the moire cancellation function.

PLL2 phase detector

The PLL2 phase detector is similar to the PLL1 detector and compares the line flyback pulse at HFLB (pin 1) with the oscillator sawtooth voltage. The control currents are independent of the horizontal frequency. The PLL2 detector thus compensates for the delay in the external horizontal deflection circuit by adjusting the phase of the HDRV (pin 8) output pulse.

An external modulation of the PLL2 phase is not allowed, because this would disturb the pre-correction of the horizontal focus parabola.

Soft start and standby

If HPLL2 is pulled to ground, either by an external DC current or by resetting register SOFTST, the horizontal outputpulses and B+ control driver pulseswillbeinhibited. This means that HDRV (pin 8) and BDRV (pin 6) are floating in this state. In both cases PLL2 and the frequency-locked loop are disabled, and CLBL (pin 16) provides a continuous blanking signal and HUNLOCK (pin 17) is floating.

This option can be used for soft start, protection and power-down modes. When pin HPLL2 is released again, anautomatic soft start sequenceon the horizontal driveas well as on the B-drive output will be performed (see Fig.24).

A soft start can only be performed if the supply voltage for the IC is a minimum of 8.6 V.

The soft start timing is determined by the filter capacitor at HPLL2 (pin 30), which is charged with a constant current during soft start. In the beginning the horizontal driver stage generates very small output pulses. The width of these pulses increases with the voltage at HPLL2 until the final duty cycle is reached. The voltage at HPLL2 increases further and performsa soft start at BDRV (pin 6) as well. After BDRV has reached full duty cycle, the voltage at HPLL2 continues to rise until HPLL2 enters its normaloperatingrange.Theinternalchargecurrentisnow disabled. Finally PLL2 and the frequency-locked loop are activated. If both functions reach normal operation, HUNLOCK (pin 17) switches from the floating status to normal vertical blanking, andcontinuous blanking at CLBL (pin 16) is removed.

Output stage for line drive pulses [HDRV (pin 8)]

An open-collector output stage allows direct drive of an inverting driver transistor because of a low saturation voltage of 0.3 V at 20 mA. To protect the line deflection transistor, the output stage is disabled (floating) for a low supply voltage at V

(see Fig.23).

The duty cycle of line drive pulses is slightly dependent on the actual horizontal frequency. This ensures optimum drive conditions over the whole frequency range.

HBUF

HREFRHBUFpar

–

----------------------------------------------

0.8×= 805 Ω=

1999 Jul 13 9

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

X-ray protection

TheX-rayprotectioninputXRAY(pin 2)providesavoltage detector with a precise threshold. If the input voltage at XRAY exceeds this threshold for a certain time, then control bit SOFTST is reset, which switches the IC into protection mode. In this mode several pins are forced into defined states:

HUNLOCK (pin 17) is floating The capacitor connected to HPLL2 (pin 30) is

discharged Horizontal output stage (HDRV) is floating B+ control driver stage (BDRV) is floating CLBL provides a continuous blanking signal.

There are two different methods of restarting ways the IC:

1. XSEL (pin 9) is open-circuit or connected to ground. The control bit SOFTST must be set to logic 1 via the I2C-bus. Then the IC returns to normal operation via soft start.

2. XSEL (pin 9) is connected to VCC via an external resistor.Thesupplyvoltage of the IC must be switched off for a certain period of time, before the IC can be restarted again using the standard power-on procedure.

Vertical oscillator and amplitude control

This stage is designed for fast stabilization of vertical size after changes in sync frequency conditions. The free-running frequency f

fr(V)

is determined by the

resistor R

VREF

connected to pin 23 and the capacitor

VCAP

connected to pin 24. The value of R

VREF

is not only optimized for noise and linearity performance in the whole vertical and EW section, but also influences several internal references. Therefore the value of R

VREF

must not

be changed. Capacitor C

VCAP

should be used toselect the free-running frequency of the vertical oscillator in accordance with the following formula:

To achieve a stabilized amplitude the free-running frequencyf

fr(V)

,withoutadjustment,shouldbe at least 10% lower than the minimum trigger frequency. The contributions shown in Table 2 can be assumed.

Table 2 Calculation of f

fr(V)

total spread

Result for 50 to 160 Hz application:

The AGC of the vertical oscillator can be disabled by setting control bit AGCDIS via the I

C-bus. A precise external current has to be injected into VCAP (pin 24) to obtain the correct vertical size. This special application mode can be used when the vertical sync pulses are serrated (shifted); this condition is found in some display modes, e.g. when using a 100 Hz up converter for video signals.

Application hint: VAGC (pin 22) has a high input impedance during scan. Therefore, the pin must not be loaded externally otherwise non-linearities in the vertical output currents may occur due to the changing charge current during scan.

Adjustment of vertical size, VGA overscan and EHT compensation

There are four differentways to adjust the amplitude of the differential output currents at VOUT1 and VOUT2.

1. Register VGAIN changes the vertical size without

affecting any other output signal of the IC. This adjustment is meant for factory alignments.

2. Register VSIZE changes not only the vertical size, but

also provides the correct tracking of all other related waveforms (see Section “Tracking of vertical adjustments”). This register should be used for user adjustments.

3. For the VGA350 mode register VOVSCN can activate

a +17% step in vertical size.

4. VSMOD(pin 21) can be used for a DC controlled EHT

compensation of vertical size by correcting the differential output currents at VOUT1 and VOUT2. The EW waveforms, verticalfocus, pin unbalance and parallelogram corrections are not affected by VSMOD.

fr(V)

10.8 R

VREF

× C

VCAP

-----------------------------------------------------------

Contributing elements

Minimum frequency offset between f

fr(V)

and

lowest trigger frequency

10%

Spread of IC ±3% Spread of R

VREF

±1%

Spread of C

VCAP

±5%

Total 19%

fr(V)

50 Hz

1.19

---------------

42 Hz==

1999 Jul 13 10

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Adjustment of vertical position, vertical linearity and vertical linearity balance

Register VOFFS provides a DC shift at the sawtooth outputs VOUT1 and VOUT2 (pins 13 and 12) without affecting any other output waveform. This adjustment is meant for factory alignments.

Register VPOS provides a DC shift at the sawtooth output VOUT1 and VOUT2 with correct tracking of all other related waveforms (see Section “Tracking of vertical adjustments”). This register should be used for user adjustments. Due to the tracking the whole picture moves vertically while maintaining the correct geometry.

Register VLIN is used to adjust the amount of the vertical S-correction in the output signal. This function can be switched off by control bit VSC.

Tracking of vertical adjustments

The adjustments via registers VSIZE, VOVSCN and VPOS also affect the waveforms of horizontal pincushion, vertical linearity (S-correction), vertical linearity balance, focus parabola, pin unbalance and parallelogram correction. The result of this interaction is that no readjustment of these parameters is necessary after an user adjustment of vertical picture size and vertical picture position.

Adjustment of vertical moire cancellation

To achieve a cancellation of vertical moire (also known as ‘scanmoire’)theverticalpicturepositioncanbemodulated by half the vertical frequency. The amplitude of the modulation is controlled by register VMOIRE and can be switched off via control bit MOD.

Horizontal pincushion (including horizontal size, corner correction and trapezium correction)

EWDRV(pin 11) provides a complete EW drive waveform. The components horizontal pincushion, horizontal size, corner correction and trapezium correction are controlled by the registers HPIN, HSIZE, HCORT, HCORB and HTRAP.

The corner correction can be adjusted separately for the top (HCORT) and bottom (HCORB) part of the picture.

The pincushion (EW parabola) amplitude, corner and trapezium correction track with the vertical picture size (VSIZE) and also with the adjustment for vertical picture position(VPOS). The corner correctiondoes not track with the horizontal pincushion (HPIN).

Further the horizontal pincushion amplitude, corner and trapezium correction track with the horizontal picture size, which is adjusted via register HSIZE and the analog modulation input HSMOD. If the DC component in the EWDRV output signal is increased via HSIZE or I

HSMOD

, the pincushion, corner and trapezium component of the EWDRV output will be reduced by a factor of

The value 14.4 V is a virtual voltage for calculation only. The output pin can not reach this value, but the gain (and DCbias)oftheexternalapplicationshouldbesuchthatthe horizontal deflection is reduced to zero when EWDRV reaches 14.4 V.

HSMOD (pin 31) can be used for a DC controlled EHT compensation by correcting horizontal size, horizontal pincushion, corner and trapezium. The control range at this pin tracks with the actual value of HSIZE. For an increasing DC component V

HSIZE

in the EWDRV output

signal, the DC component V

HEHT

caused by I

HSMOD

will be

reducedbyafactorof asshownintheequation above.

The whole EWDRV voltage is calculated as follows: V

EWDRV

= 1.2 V + [V

HSIZE+VHEHT

× f(HSIZE) + (V

HPIN

HCOR+VHTRAP

) × g(HSIZE, HSMOD)] × h(I

HREF

)

Where:

HSIZEVHEHT

HSIZE

14.4 V

-----------------

–





14.4 V

-------------------------------------------------------------------------

–

HSIZE

14.4 V

-----------------

–

HEHT

HSMOD

120 µA

------------------- -

0.69×=

f(HSIZE) 1

HSIZE

14.4 V

-----------------

–=

g(HSIZE, HSMOD) 1

HSIZEVHEHT

HSIZE

14.4 V

-----------------

–





14.4 V

--------------------------------------------------------------------------

–=

HREF

()

HREF

f70kHz=

--------------------------------

1999 Jul 13 11

Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Two different modes of operation can be chosen for the EW output waveform via control bit FHMULT:

1. Mode 1 Horizontal size is controlled via register HSIZE and

causesaDCshift at the EWDRV output. The complete waveform is also multiplied internally by a signal proportional to the line frequency [which is detected via the current at HREF (pin 28)]. This mode is to be used for driving EW diode modulator stages which require a voltage proportional to the line frequency.

2. Mode 2 The EW drive waveform does not track with the line

frequency. This mode is to be used for driving EW modulatorswhich require a voltage independent ofthe line frequency.

Output stage for asymmetric correction waveforms [ASCOR (pin 20)]

This output is designed as a voltage output for superimposed waveforms of vertical parabola and sawtooth. The amplitude and polarity of both signals can be changed by registers HPARAL and HPINBAL via the I2C-bus.

Application hint: The TDA4856 offers two possibilities to control registers HPINBAL and HPARAL.

1. Control bit ACD = 1 The two registers now control the horizontal phase by

means of internal modulation of the PLL2 horizontal phase control. The ASCOR output (pin 20) can be left unused, but it will always provide an output signal because the ASCOR output stage is not influenced by the control bit ACD.

2. Control bit ACD = 0 The internal modulation via PLL2 is disconnected.

In order to obtain the required effect on the screen, pin ASCORmust now be fedtothe DC amplifier which controls the DC shift of the horizontal deflection. This option is useful for applications which already use a DC shift transformer.

If the tube does not need HPINBAL and HPARAL, then pin ASCOR can be used for other purposes, i.e. for a simple dynamic convergence.

Dynamic focus section [FOCUS (pin 32)]

Thissectiongeneratesacompletedrivesignalfordynamic focus applications. The amplitude of the horizontal parabola is internally stabilized, thus it is independent of the horizontal frequency. The amplitude can be adjusted via register HFOCUS. Changing horizontal size may require a correction of HFOCUS. To compensate for the delay in external focus amplifiers a ‘pre-correction’ for the phase of the horizontal parabola has been implemented (see Fig.28). The amount of this pre-correction can be adjusted via register HFOCAD. The amplitude of the vertical parabola is independent of frequency and tracks with all vertical adjustments. The amplitude can be adjusted via register VFOCUS.

FOCUS (pin 32) is designed as a voltage output for the superimposed vertical and horizontal parabolas.

B+ control function block

The B+ control function block of the TDA4856 consists of an Operational Transconductance Amplifier (OTA), a voltagecomparator, a flip-flop and a dischargecircuit.This configuration allows easy applications for different B+ control concepts. See also Application Note AN96052:

“B+ converter Topologies for Horizontal Deflection and EHT with TDA4855/58”

GENERAL DESCRIPTION The non-inverting input of the OTA is connected internally

toa high precision referencevoltage. The inverting inputis connectedto BIN (pin 5). Aninternal clamping circuit limits the maximum positive output voltage of the OTA. The output itself is connected to BOP (pin 3) and to the inverting input of the voltage comparator. The non-inverting input of the voltage comparator can be accessed via BSENS (pin 4).

B+ drive pulses are generated by an internal flip-flop and fed to BDRV (pin 6) via an open-collector output stage. This flip-flop is set at the rising edge of the signal at HDRV (pin 8). The falling edge of the output signal at BDRV has a defined delay of t

d(BDRV)

to the rising edge of the HDRV pulse. When the voltage at BSENS exceeds the voltageat BOP, the voltage comparator output resets the flip-flop and, therefore, the open-collector stage at BDRV is floating again.

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

An internal discharge circuit allows a well defined discharge of capacitors at BSENS. BDRV is active at a LOW-level output voltage (see Figs 22 and 23), thus it requires an external inverting driver stage.

The B+ function block can be used for B+ deflection modulators in many different ways. Two popular application combinations are as follows:

• Boost converter in feedback mode (see Fig.22) In this application the OTA is used as an error amplifier

witha limited output voltagerange. The flip-flop isset on the rising edge of the signal at HDRV. A reset will be generated when the voltage at BSENS, taken from the current sense resistor, exceeds the voltage at BOP.

If no reset is generated within a line period, the rising edgeof the next HDRV pulseforces the flip-flop to reset. The flip-flop is set immediately after the voltage at BSENS has dropped below the threshold voltage V

RESTART(BSENS)

• Buck converter in feed forward mode (see Fig.23) This application uses an external RC combination at

BSENS to provide a pulse width which is independent from the horizontal frequency. The capacitor is charged via an external resistor and discharged by the internal discharge circuit. For normal operation the discharge circuit is activated when the flip-flop is reset by the internal voltage comparator. The capacitor will now be discharged with a constant current until the internally controlled stop level V

STOP(BSENS)

is reached. This level willbe maintained until therising edge of thenext HDRV pulse sets the flip-flop again and disables the discharge circuit.

If no reset is generated within a line period, the rising edge of the next HDRV pulse automatically starts the discharge sequence and resets the flip-flop. When the voltage at BSENS reaches the threshold voltage V

RESTART(BSENS)

, the discharge circuit will be disabled automatically and the flip-flop will be set immediately. This behaviour allows a definition of the maximum duty cycle of the B+ control drive pulse by the relationship of charge current to discharge current.

Supply voltage stabilizer, references, start-up procedures and protection functions

The TDA4856 provides an internal supply voltage stabilizer for excellent stabilization of all internal references.Aninternalgap reference, especially designed for low-noise, is the reference for the internal horizontal andverticalsupplyvoltages.Allinternalreference currents and drive current for the vertical output stage are derived from this voltage via external resistors.

If either the supply voltage is below 8.3 V or no data from the I2C-bus has been received after power-up, the internal softstart and protection functions do not allowanyof those outputs [HDRV, BDRV, VOUT1, VOUT2 and HUNLOCK (see Fig.24)] to be active.

For supply voltages below 8.3 V the internal I2C-bus will not generate an acknowledge and the IC is in standby mode. This is because the internal protection circuit has generated a reset signal for the soft start register SOFTST. Above 8.3 V data is accepted and all registers can be loaded. If the register SOFTST has received a set from the I2C-bus, the internal soft start procedure is released, which activates all above mentioned outputs.

If during normal operation the supply voltage has dropped below 8.1 V, the protection mode is activated and HUNLOCK(pin 17)changesto the protection status and is floating. This can be detected by the microcontroller.

This protection mode has been implemented in order to protect the deflection stages and the picture tube during start-up, shut-down and fault conditions. This protection mode can be activated as shown in Table 3.

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Table 3 Activation of protection mode

When the protection mode is active, several pins of the TDA4856 are forced into a defined state:

HDRV (horizontal driver output) is floating BDRV (B+ control driver output) is floating HUNLOCK (indicates, that the frequency-to-voltage

converter is out of lock) is floating (HIGH-level via external pull-up resistor)

CLBL provides a continuous blanking signal The capacitor at HPLL2 is discharged.

If the soft start procedure is activated via the I2C-bus, all of these actions will beperformed in a well defined sequence (see Figs 24 and 25).

Power dip recognition

In standby mode the I2C-bus will only answer with an acknowledge, when data is sent to control register with subaddress 1AH. This register contains the standby and soft start control bit.

If the I2C-bus master transmits data to another register, an aknowledge is given after the chip address and the subaddress; an acknowledge is not given after the data. This indicates that only in soft start mode data can be stored into normal registers.

If the supply voltage dips under 8.1 V the TDA4856leaves normal operation mode and changes into standby mode. The microcontroller can check this state by sending data intoaregister with the subaddress 0XH. The acknowledge will only be given on the data if the TDA4856 is active.

Due to this behaviour the start-up of the TDA4856 is defined as follows. The first data that is transferred to the TDA4856 must be sent to the control register with subaddress 1AH. Any other subaddress will not lead to an acknowledge. This is a limitation in checking the I2C-busses of the monitor during start-up.

ACTIVATION RESET

Low supply voltage at pin 10 increase supply voltage;

reload registers; soft start via I2C-bus

Power dip, below 8.1 V reload registers;

soft start via I2C-bus or via supply voltage

X-ray protection XRAY (pin 2) triggered

reload registers; soft start via I2C-bus

HPLL2 (pin 30) externally pulled to ground

release pin 30

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); all voltages measured with respect to ground.

Notes

1. Machine model: 200 pF; 0.75 µH; 10 Ω.

2. Human body model: 100 pF; 7.5 µH; 1500 Ω.

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION

In accordance with

“URF-4-2-59/601”

; EMC emission/immunity test in accordance with

“DIS 1000 4.6”

(IEC 801.6).

Note

1. Tests are performed with application reference board. Tests with other boards will have different results.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

supply voltage −0.5 +16 V

i(n)

input voltage on pins:

BIN −0.5 +6.0 V HSYNC, VSYNC, VREF, HREF, VSMOD and HSMOD −0.5 +6.5 V SDA and SCL −0.5 +8.0 V XRAY −0.5 +8.0 V

o(n)

output voltage on pins:

VOUT2, VOUT1 and HUNLOCK −0.5 +6.5 V BDRV and HDRV −0.5 +16 V

I/O(n)

input/output voltages at pins BOP and BSENS −0.5 +6.0 V

o(HDRV)

horizontal driver output current − 100 mA

i(HFLB)

horizontal ﬂyback input current −10 +10 mA

o(CLBL)

video clamping pulse/vertical blanking output current −−10 mA

o(BOP)

B+ control OTA output current − 1mA

o(BDRV)

B+ control driver output current − 50 mA

o(EWDRV)

EW driver output current −−5mA

o(FOCUS)

focus driver output current −−5mA

amb

operating ambient temperature −20 +70 °C

junction temperature − 150 °C

stg

storage temperature −55 +150 °C

ESD

electrostatic discharge for all pins note 1 −150 +150 V

note 2 −2000 +2000 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air 55 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

EMC

emission test note 1 − 1.5 − mV immunity test note 1 − 2.0 − V

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

CHARACTERISTICS

VCC= 12 V; T

amb

=25°C; peripheral components in accordance with Fig.1; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Horizontal sync separator

NPUT CHARACTERISTICS FOR DC-COUPLED TTL SIGNALS: PIN HSYNC

i(HSYNC)

sync input signal voltage 1.7 −−V

HSYNC(sl)

slicing voltage level 1.2 1.4 1.6 V

r(HSYNC)

rise time of sync pulse 10 − 500 ns

f(HSYNC)

fall time of sync pulse 10 − 500 ns

W(HSYNC)(min)

minimum width of sync pulse 0.7 −−µs

i(HSYNC)

input current V

HSYNC

= 0.8 V −−−200 µA

HSYNC

= 5.5 V −−10 µA INPUT CHARACTERISTICS FOR AC-COUPLED VIDEO SIGNALS (SYNC-ON-VIDEO, NEGATIVE SYNC POLARITY) V

HSYNC

sync amplitude of video input signal voltage

source

=50Ω−300 − mV

HSYNC(sl)

slicing voltage level (measured from top sync)

source

=50Ω 90 120 150 mV

clamp(HSYNC)

top sync clamping voltage level

source

=50Ω 1.1 1.28 1.5 V

ch(HSYNC)

charge current for coupling capacitor

HSYNC>Vclamp(HSYNC)

1.7 2.4 3.4 µA

W(HSYNC)(min)

minimum width of sync pulse 0.7 −−µs

source(max)

maximum source resistance duty cycle = 7% −−1500 Ω

i(diff)(HSYNC)

differential input resistance during sync − 80 −Ω

Automatic polarity correction for horizontal sync

horizontal sync pulse width related to line period

−−25 %

d(HPOL)

delay time for changing polarity

0.3 − 1.8 ms

Vertical sync integrator

int(V)

integration time for generation of a vertical trigger pulse

fH= 15.625 kHz; I

HREF

= 0.52 mA

14 20 26 µs

fH= 31.45 kHz; I

HREF

= 1.052 mA

71013µs

fH= 64 kHz; I

HREF

= 2.141 mA

3.9 5.7 6.5 µs

fH= 100 kHz; I

HREF

= 3.345 mA

2.5 3.8 4.5 µs

Vertical sync slicer (DC-coupled, TTL compatible): pin VSYNC

i(VSYNC)

sync input signal voltage 1.7 −−V

VSYNC(sl)

slicing voltage level 1.2 1.4 1.6 V

i(VSYNC)

input current 0 V < V

SYNC

< 5.5 V −−±10 µA

P(H)

---------- -

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Automatic polarity correction for vertical sync

W(VSYNC)(max)

maximum width of vertical sync pulse

−−400 µs

d(VPOL)

delay for changing polarity 0.45 − 1.8 ms

Video clamping/vertical blanking output: pin CLBL

clamp(CLBL)

width of video clamping pulse measured at V

CLBL

= 3 V 0.6 0.7 0.8 µs

clamp(CLBL)

top voltage level of video clamping pulse

4.32 4.75 5.23 V

clamp

temperature coefﬁcient of V

clamp(CLBL)

− 4 − mV/K

STPS

clamp

steepness of slopes for clamping pulse

RL=1MΩ; CL=20pF − 50 − ns/V

d(HSYNCt-CLBL)

delay between trailing edge of horizontal sync and start of video clamping pulse

clamping pulse triggered on trailing edge of horizontal sync; control bit CLAMP = 0; measured at V

CLBL

=3V

− 130 − ns

clamp1(max)

maximum duration of video clamping pulse referenced to end of horizontal sync

−−1.0 µs

d(HSYNCl-CLBL)

delay between leading edge of horizontal sync and start of video clamping pulse

clamping pulse triggered on leading edge of horizontal sync; control bit CLAMP = 1; measured at V

CLBL

=3V

− 300 − ns

clamp2(max)

maximum duration of video clamping pulse referenced to end of horizontal sync

−−0.15 µs

blank(CLBL)

top voltage level of vertical blanking pulse

notes 1 and 2 1.7 1.9 2.1 V

blank(CLBL)

width of vertical blanking pulse at pins CLBL and HUNLOCK

control bit VBLK = 0 220 260 300 µs control bit VBLK = 1 305 350 395 µs

blank

temperature coefﬁcient of V

blank(CLBL)

− 2 − mV/K

scan(CLBL)

output voltage during vertical scan

CLBL

= 0 0.59 0.63 0.67 V

scan

temperature coefﬁcient of V

scan(CLBL)

−−2 − mV/K

sink(CLBL)

internal sink current 2.4 −−mA

L(CLBL)

external load current −−−3.0 mA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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Philips Semiconductors Product speciﬁcation

I2C-bus autosync deﬂection controller for PC monitors

TDA4856

Horizontal oscillator: pins HCAP and HREF

fr(H)

free-running frequency without PLL1 action (for testing only)

HBUF

= ∞;

HREF

= 2.4 kΩ;

HCAP

= 10 nF; note 3

30.53 31.45 32.39 kHz

∆f

fr(H)

spread of free-running frequency(excludingspreadof external components)

−−±3.0 %

temperature coefﬁcient of free-running frequency

−100 0 +100 10−6/K

H(max)

maximum oscillator frequency −−130 kHz

HREF

voltage at input for reference current

2.43 2.55 2.68 V

Unlock blanking detection: pin HUNLOCK

scan(HUNLOCK)

low level of HUNLOCK saturation voltage in case

of locked PLL1; internal sink current = 1 mA

−−250 mV

blank(HUNLOCK)

blanking level of HUNLOCK external load current = 0 0.9 1 1.1 V

blank

temperature coefﬁcient of V

blank(HUNLOCK)

−−0.9 − mV/K

sink

temperature coefﬁcient of I

sink(HUNLOCK)

− 0.15 − %/K

sink(int)

internal sink current for blanking pulses;

PLL1 locked

1.4 2.0 2.6 mA

L(HUNLOCK)

maximum external load current

HUNLOCK

=1V −−−2mA

leakage current V

HUNLOCK

= 5 V in case of unlocked PLL1 and/or protection active

−−±5 µA

PLL1 phase comparator and frequency-locked loop: pins HPLL1 and HBUF

W(HSYNC)(max)

maximum width of horizontal sync pulse (referenced to line period)

−−25 %

lock(HPLL1)

total lock-in time of PLL1 − 40 80 ms

ctrl(HPLL1)

control currents notes 4 and 5

locked mode; level 1 − 15 −µA locked mode; level 2 − 145 −µA

HBUF

buffered f/v voltage at HBUF (pin 27)

minimum horizontal frequency

− 2.55 − V

maximum horizontal frequency

− 0.5 − V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

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