Philips TDA4855 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA4855

Autosync Deflection Controller (ASDC)

Preliminary speciﬁcation File under Integrated Circuits, IC02

1996 Jul 18

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

FEATURES Concept features

• Full Horizontal (H) plus Vertical (V) autosync capability

• Completely DC controllable for analog and digital

concepts

• Excellent geometry control functions (e.g. automatic correction of East-West (EW) parabola during adjustment of vertical size and vertical shift)

• Flexible Switched Mode Power Supply (SMPS) function block for feedback and feed forward converters

• Horizontal focus parabola with amplitude control

• X-ray protection

• Start-up and switch-off sequence for safe operation of

all power components

• Very good vertical linearity

• Internal supply voltage stabilization

• SDIP32 package.

Synchronization inputs

• Can handle all sync signals (Horizontal, Vertical, Composite and Sync-on-video)

• Combined output for video clamping, vertical blanking and protection blanking.

Horizontal section

• Extremely low jitter

• Frequency locked loop for smooth catching of line

frequency

• Simple frequency preset of f

min

and f

by external

max

resistors

• DC controllable wide range linear picture position

• Soft start for horizontal driver.

Vertical section

• Vertical amplitude independent of frequency

• Automatic correction of picture height for VGA350 and

VGA400 modes

• DC controllable picture height, picture position and S-correction

• Differential current outputs for DC coupling to vertical booster.

EW section

• Output for DC adjustable EW parabola with smoothed top

• DC controllable picture width and trapezium correction

• Optional tracking of EW parabola with line frequency

• Prepared for additional DC controls of vertical linearity,

EW-corner, EW pin balance, EW parallelogram, vertical focus by extended application.

GENERAL DESCRIPTION

The TDA4855 is a high performance and efficient solution for autosync monitors. The concept is fully DC controllable and can be used in applications with a microcontroller and stand-alone in rock bottom solutions.

The TDA4855 provides synchronization processing, H + V synchronization with full autosync capability, and very short settling times after mode changes. External power components are given a great deal of protection. The IC generates the drive waveforms for DC-coupled vertical boosters such as TDA486X and TDA8351.

The TDA4855 provides extended functions e.g. as a flexible SMPS block and an extensive set of geometry control facilities, providing excellent picture quality.

Together with the Philips TDA488X video processor family a very advanced system solution is offered.

1996 Jul 18 2

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

∆HPOS horizontal shift adjustment range −±10.5 − % ∆VAMP vertical size adjustment range 60 − 100 % ∆VPOS vertical shift adjustment range −±11.5 − % ∆VSCOR vertical S-correction adjustment range 2 − 46 % ∆V

EWPAR

∆V

EWWID

∆V

EWTRP

amb

ORDERING INFORMATION

supply voltage 9.2 − 16 V supply current − 49 − mA

EW parabola adjustment range 0.15 − 3.0 V horizontal size adjustment range 0.2 − 4.0 V trapezium correction adjustment range −±0.5 − V operating ambient temperature 0 − 70 °C

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA4855 SDIP32 plastic shrink dual in-line package; 32 leads (400 mil) SOT232-1

1996 Jul 18 3

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

BLOCK DIAGRAM

EW

parabola

horizontal

size

EW

39 kΩ

EWPAR

220 kΩ

39 kΩ

EWWID

220 kΩ

39 kΩ

EWTRP

trapeziun

220 kΩ

EWDRV

XRAY

BDRV

(3)

B+ CONTROL

BSENS

APPLICATION

BOP

BIN

MBG550

VPOS VAMP VSCOR

220 kΩ

100 

22

kΩ

VREF

VAGC

VCAP

C 1%

VOUT1 VOUT2

39 kΩ

VCAP VAGC

VREF

23 24 22 17 18 19 13 12

VERTICAL

S-CORRECTION

OUTPUT STAGE

VERTICAL SIZE

VERTICAL POSITION

AGC

VERTICAL

OSCILLATOR

POLARITY

CORRECTION

EW

PARABOLA

VGA

PRESETS

TDA4855

INTEGRATOR

VERTICAL SYNC

B+

CONTROL

X-RAY

PROTECTION

FREQUENCY DETECTOR

COINCIDENCE DETECTOR

HFLB

STAGE

OUTPUT

HORIZONTAL

OSCILLATOR

HORIZONTAL

PLL1 PLL2

POLARITY

CORRECTION

HDRV

HFLB

12 nF

HPLL2

10 nF

HCAP

(1)

HREF

(1)

HBUF

30 28 29 31 1 7

220 

HPOS

kΩ

39

HPLL1 HBUF

kΩ

1.5

(2)

handbook, full pagewidth

Fig.1 Block diagram and application circuit.

47 nF

27 kΩ

SYNC

INPUT

VERTICAL

VSYNC

(TTL level)

AND

SUPPLY

9825

PGND

9.2 to 16 V CC

REFERENCE

SGND

VERTICAL BLANKING

VIDEO CLAMPING PULSE

CLBL

blanking

clamping

1996 Jul 18 4

FOCUS

H-focus

parabola

FOCUS

COMPOSITE

SYNC INPUT

HORIZONTAL/

HSYNC

(TTL level)

(video)

range.

(1) See calculation of f

(2) See note 3 of Chapter “Characteristics”.

(3) See Figs 12 and 13.

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

PINNING

SYMBOL PIN DESCRIPTION

HFLB 1 horizontal ﬂyback input XRAY 2 X-ray protection input BOP 3 B+ control OTA output;

comparator input BSENS 4 B+ control comparator input/output BIN 5 B+ control OTA input BDRV 6 B+ control driver output HDRV 7 horizontal driver output PGND 8 power ground V

9 supply voltage FOCUS 10 horizontal focus parabola input/output EWDRV 11 EW parabola output VOUT2 12 vertical output 2 (ascending sawtooth) VOUT1 13 vertical output 1 (descending

sawtooth)

VSYNC 14 vertical synchronization input/output

(TTL level)

HSYNC 15 horizontal/composite synchronization

input (TTL level or sync-on-video)

CLBL 16 video clamping pulse/vertical blanking

and protection output VPOS 17 vertical shift input VAMP 18 vertical size input VSCOR 19 vertical S-correction input EWTRP 20 EW trapezium correction input EWPAR 21 EW parabola amplitude input VAGC 22 external capacitor for vertical

amplitude control VREF 23 external resistor for vertical oscillator VCAP 24 external capacitor for vertical oscillator SGND 25 signal ground HPLL1 26 external ﬁlter for PLL1 HBUF 27 buffered f/v voltage output HREF 28 reference current for horizontal

oscillator HCAP 29 external capacitor for horizontal

oscillator HPOS 30 horizontal shift input HPLL2 31 external ﬁlter for PLL2/soft start EWWID 32 horizontal size input

handbook, halfpage

HFLB

XRAY

BOP

BIN

BDRV HDRV PGND

CLBL

4 5 6 7 8

9 10 11 12 13 14 15 16

TDA4855

MBG549

BSENS

FOCUS

EWDRV

VOUT2

VOUT1 VSYNC HSYNC

Fig.2 Pin configuration.

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

EWWID HPLL2 HPOS HCAP HREF HBUF HPLL1 SGND VCAP VREF VAGC EWPAR EWTRP VSCOR VAMP VPOS

1996 Jul 18 5

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction

HSYNC (pin 15) is the input for horizontal synchronization signals, which can be DC-coupled TTL signals (horizontal or composite sync) and AC-coupled negative-going video sync signals. Video syncs are clamped to 1.28 V and sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to sync top.

For DC-coupled TTL signals the input clamping current is limited. The slicing level for TTL signals is 1.4 V.

The separated sync signal (either video or TTL) is integrated on an internal capacitor to detect and normalize the sync polarity.

Normalized horizontal sync pulses are used as input signals for the vertical sync integrator, the PLL1 phase detector and the frequency-locked loop.

Vertical sync integrator

Normalized composite sync signals from HSYNC are integrated on an internal capacitor in order to extract vertical sync pulses. The integration time is dependent on the horizontal oscillator reference current at HREF (pin 28). The integrator output directly triggers the vertical oscillator. This signal is available at VSYNC (normally vertical sync input; pin 14), which is used as an output in this mode.

Vertical sync slicer and polarity correction

Vertical sync signals (TTL) applied to VSYNC (pin 14) are sliced at 1.4 V. The output signal of the sync slicer is integrated on an internal capacitor to detect and normalize the sync polarity.

If a composite sync signal is detected at HSYNC, VSYNC is used as output for the integrated vertical sync (e.g. for power saving applications).

Video clamping/vertical blanking generator

The lower level of the sandcastle pulse is the vertical blanking pulse, which is derived directly from the internal oscillator waveform. It is started by the vertical sync and stopped with the start of the vertical scan. This results in optimum vertical blanking.

Blanking will be activated continuously, if one of the following conditions is true:

No horizontal flyback pulses at HFLB (pin 1) X-ray protection is activated Soft start of horizontal drive (voltage at HPLL2 (pin 31)

is low) Supply voltage at V PLL1 is unlocked while frequency-locked loop is in

search mode.

Blanking will not be activated if the horizontal sync frequency is below the valid range or there are no sync pulses available.

VGA mode detector

The polarities of horizontal and vertical sync are internally detected in order to provide an automatic adjustment of vertical size for VGA350 and VGA400 modes. These automatic VGA presets are activated only if the current ratio I (see Chapter “Characteristics”). Thus it is possible to disable this function for a part of the frequency range or even completely.

Table 1 VGA modes

MODE

VGA350 + − VGA400 − + VGA480 −−

HBUF/IHREF

−++

(pin 9) is low (see Fig.14)

exceeds a fixed value

HORIZONTAL/VERTICAL SYNC

POLARITY

The video clamping/vertical blanking signal at CLBL (pin 16) is a two-level sandcastle pulse which is especially suitable for video ICs such as the TDA488X family, but also for direct applications in video output stages.

The upper level is the video clamping pulse, which is triggered by the trailing edge of the horizontal sync pulse. The width of the video clamping pulse is determined by an internal monoflop.

1996 Jul 18 6

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

Frequency-locked loop

The frequency-locked loop can lock the horizontal oscillator over a wide frequency range. This is achieved by a combined search and PLL operation. The frequency range is preset by two external resistors and the

recommended maximum ratio is

min

---------- f

max

------- -

3.5

Larger ranges are possible by extended applications. Without a horizontal sync signal the oscillator will be

free-running at f

. Any change of sync conditions is

min

detected by the internal coincidence detector. A deviation of more than 4% between horizontal sync and oscillator frequency switches the horizontal section into search mode. This means that PLL1 control currents are switched off immediately. Then the internal frequency detector starts tuning the oscillator. Very small DC currents at HPLL1 (pin 26) are used to perform this tuning with a well defined change rate. When coincidence between horizontal sync and oscillator frequency is detected, the search mode is replaced by a normal PLL operation. This operation ensures a smooth tuning and avoids fast changes of horizontal frequency during catching.

In this concept it is not allowed to load HPLL1. The frequency dependent voltage at this pin is fed internally to HBUF (pin 27) via a sample-and-hold and buffer stage. The sample-and-hold stage removes all disturbances caused by horizontal sync or composite vertical sync from the buffered voltage. An external resistor from HBUF to HREF defines the frequency range.

See also hints for locking procedure in note 3 of Chapter “Characteristics”.

PLL1 phase detector

The phase detector is a standard type using switched current sources. It compares the middle of horizontal sync with a fixed point on the oscillator sawtooth voltage. The PLL1 loop filter is connected to HPLL1 (pin 26).

The reference current at HREF also defines the integration time constant of the vertical sync integration.

Calculation of line frequency range

First the oscillator frequencies f

min

and f

have to be

max

calculated. This is achieved by adding the spread of the relevant components to the highest and lowest sync frequencies f the difference of the currents in R highest oscillator frequency R

S(min)

and f

. The oscillator is driven by

S(max)

and R

HREF

does not contribute to

HBUF

. At the

the spread. The spread will increase towards lower frequencies due to the contribution of R

dependent on the ratio

S max()

------------------f

Smin()

HBUF

. It is also

The following example is a 31.45 to 64 kHz application:

S max()

------------------f

Smin()

64 kHz

---------------------------

31.45 kHz

2.04== =

Table 2 Calculation of total spread

spread of: for f

max

for f

min

IC 3% 3% C R R

HCAP HREF HREF

, R

HBUF

2% 2% 1% −

− 1% × (2.3 × nS− 1)

Total 6% 8.69%

Thus the typical frequency range of the oscillator in this example is:

maxfSmax()

min

Smin()

----------------- -

1.087

The resistors R

1.06× 67.84 kHz==

28.93 kHz==

HREF

and R

can be calculated with the

HBUF

following formulae:

Horizontal oscillator

The horizontal oscillator is of the relaxation type and requires a capacitor of 10 nF at HCAP (pin 29). For optimum jitter performance the value of 10 nF must not be changed.

The maximum oscillator frequency is determined by a resistor from HREF to ground. A resistor from HREF to HBUF defines the frequency range.

1996 Jul 18 7

HREF

HBUF

Where:

74 kHz k××Ω

-------------------------------------f

max

HREF

-------------------------------------------- -

max

---------- f

min

kHz[]

1.19× n×

n1–

2.35==

1.091 kΩ==

2.26 kΩ==

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

The spread of f

Smax()

ratio .

------------------f

Smin()

increases with the frequency

min

For higher ratios this spread can be reduced by using resistors with less tolerances.

PLL2 phase detector

The PLL2 phase detector is similar to the PLL1 detector and compares the line flyback pulse at HFLB (pin 1) with the oscillator sawtooth voltage. The PLL2 detector thus compensates for the delay in the external horizontal deflection circuit by adjusting the phase of the HDRV (pin 7) output pulse.

The phase between horizontal flyback and horizontal sync can be controlled at HPOS (pin 30).

If HPLL2 is pulled to ground, horizontal output pulses, vertical output currents and B+ control driver pulses are inhibited. This means, HDRV (pin 7), BDRV (pin 6) VOUT1 (pin 13) and VOUT2 (pin 12) are floating in this state. PLL2 and the frequency-locked loop are disabled, and CLBL (pin 16) provides a continuous blanking signal.

This option can be used for soft start, protection and power-down modes. When the HPLL2 voltage is released again, an automatic soft start sequence will be performed (see Fig.15).

The soft start timing is determined by the filter capacitor at HPLL2 (pin 31), which is charged with an constant current during soft start. In the beginning the horizontal driver stage generates very small output pulses. The width of these pulses increases with the voltage at HPLL2 until the final duty factor is reached. At this point BDRV (pin 6), VOUT1 (pin 13) and VOUT2 (pin 12) are re-enabled. The voltage at HPLL2 continues to rise until PLL2 enters its normal operating range. The internal charge current is now disabled. Finally PLL2 and the frequency-locked loop are enabled, and the continuous blanking at CLBL is removed.

Horizontal phase adjustment

HPOS (pin 30) provides a linear adjustment of the relative phase between the horizontal sync and oscillator sawtooth. Once adjusted, the relative phase remains constant over the whole frequency range.

therefore the phase between horizontal sync and horizontal drive pulse is only determined by PLL2.

Output stage for line drive pulses

An open collector output stage allows direct drive of an inverting driver transistor because of a low saturation voltage of 0.3 V at 20 mA. To protect the line deflection transistor, the output stage is disabled (floating) for low supply voltage at V

(see Fig.14).

The duty factor of line drive pulses is slightly dependent on the actual line frequency. This ensures optimum drive conditions over the whole frequency range.

X-ray protection

The x-ray protection input XRAY (pin 2) provides a voltage detector with a precise threshold. If the input voltage at XRAY exceeds this threshold for a certain time, an internal latch switches the IC into protection mode. In this mode several pins are forced into defined states:

Horizontal output stage (HDRV) is floating B+ control driver stage (BDRV) is floating Vertical output stages (VOUT1 and VOUT2) are floating CLBL provides a continuous blanking signal The capacitor connected to HPLL2 (pin 31) is

discharged.

To reset the latch and return to normal operation, V

has

to be temporarily switched off.

Vertical oscillator and amplitude control

This stage is designed for fast stabilization of vertical amplitude after changes in sync frequency conditions. The free-running frequency f resistor R C

connected to pin 24. The value of R

VCAP

connected to pin 23 and the capacitor

VREF

is determined by the

osc(V)

VREF

is not only optimized for noise and linearity performance in the whole vertical and EW section, but also influences several internal references. Therefore the value of R be changed. Capacitor C

should be used to select the

VCAP

VREF

must not

free-running frequency of the vertical oscillator in accordance with the following formula:

osc V()

-----------------------------------------------------------

10.8 R

× C

VREF

VCAP

Application hint: HPOS is a current input, which provides an internal reference voltage while I

is in the specified

HPOS

adjustment current range. By grounding HPOS the symmetrical control range is forced to its centre value,

1996 Jul 18 8

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

To achieve a stabilized amplitude the free-running frequency f

, without adjustment, should be at least

osc(V)

10% lower than the minimum trigger frequency. The contributions shown in Table 3 can be assumed.

Table 3 Calculation of f

osc(V)

total spread

Contributing elements:

Minimum frequency offset between f

osc(V)

±10%

and lowest trigger frequency Spread of IC ±3% Spread of R Spread of C

VREF VCAP

±1% ±5%

Total 19%

Result for 50 to 110 Hz application:

osc V()

50 Hz

---------------

1.19

42 Hz==

Application hint: VAGC (pin 22) has a high input impedance during scan, thus the pin must not be loaded externally. Otherwise non-linearities in the vertical output currents may occur due to the changing charge current during scan.

Application hint: The full vertical sync range of 1 : 2.5 can be made usable by incorporating an adjustment of the free-running frequency. Also the complete sync range can be shifted to higher frequencies (e.g. 70 to 160 Hz) by reducing the value of C

VCAP

Adjustment of vertical size, vertical shift and S-correction

VPOS (pin 17) is the input for the DC adjustable vertical picture shift. This pin provides a phase shift at the sawtooth output VOUT1 and VOUT2 (pins 13 and 12) and the EW drive output EWDRV (pin 11) in such a way, that the whole picture moves vertically while maintaining the correct geometry.

The amplitude of the differential output currents at VOUT1 and VOUT2 can be adjusted via input VAMP (pin 18). This can be a combination of a DC adjustment and a dynamic waveform modulation.

VSCOR (pin 19) is used to adjust the amount of vertical S-correction in the output signal.

The adjustments for vertical size and vertical shift also affect the waveforms of the EW parabola and the vertical S-correction. The result of this interaction is that no

readjustment of these parameters is necessary after an adjustment of vertical picture size or position.

Application hint: VPOS is a current input, which provides an internal reference voltage while I

is in the specified

VPOS

adjustment current range. By grounding VPOS (pin 17) the symmetrical control range is forced to its centre value.

Application hint: VSCOR is a current input at 5 V. Superimposed on this level is a very small positive-going vertical sawtooth, intended to modulate an external long-tailed transistor pair. This enables further optional DC controls of functions which are not directly accessible such as vertical tilt or vertical linearity (see Fig.17).

EW parabola (including horizontal size and trapezium correction)

EWDRV (pin 11) provides a complete EW drive waveform. EW parabola amplitude, DC shift (horizontal size) and trapezium correction can be controlled via separate DC inputs.

EWPAR (pin 21) is used to adjust the parabola amplitude. This can be a combination of a DC adjustment and a dynamic waveform modulation.

The EW parabola amplitude also tracks with vertical picture size. The parabola waveform itself tracks with the adjustment for vertical picture shift (VPOS). Additional effort has been taken to generate a smooth waveform at the top of the parabola. This is to avoid ringing in the horizontal output stage.

EWWID (pin 32) offers two modes of operation:

1. Mode 1

Horizontal size is DC controlled via EWWID (pin 32) and causes a DC shift at the EWDRV output. Also the complete waveform is multiplied internally by a signal proportional to the line frequency (which is detected via the current at HREF (pin 28). This mode is to be used for driving EW modulator stages which require a voltage proportional to the line frequency.

2. Mode 2

EWWID (pin 32) is grounded. Then EWDRV is no longer multiplied by the line frequency. The DC adjustment for horizontal size must be added to the input of the B+ control amplifier BIN (pin 5). This mode is to be used for driving EW modulators which require a voltage independent of the line frequency.

EWTRP (pin 20) is used to adjust the amount of trapezium correction in the EW drive waveform.

1996 Jul 18 9

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

Application hint: EWTRP (pin 20) is a current input at 5 V. Superimposed on this level is a very small vertical parabola with positive tips, intended to modulate an external long-tailed transistor pair. This enables further optional DC controls of functions which are not directly accessible such as EW-corner, vertical focus or EW pin balance (see Fig.17).

Application hint: By grounding EWTRP (pin 20) the symmetrical control range is forced to its centre value.

Dynamic focus section

This section generates a horizontal parabola waveform for dynamic focus applications. The amplitude of this parabola is internally stabilized, thus it is independent from the line frequency.

FOCUS (pin 10) is designed as a current sink. The peak-to-peak amplitude of the output current can be adjusted by forcing the voltage at pin 10 to a value between 1 and 4 V.

B+ control function block

The B+ control function block of the ASDC consists of an Operational Transconductance Amplifier (OTA), a voltage comparator, a flip-flop and a discharge circuit. This configuration allows easy applications for different B+ control concepts.

ENERAL DESCRIPTION

G The non-inverting input of the OTA is connected internally

to a high precision reference voltage. The inverting input is connected to BIN (pin 5). An internal clamping circuit limits the maximum positive output voltage of the OTA. The output itself is connected to BOP (pin 3) and to the inverting input of the voltage comparator. The non-inverting input of the voltage comparator can be accessed via BSENS (pin 4).

B+ drive pulses are generated by an internal flip-flop and fed to BDRV (pin 6) via an open collector output stage. This flip-flop will be set at the rising edge of the signal at HDRV (pin 7). The falling edge of the output signal at BDRV has a defined delay of t

to the rising edge of

d(BDRV)

the HDRV pulse. When the voltage at BSENS exceeds the voltage at BOP, the voltage comparator output resets the flip-flop, and therefore the open collector stage at BDRV is floating again.

An internal discharge circuit allows a well defined discharge of capacitors at BSENS. BDRV is active at a low level output voltage (see Figs 12 and 13), thus it requires an external inverting driver stage.

The B+ function block can be used for B+ deflection modulators in either of two modes:

• Feedback mode (see Fig.12)

In this application the OTA is used as an error amplifier with a limited output voltage range. The flip-flop will be set at the rising edge of the signal at HDRV. A reset will be generated when the voltage at BSENS taken from the current sense resistor exceeds the voltage at BOP.

If no reset is generated within a line period, the rising edge of the next HDRV pulse forces the flip-flop to reset. The flip-flop is set immediately after the voltage at BSENS has dropped below the threshold voltage V

RESTART(BSENS)

• Feed forward mode (see Fig.13)

This application uses an external RC combination at BSENS to provide a pulse width which is independent from the horizontal frequency. The capacitor is charged via an external resistor and discharged by the internal discharge circuit. For normal operation the discharge circuit is activated when the flip-flop is reset by the internal voltage comparator. Now the capacitor will be discharged with a constant current until the internally controlled stop level V

STOP(BSENS)

is reached. This level will be maintained until the rising edge of the next HDRV pulse sets the flip-flop again and disables the discharge circuit.

If no reset is generated within a line period, the rising edge of the next HDRV pulse automatically starts the discharge sequence and resets the flip-flop (Fig.13). When the voltage at BSENS reaches the threshold voltage V

RESTART(BSENS)

, the discharge circuit will be disabled automatically and the flip-flop will be set immediately. This behaviour allows a definition of the maximum duty cycle of the B+ control drive pulse by the relationship of charge current to discharge current.

1996 Jul 18 10

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

Supply voltage stabilizer, references and protection

The ASDC provides an internal supply voltage stabilizer for excellent stabilization of all internal references. An internal gap reference especially designed for low-noise is the reference for the internal horizontal and vertical supply voltages. All internal reference currents and drive current for the vertical output stage are derived from this voltage via external resistors.

A special protection mode has been implemented in order to protect the deflection stages and the picture tube during start-up, shut-down and fault conditions. This protection mode can be activated as shown in Table 4.

Table 4 Activation of protection mode

ACTIVATION RESET

Low supply voltage at pin 9 increase supply voltage X-ray protection XRAY (pin 2)

triggered HPLL2 (pin 31) pulled to

ground

When protection mode is active, several pins of the ASDC are forced into a defined state:

HDRV (horizontal driver output) is floating BDRV (B+ control driver output) is floating VOUT1 and VOUT2 (vertical outputs) are floating CLBL provides a continuous blanking signal The capacitor at HPLL2 is discharged.

remove supply voltage

release pin 31

The return to normal operation is performed in accordance with the start-up sequence in Fig.14a, if the reset was caused by the supply voltage at pin 9. The first action with increasing supply voltage is the activation of continuous blanking at CLBL. When the threshold for activation of HDRV is passed, an internal current begins to charge the external capacitor at HPLL2 and a PLL2 soft start sequence is performed (see Fig.15). In the beginning of this phase the horizontal driver stage generates very small output pulses. The width of these pulses increases with the voltage at HPLL2 until the final duty cycle is reached. Then the PLL2 voltage passes the threshold for activation of BDRV, VOUT1 and VOUT2.

For activation of these pins not only the PLL2 voltage, but also the supply voltage must have passed the appropriate threshold. A last pair of thresholds has to be passed by PLL2 voltage and supply voltage before the continuous blanking is finally removed, and the operation of PLL2 and frequency-locked loop is enabled.

A return to the normal operation by releasing the voltage at HPLL2 will lead to a slightly different sequence. Here the activation of all functions is influenced only by the voltage at HPLL2 (see Fig.15).

Application hint: Internal discharge of the capacitor at HPLL2 will only be performed, if the protection mode was activated via the supply voltage or X-ray protection.

If the protection mode is activated via the supply voltage at pin 9, all these actions will be performed in a well defined sequence (see Fig.14). For activation via X-ray protection or HPLL2 all actions will occur simultaneously.

1996 Jul 18 11

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); all voltages measured with respect to ground.

SYMBOL PARAMETER MIN. MAX. UNIT

I(n)

O(n)

I/O(n)

HDRV

HFLB

CLBL

BOP

BDRV

EWDRV

amb

stg

esd

supply voltage −0.5 +16 V input voltages

BIN −0.5 +6.0 V HSYNC, VPOS, VAMP, VSCOR, VREF, HREF and HPOS −0.5 +6.5 V XRAY −0.5 +8.0 V

output voltages

VOUT1 and VOUT2 −0.5 +6.5 V BDRV and HDRV −0.5 +16 V

input/output voltages

BOP and BSENS −0.5 +6.0 V

FOCUS and VSYNC −0.5 +6.5 V horizontal driver output current − 100 mA horizontal ﬂyback input current −10 +10 mA video clamping pulse/vertical blanking output current −−10 mA B+ control OTA output current − 1mA B+ control driver output current − 50 mA EW driver output current −−5mA operating ambient temperature 0 70 °C junction temperature − 150 °C storage temperature −55 +150 °C electrostatic discharge for all pins (note 1)

machine model −400 +400 V

human body model −3000 +3000 V

Note

1. Machine model: 200 pF, 25 Ω, 2.5 µH; human body model: 100 pF, 1500 Ω, 7.5 µH.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

th j-a

thermal resistance from junction to ambient in free air 55 K/W

QUALITY SPECIFICATION

In accordance with

“URF-4-2-59/601”

; EMC emission/immunity test in accordance with

“DIS 1000 4.6”

(IEC 801.6)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

EMC

emission test note 1 − 1.5 − mV immunity test note 1 − 2.0 − V

Note

1. Tests are performed with application reference board. Tests with other boards will have different results.

1996 Jul 18 12

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

CHARACTERISTICS

=12V; T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Horizontal sync separator

NPUT CHARACTERISTICS FOR DC-COUPLED TTL SIGNALS [HSYNC (PIN 15)]

DC(HSYNC)

r(HSYNC)

f(HSYNC)

W(HSYNC)

DC(HSYNC)

INPUT CHARACTERISTICS FOR AC-COUPLED VIDEO SIGNALS (SYNC-ON-VIDEO, NEGATIVE SYNC POLARITY) V

AC(HSYNC)

clamp(HSYNC)

C(HSYNC)

HSYNC(min)

S(max)

diff(HSYNC)

Automatic polarity correction for horizontal sync

PH()

------------t

P(H)

Vertical sync integrator

int(V)

Vertical sync slicer (DC-coupled, TTL compatible) [VSYNC (pin 14)]

VSYNC

=25°C; peripheral components in accordance with Fig.1; unless otherwise speciﬁed.

amb

sync input signal voltage 1.7 −−V slicing voltage level 1.2 1.4 1.6 V rise time of sync pulse 10 − 500 ns fall time of sync pulse 10 − 500 ns minimum width of sync pulse 0.7 −−µs input current V

sync amplitude of video input

= 0.8 V −−−200 µA

HSYNC

= 5.5 V −−10 µA

HSYNC

− 300 − mV

signal voltage slicing voltage level

(measured from top sync)

source resistance R

=50Ω

90 120 150 mV

top sync clamping voltage level 1.1 1.28 1.5 V charge current for coupling

HSYNC

> V

clamp(HSYNC)

1.7 2.4 3.4 µA

capacitor minimum width of sync pulse 0.7 −−µs maximum source resistance duty factor = 7% −−1500 Ω differential input resistance during sync − 80 −Ω

horizontal sync pulse width related to t

fH< 45 kHz −−20 %

> 45 kHz −−25 %

delay time for changing polarity 0.3 − 1.8 ms

integration time for generation of a vertical trigger pulse

fH= 31.45 kHz; I

= 1.052 mA

HREF

= 64 kHz;

= 2.141 mA

HREF

= 100 kHz;

= 3.345 mA

HREF

71013µs

3.9 5.7 6.5 µs

2.5 3.8 4.5 µs

sync input signal voltage 1.7 −−V slicing voltage level 1.2 1.4 1.6 V input current 0 V < V

< 5.5 V −−±10 µA

SYNC

1996 Jul 18 13

Philips Semiconductors Preliminary speciﬁcation

Autosync Deﬂection Controller (ASDC) TDA4855

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VERTICAL SYNC OUTPUT AT VSYNC (PIN 14) DURING COMPOSITE SYNC AT HSYNC (PIN 15) I

VSYNC

output current during internal vertical

sync

VSYNC

internal clamping voltage level during internal vertical

sync

steepness of slopes − 300 − ns/mA

Automatic polarity correction for vertical sync

VSYNC(max)

maximum width of vertical sync pulse

d(VPOL)

delay for changing polarity 0.3 − 1.8 ms

Video clamping/vertical blanking output [CLBL (pin 16)]

clamp(CLBL)

width of video clamping pulse measured at V top voltage level of video

clamping pulse

d(clamp)

clamp(max)

delay between trailing edge of horizontal sync and start of video clamping pulse

maximum duration of video

clamping pulse triggered on trailing edge of horizontal sync

measured at V clamping pulse referenced to end of horizontal sync

clamp

temperature coefﬁcient of V

clamp(CLBL)

steepness of slopes for

=1MΩ; CL=20pF − 50 − ns/V

clamping pulse

blank(CLBL)

top voltage level of vertical

notes 1 and 2 1.7 1.9 2.1 V blanking pulse

blank(CLBL)

width of vertical blanking pulse VGA presets active 500 575 650 µs

VGA presets disabled 240 300 360 µs

blank

scan(CLBL)

temperature coefﬁcient of V

blank(CLBL)

output voltage during vertical

= 0 0.59 0.63 0.67 V

CLBL

scan

sink(CLBL)

load(CLBL)

temperature coefﬁcient of V

scan(CLBL)

internal sink current 2.4 −−mA external load current −−−3.0 mA

= 3 V 0.6 0.7 0.8 µs

CLBL

=3V −−1.0 µs

CLBL

−0.7 −1.0 −1.35 mA

4.4 4.8 5.2 V

−−300 µs

4.32 4.75 5.23 V

− 130 − ns

− +4 − mV/K

− +2 − mV/K

−−2−mV/K

1996 Jul 18 14

+ 30 hidden pages

Philips TDA4855 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Synchronization inputs

Horizontal section

Vertical section

EW section

GENERAL DESCRIPTION

QUICK REFERENCE DATA

ORDERING INFORMATION

BLOCK DIAGRAM

PINNING

Vertical sync integrator

Vertical sync slicer and polarity correction

Video clamping/vertical blanking generator

VGA mode detector

Frequency-locked loop

PLL1 phase detector

Calculation of line frequency range

Horizontal oscillator

PLL2 phase detector

Horizontal phase adjustment

Output stage for line drive pulses

X-ray protection

Vertical oscillator and amplitude control

Adjustment of vertical size, vertical shift and S-correction

EW parabola (including horizontal size and trapezium correction)

Dynamic focus section

B+ control function block

Supply voltage stabilizer, references and protection

LIMITING VALUES

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION

CHARACTERISTICS