Philips TDA4851 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA4851

Horizontal and vertical deflection controller for VGA/XGA and autosync monitors

Preliminary speciﬁcation File under Integrated Circuits, IC02

November 1992

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller

TDA4851

for VGA/XGA and autosync monitors

FEATURES

• VGA operation fully implemented including alignment-free vertical and E/W amplitude presettings

• 4th VGA mode easy applicable (XGA, Super VGA)

• Autosync operation externally selectable

• Low jitter

• All adjustments DC-controllable

• Alignment-free oscillators

• Sync separators for video or horizontal and vertical TTL

sync levels regardless of polarity

• Horizontal oscillator with PLL1 for sync and PLL2 for flyback

• Constant vertical and E/W amplitude in autosync operation

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V I

i sync

positive supply voltage (pin 1) 9.2 12 16 V supply current − 40 − mA AC-coupled composite video signal with negative-going sync

(peak-to-peak value, pin 9) sync slicing level − 120 − mV DC-coupled TTL-compatible horizontal sync signal (peak-to-peak value,

pin 9) slicing level 1.2 1.4 1.6 V DC-coupled TTL-compatible vertical sync signal (peak-to-peak value,

pin 10)

slicing level 1.2 1.4 1.6 V I I T

o V o H

amb

vertical differential output current (peak-to-peak value, pins 5 and 6) − 1 − mA

horizontal sink output current on pin 3 −−60 mA

operating ambient temperature range 0 −+70 °C

• DC-coupling to vertical power amplifier

• Internal supply voltage stabilization with excellent ripple

rejection to ensure stable geometrical adjustments

GENERAL DESCRIPTION

The TDA4851 is a monolithic integrated circuit for economical solutions in VGA/XGA and autosync monitors. The IC incorporates the complete horizontal and vertical small signal processing. VGA-dependent mode detection and settings are performed on chip. In conjunction with TDA4860/61/65, or TDA8351 (vertical output circuits) the ICs offer an extremely advanced system solution.

− 1 − V

1.7 −− V

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

PINS

PIN POSITION

TDA4851 20 DIL plastic SOT146

Note

1. SOT146-1; 1996 November 26.

November 1992 2

PACKAGE

MATERIAL CODE

(1)

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November 1992 3

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and autosync monitors

Fig.1 Block diagram.

TDA4851

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and autosync monitors

PINNING

SYMBOL PIN DESCRIPTION

FLB 2 horizontal ﬂyback input HOR 3 horizontal output GND 4 ground (0 V) VERT1 5 vertical output 1; negative-going sawtooth VERT2 6 vertical output 2; positive-going sawtooth MODE 7 4th mode output and autosync input CLBL 8 clamping/blanking pulse output HVS 9 horizontal sync/video input VS 10 vertical sync input EW 11 E/W output (parabola to driver stage) C

VOS

PLL1 17 PLL1 phase R

HOS

PLL2 20 PLL2 phase

1 positive supply voltage

12 capacitor for amplitude control 13 vertical amplitude adjustment input 14 E/W amplitude adjustment input (parabola) 15 vertical oscillator resistor 16 vertical oscillator capacitor

18 horizontal oscillator resistor 19 horizontal oscillator capacitor

TDA4851

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction

An AC-coupled video signal or a DC-coupled TTL sync signal (H only or composite sync) is input on pin 9. Video signals are clamped with top sync on 1.28 V, and are sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to top sync. DC-coupled TTL sync signals are also sliced at 1.4 V, however with the clamping circuit in current limitation. The polarity of the separated sync is detected by internal integration of the signal, then the polarity is corrected. The polarity information is fed to the VGA mode detector. The corrected sync is input signal for the vertical sync integrator and the PLL1 stage.

Vertical sync separator, polarity correction and vertical sync integrator

DC-coupled vertical TTL sync signals may be applied to pin 10. They are sliced at 1.4 V. The polarity of the separated sync is detected by internal integration, then the polarity is corrected. The polarity information is fed to the

VGA mode detector. If pin 10 is not used, it must be connected to ground. The separated V

signal from

i sync

pin10, or the integrated composite sync signal from pin 9 (TTL or video) triggers directly the vertical oscillator.

VGA mode detector and mode output

The three standard VGA modes and a 4th not fixed mode are decoded by the polarities of the horizontal and the vertical sync input signals. An external resistor (from V

pin 7) is necessary to match this function. In all three VGA modes the correct amplitudes are activated. The presence of the 4th mode is indicated by a HIGH on pin 7. This signal can be used externally to switch any horizontal or vertical parameters.

VGA mode detector input

For autosync operation the voltage on pin 7 must be externally forced to a level of < 50 mV. Vertical amplitude pre-settings for VGA are then inhibited. The delay time between vertical trigger pulse and the start of vertical deflection changes from 575 µs to 300 µs (575 µs is

November 1992 4

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and autosync monitors

needed for VGA). The vertical amplitude then remains constant in a frequency range from 50 Hz up to 110 Hz.

Clamping and V-blanking generator

A combined clamping and V-blanking pulse is available on pin 8 (suitable for the video pre-amplifier TDA4881). The lower level of 1.9 V is the blanking signal derived from the vertical blanking pulse from the internal vertical oscillator. Vertical blanking equals the delay between vertical sync and start of vertical scan. By this, an optimum blanking is achieved for VGA/XGA and autosync operation (selectable via pin 7). The upper level of 5.4 V is the horizontal clamping pulse with an internally fixed pulse width of 0.8 µs. A monoflop, which is triggered by the trailing edge of the horizontal sync pulse, generates this pulse. If composite sync is applied, one clamping pulse per H-period is generated during V-sync. The phase of the clamping pulse may change during V-sync (see Fig.8).

PLL1 phase detector

The phase detector is a standard type using switched current sources. The middle of the sync is compared with a fixed point of the oscillator sawtooth voltage. The PLL filter is connected to pin 17. If composite sync is applied, the disturbed control voltage is corrected during V-sync (see Fig.8).

Horizontal oscillator

TDA4851

A certain amount of phase adjustment is possible by injecting a DC current from an external source into the PLL2 filter capacitor at pin 20.

Horizontal driver

This open-collector output stage (pin 3) can directly drive an external driver transistor. The saturation voltage is less than 300 mV at 20 mA. To protect the line deflection transistor, the horizontal output stage does not conduct for V

Vertical oscillator and amplitude control

This stage is designed for fast stabilization of the vertical amplitude after changes in sync conditions. The free-running frequency f R

VOS

and C

. The recommended values should be

VOS

is determined by the values of

altered marginally only to preserve the excellent linearity and noise performance. The vertical drive currents I I

are in relation to the value of R

Therefore, the oscillator frequency must be determined only by C

on pin 16.

VOS

-----------------------------------------------------

10.8 R

× C

VOS

To achieve a stabilized amplitude the free-running frequency f

(without adjustment) must be lower than the

lowest occurring sync frequency. The following contributions can be assumed:

VOS

< 6.4 V (pin 1).

VOS

and

This oscillator is of the relaxation type and requires a fixed capacitor of 10 nF at pin 19. By changing the current into pin 18 the whole frequency range from 13 to 100 kHz can be covered. The current can be generated either by a frequency to voltage converter or by a resistor. A frequency adjustment may also be added if necessary. The PLL1 control voltage at pin 17 modulates via a buffer stage the oscillator thresholds. A high DC-loop gain ensures a stable phase relationship between horizontal sync and line flyback pulses.

PLL2 phase detector

This phase detector is similar to the PLL1 phase detector. Line flyback signals (pin 2) are compared with a fixed point of the oscillator sawtooth voltage. Delays in the horizontal deflection circuit are compensated by adjusting the phase relationship between horizontal sync and horizontal output pulses.

November 1992 5

minimum frequency offset between f

and the

lowest trigger frequency 10% spread of IC ±3% spread of R (22 kΩ) ±1% spread of C (0.1 µF) ±5%

19%

Result:f

Hz 42 Hz==

-----------

1.19

(for 50 to 110 Hz application)

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller

TDA4851

for VGA/XGA and autosync monitors

Table 1 VGA modes

MODE

H / V SYNC

POLARITY

1 + / − 31.45 70 350 LOW 2 − / + 31.45 70 400 LOW 3 − / − 31.45 60 480 LOW 4 + / + ﬁxed by external circuitry −−HIGH autosync */* ﬁxed by external circuitry −−forced to GND

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL PARAMETER MIN. MAX. UNIT

3,7

stg

amb

supply voltage (pin 1) −0.5 16 V voltage on pins 3 and 7 −0.5 16 V voltage on pin 8 −0.5 7 V voltage on pins 5, 6, 9, 10, 13, 14 and 18 −0.5 6.5 V current on pin 2 −±10 mA current on pin 3 − 100 mA current on pin 7 − 20 mA current on pin 8 −−10 mA storage temperature range −55 +150 °C

operating ambient temperature range 0 70 °C Tj maximum junction temperature 0 +150 °C V

ESD

electrostatic handling for all pins (note 1) −±400 V

FREQUENCY H

(kHz)

FREQUENCY V

(Hz)

NUMBER OF

ACTIVE LINES

MODE OUTPUT

PIN 7

Note to the Limiting Values

1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.

THERMAL RESISTANCE

SYMBOL PARAMETER THERMAL RESISTANCE

th j-a

from junction to ambient in free air 65 K/W

November 1992 6

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