Philips TDA4850-V2, TDA4850-V1 Datasheet
DATA SH EET
Product specification
Supersedes data of September 1991
File under Integrated Circuits, IC02
1997 Jun 05
INTEGRATED CIRCUITS
TDA4850
Horizontal and vertical deflection
controller for VGA/XGA and
multi-frequency monitors
1997 Jun 05 2
Philips Semiconductors Product specification
Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors
TDA4850
FEATURES
• VGA operation fully implemented including
alignment-free vertical and E/W amplitude pre-settings
• 4th VGA mode easy applicable (XGA, Super VGA)
• Multi-frequency operation externally selectable
• All adjustments DC-controllable
• Alignment-free oscillators
• Sync separators for video or horizontal and vertical TTL
sync levels regardless of polarity
• Horizontal oscillator with PLL1 for sync and PLL2 for
flyback
• Constant vertical and E/W amplitude in multi-frequency
operation
• DC-coupling to vertical power amplifier (TDA486X or
TDA8351)
• Internal supply voltage stabilization with excellent ripple
rejection to ensure stable geometrical adjustments.
GENERAL DESCRIPTION
The TDA4850 provides economical solutions in VGA/XGA
and multi-frequency monitors. The IC incorporates the
complete horizontal and vertical small signal processing.
VGA-dependent mode detection and settings are
performed on chip. In conjunction with TDA486X or
TDA8351 (vertical output circuits) both ICs offer an
extremely advanced system solution.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
P
supply voltage (pin 1) 9.2 12 16 V
I
P
supply current − 40 − mA
V
i sync
AC-coupled composite video signal with negative-going sync
(peak-to-peak value; pin 9)
− 1 − V
sync slicing level − 120 − mV
DC-coupled TTL-compatible horizontal sync signal
(peak value; pin 9)
1.7 −−V
slicing level 1.2 1.4 1.6 V
DC-coupled TTL-compatible vertical sync signal
(peak value; pin 10)
1.7 −−V
slicing level 1.2 1.4 1.6 V
I
oV
vertical differential output current (peak-to-peak value;
pins 5 and 6)
− 1 − mA
I
oH
horizontal sink output current on pin 3 −−60 mA
T
amb
operating ambient temperature 0 − 70 °C
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
TDA4850 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
1997 Jun 05 3
Philips Semiconductors Product specification
Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors
TDA4850
BLOCK DIAGRAM
andbook, full pagewidth
MEH165
HORIZONTAL
SYNC
SEPARATOR
(TTL VIDEO SYNC)
AUTOMATIC
POLARITY
CORRECTION
9
7
+
17 18
R
HOS
C
HOS
19
DC-coupled
(TTL level)
10
vertical sync
(TTL level)
mode
detector
disable
4th mode
AC-coupled
(video)
PLL1
HORIZONTAL
OSCILLATOR
HORIZONTAL
OUTPUT
20
3
2
PLL2
horizontal
flyback
SUPPLY AND
REFERENCE
VOLTAGE
PARABOLA
ADJUSTMENT
AND OUTPUT
VERTICAL
AMPLITUDE
ADJUSTMENT
AND OUTPUT
VERTICAL
OSCILLATOR
AMPLITUDE
CONTROL
VERTICAL
SYNC
INTEGRATOR
H
+
V
CLAMPING AND
BLANKING
GENERATOR
VGA/MULTI-
FREQUENCY
SWITCH
VGA MODE
DETECTOR
AND OUTPUT
AUTOMATIC
POLARITY
CORRECTION
VERTICAL
SYNC
SEPARATOR
4
1
14
VP(9.2 to 16 V)
E/W drive
horizontal drive
parabola
amplitude
+
V
B
11
differential vertical output
V supply
H supply
R
VOS
158
clamping/
blanking
pulse
C
VOS
16
C
VA
12 13 5 6
vertical amplitude
TDA4850
Fig.1 Block diagram.
1997 Jun 05 4
Philips Semiconductors Product specification
Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors
TDA4850
PINNING
SYMBOL PIN DESCRIPTION
V
P
1 positive supply voltage
FLB 2 horizontal flyback input
HOR 3 horizontal output
GND 4 ground (0 V)
VERT1 5 vertical output 1;
negative-going sawtooth
VERT2 6 vertical output 2;
positive-going sawtooth
MODE 7 4th mode output and mode detector
disable input
CLBL 8 clamping/blanking pulse output
HVS 9 horizontal sync/video input
VS 10 vertical sync input
EW 11 E/W output (parabola to driver stage)
C
VA
12 capacitor for amplitude control
R
VA
13 vertical amplitude adjustment input
R
EW
14 E/W amplitude adjustment input
(parabola)
R
VOS
15 vertical oscillator resistor
C
VOS
16 vertical oscillator capacitor
PLL1 17 PLL1 phase
R
HOS
18 horizontal oscillator resistor
C
HOS
19 horizontal oscillator capacitor
PLL2 20 PLL2 phase
Fig.2 Pin configuration.
handbook, halfpage
V
P
FLB
HOR
GND
VERT1
VERT2
MODE
CLBL
HVS
VS
PLL2
C
HOS
R
HOS
PLL1
R
VOS
R
EW
C
VOS
R
VA
C
VA
EW
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
TDA4850
MEH168
1997 Jun 05 5
Philips Semiconductors Product specification
Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors
TDA4850
FUNCTIONAL DESCRIPTION
Horizontal sync separator and polarity correction
An AC-coupled video signal or a DC-coupled TTL sync
signal (H only or composite sync) is input on pin 9. Video
signals are clamped with top sync on 1.28 V, and are
sliced at 1.4 V. This results in a fixed absolute slicing level
of 120 mV related to top sync.
DC-coupled TTL sync signals are also sliced at 1.4 V,
however with the clamping circuit in current limitation.
The polarity of the separated sync is detected by internal
integration of the signal, then the polarity is corrected.
The polarity information is fed to the VGA mode detector.
The corrected sync is input signal for the vertical sync
integrator and the PLL1 stage.
Vertical sync separator, polarity correction and
vertical sync integrator
DC-coupled vertical TTL sync signals may be applied to
pin 10. They are sliced at 1.4 V. The polarity of the
separated sync is detected by internal integration, then
polarity is corrected. The polarity information is fed to the
VGA mode detector. If pin 10 is not used, it must be
connected to ground.
The separated V
i(sync)
signal from pin 10, or the integrated
composite sync signal from pin 9 (TTL or video) triggers
directly the vertical oscillator.
VGA mode detector and mode output
The three standard VGA modes and a 4th not fixed mode
are decoded by the polarities of the horizontal and the
vertical sync input signals. An external resistor (from V
P
to
pin 7) is necessary to match this function. In all three VGA
modes the correct amplitudes are activated. The presence
of the 4th mode is indicated by HIGH on pin 7. This signal
can be used externally to switch any horizontal or vertical
parameters.
VGA mode detector input
For multi-frequency operation the voltage on pin 7 must be
externally forced to a level of <50 mV. Vertical amplitude
pre-settings for VGA are then inhibited. The delay time
between vertical trigger pulse and the start of vertical
deflection changes from 575 to 300 µs (575 µs is needed
for VGA). The vertical amplitude then remains constant in
a frequency range from 50 to 110 Hz.
Clamping and blanking generator
A combined clamping and blanking pulse is available on
pin 8 (suitable for the video preamplifier TDA4880).
The lower level of 2.1 V can be the blanking signal derived
from line flyback, or the vertical blanking pulse from the
internal vertical oscillator.
Vertical blanking equals to the delay between vertical sync
and start of vertical scan. By this, an optimum blanking is
achieved for VGA/XGA as well as for multi-frequency
operation (selectable via pin 7).
The upper level of 3.9 V is the horizontal clamping pulse
with internally fixed pulse width of 1 µs. A mono flop, which
is triggered by the trailing edge of the horizontal sync
pulse, generates this pulse.
PLL1 phase detector
The phase detector is a standard one using switched
current sources. The middle of the sync is compared with
a fixed point of the oscillator sawtooth voltage. The PLL
filter is connected to pin 17.
Horizontal oscillator
This oscillator is a relaxation type oscillator. Its frequency
is determined mainly by the capacitor on pin 19.
A frequency range of one octave is achieved by the current
on pin 18. The ϕ1 control voltage from pin 17 is fed via a
buffer amplifier and an attenuator to the current reference
pin 18 to achieve a high DC loop gain. Therefore, changes
in frequency will not affect the phase relationship between
horizontal sync pulses and line flyback pulses.
PLL2 phase detector
This phase detector is similar to the PLL1 phase detector.
Line flyback signals (pin 2) are compared with a fixed point
of the oscillator sawtooth voltage. Delays in the horizontal
deflection circuit are compensated by adjusting the phase
relationship between horizontal sync and horizontal output
pulses.
A certain amount of phase adjustments is possible by
injecting a DC current from an external source into the
PLL2 filter capacitor on pin 20.
1997 Jun 05 6
Philips Semiconductors Product specification
Horizontal and vertical deflection controller
for VGA/XGA and multi-frequency monitors
TDA4850
Horizontal driver
This open-collector output stage (pin 3) can directly drive
an external driver transistor. The saturation voltage is
300 mV at 20 mA. To protect the line deflection transistor,
the horizontal output stage does not conduct at VP< 6.4 V
(pin 1).
Vertical oscillator and amplitude control
This stage is designed for fast stabilization of the vertical
amplitude after changes in sync conditions.
The free-running frequency f
o
is determined by the values
of R
VOS
and C
VOS
. The recommended values should be
altered marginally only to preserve the excellent linearity
and noise performance. The vertical drive currents I
5
and
I
6
are in relation to the value of R
VOS
. Therefore, the
oscillator frequency must be determined only by C
VOS
on
pin 16.
f
o
1
10.8 R
VOS
× C
VOS
×
----------------------------------------------------
=
To achieve a stabilized amplitude the free-running
frequency f
o
(without adjustment) must be lower than the
lowest occurring sync frequency. The contributions shown
in Table 1 can be assumed.
Table 1 Calculation of f
o
total spread
Result for 50 to 110 Hz application:
CONTRIBUTING ELEMENTS %
Minimum frequency offset between f
o
and
the lowest trigger frequency
10
Spread of IC ±3
Spread of R (22 kΩ) ±1
Spread of C (0.1 µF) ±5
Total 19
f
o
50 Hz
1.19
---------------
42 Hz==
Table 2 VGA modes
MODE
HORIZONTAL/VERTICAL
SYNC POLARITY
HORIZONTAL
FREQUENCY
(kHz)
VERTICAL
FREQUENCY
(Hz)
NUMBER OF
ACTIVE LINES
MODE
OUTPUT PIN 7
1+/− 31.45 70 350 LOW
2 −/+ 31.45 70 400 LOW
3 −/− 31.45 60 480 LOW
4 +/+ fixed by external circuitry −−HIGH
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