Philips TDA4850 Service Manual

INTEGRATED CIRCUITS

DATA SH EET

TDA4850

Horizontal and vertical deflection controller for VGA/XGA and multi-frequency monitors

Product speciﬁcation Supersedes data of September 1991 File under Integrated Circuits, IC02

1997 Jun 05

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and multi-frequency monitors

FEATURES

• VGA operation fully implemented including alignment-free vertical and E/W amplitude pre-settings

• 4th VGA mode easy applicable (XGA, Super VGA)

• Multi-frequency operation externally selectable

• All adjustments DC-controllable

• Alignment-free oscillators

• Sync separators for video or horizontal and vertical TTL

sync levels regardless of polarity

• Horizontal oscillator with PLL1 for sync and PLL2 for flyback

• Constant vertical and E/W amplitude in multi-frequency operation

• DC-coupling to vertical power amplifier (TDA486X or TDA8351)

• Internal supply voltage stabilization with excellent ripple rejection to ensure stable geometrical adjustments.

GENERAL DESCRIPTION

The TDA4850 provides economical solutions in VGA/XGA and multi-frequency monitors. The IC incorporates the complete horizontal and vertical small signal processing. VGA-dependent mode detection and settings are performed on chip. In conjunction with TDA486X or TDA8351 (vertical output circuits) both ICs offer an extremely advanced system solution.

TDA4850

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V I

i sync

supply voltage (pin 1) 9.2 12 16 V supply current − 40 − mA AC-coupled composite video signal with negative-going sync

− 1 − V

(peak-to-peak value; pin 9) sync slicing level − 120 − mV DC-coupled TTL-compatible horizontal sync signal

1.7 −−V

(peak value; pin 9) slicing level 1.2 1.4 1.6 V DC-coupled TTL-compatible vertical sync signal

1.7 −−V

(peak value; pin 10) slicing level 1.2 1.4 1.6 V

vertical differential output current (peak-to-peak value;

− 1 − mA

pins 5 and 6) I T

amb

horizontal sink output current on pin 3 −−60 mA

operating ambient temperature 0 − 70 °C

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA4850 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

1997 Jun 05 2

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and multi-frequency monitors

BLOCK DIAGRAM

parabola

amplitude

VP(9.2 to 16 V)

SUPPLY AND

V supply

andbook, full pagewidth

vertical amplitude

clamping/

blanking

pulse

E/W drive

differential vertical output

VOS

12 13 5 6

158

PARABOLA

AND OUTPUT

ADJUSTMENT

VERTICAL

AMPLITUDE

ADJUSTMENT

VERTICAL

AMPLITUDE

OSCILLATOR

SYNC

VERTICAL

INTEGRATOR

AND OUTPUT

CONTROL

VOLTAGE

REFERENCE

H supply

TDA4850

BLANKING

GENERATOR

CLAMPING AND

horizontal drive

OUTPUT

HORIZONTAL

PLL2

HORIZONTAL

PLL1

OSCILLATOR

17 18

MEH165

HOS

TDA4850

flyback

horizontal

Fig.1 Block diagram.

POLARITY

AUTOMATIC

CORRECTION

SYNC

VERTICAL

SEPARATOR

(TTL level)

vertical sync

1997 Jun 05 3

SWITCH

VGA/MULTI-

FREQUENCY

VGA MODE

DETECTOR

AND OUTPUT

4th mode

mode

detector

disable

POLARITY

AUTOMATIC

CORRECTION

SYNC

SEPARATOR

HORIZONTAL

(TTL VIDEO SYNC)

(TTL level)

DC-coupled

(video)

AC-coupled

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and multi-frequency monitors

PINNING

SYMBOL PIN DESCRIPTION

FLB 2 horizontal ﬂyback input HOR 3 horizontal output GND 4 ground (0 V) VERT1 5 vertical output 1;

VERT2 6 vertical output 2;

MODE 7 4th mode output and mode detector

CLBL 8 clamping/blanking pulse output HVS 9 horizontal sync/video input VS 10 vertical sync input EW 11 E/W output (parabola to driver stage) C

VOS

PLL1 17 PLL1 phase R

HOS

PLL2 20 PLL2 phase

1 positive supply voltage

negative-going sawtooth

positive-going sawtooth

disable input

12 capacitor for amplitude control 13 vertical amplitude adjustment input 14 E/W amplitude adjustment input

(parabola) 15 vertical oscillator resistor 16 vertical oscillator capacitor

18 horizontal oscillator resistor 19 horizontal oscillator capacitor

handbook, halfpage

FLB

HOR

GND

VERT1

5 6 7 8 9

TDA4850

MEH168

VERT2

MODE

CLBL

HVS

Fig.2 Pin configuration.

TDA4850

PLL2

20 19

HOS

PLL1

VOS

1997 Jun 05 4

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and multi-frequency monitors

FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction

An AC-coupled video signal or a DC-coupled TTL sync signal (H only or composite sync) is input on pin 9. Video signals are clamped with top sync on 1.28 V, and are sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to top sync.

DC-coupled TTL sync signals are also sliced at 1.4 V, however with the clamping circuit in current limitation. The polarity of the separated sync is detected by internal integration of the signal, then the polarity is corrected.

The polarity information is fed to the VGA mode detector. The corrected sync is input signal for the vertical sync integrator and the PLL1 stage.

Vertical sync separator, polarity correction and vertical sync integrator

DC-coupled vertical TTL sync signals may be applied to pin 10. They are sliced at 1.4 V. The polarity of the separated sync is detected by internal integration, then polarity is corrected. The polarity information is fed to the VGA mode detector. If pin 10 is not used, it must be connected to ground.

The separated V composite sync signal from pin 9 (TTL or video) triggers directly the vertical oscillator.

VGA mode detector and mode output

The three standard VGA modes and a 4th not fixed mode are decoded by the polarities of the horizontal and the vertical sync input signals. An external resistor (from V pin 7) is necessary to match this function. In all three VGA modes the correct amplitudes are activated. The presence of the 4th mode is indicated by HIGH on pin 7. This signal can be used externally to switch any horizontal or vertical parameters.

VGA mode detector input

For multi-frequency operation the voltage on pin 7 must be externally forced to a level of <50 mV. Vertical amplitude pre-settings for VGA are then inhibited. The delay time between vertical trigger pulse and the start of vertical deflection changes from 575 to 300 µs (575 µs is needed for VGA). The vertical amplitude then remains constant in a frequency range from 50 to 110 Hz.

signal from pin 10, or the integrated

i(sync)

TDA4850

Clamping and blanking generator

A combined clamping and blanking pulse is available on pin 8 (suitable for the video preamplifier TDA4880). The lower level of 2.1 V can be the blanking signal derived from line flyback, or the vertical blanking pulse from the internal vertical oscillator.

Vertical blanking equals to the delay between vertical sync and start of vertical scan. By this, an optimum blanking is achieved for VGA/XGA as well as for multi-frequency operation (selectable via pin 7).

The upper level of 3.9 V is the horizontal clamping pulse with internally fixed pulse width of 1 µs. A mono flop, which is triggered by the trailing edge of the horizontal sync pulse, generates this pulse.

PLL1 phase detector

The phase detector is a standard one using switched current sources. The middle of the sync is compared with a fixed point of the oscillator sawtooth voltage. The PLL filter is connected to pin 17.

Horizontal oscillator

This oscillator is a relaxation type oscillator. Its frequency is determined mainly by the capacitor on pin 19. A frequency range of one octave is achieved by the current on pin 18. The ϕ1 control voltage from pin 17 is fed via a buffer amplifier and an attenuator to the current reference pin 18 to achieve a high DC loop gain. Therefore, changes in frequency will not affect the phase relationship between horizontal sync pulses and line flyback pulses.

PLL2 phase detector

This phase detector is similar to the PLL1 phase detector. Line flyback signals (pin 2) are compared with a fixed point of the oscillator sawtooth voltage. Delays in the horizontal deflection circuit are compensated by adjusting the phase relationship between horizontal sync and horizontal output pulses.

A certain amount of phase adjustments is possible by injecting a DC current from an external source into the PLL2 filter capacitor on pin 20.

1997 Jun 05 5

Philips Semiconductors Product speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and multi-frequency monitors

Horizontal driver

This open-collector output stage (pin 3) can directly drive an external driver transistor. The saturation voltage is 300 mV at 20 mA. To protect the line deflection transistor, the horizontal output stage does not conduct at VP< 6.4 V (pin 1).

Vertical oscillator and amplitude control

This stage is designed for fast stabilization of the vertical amplitude after changes in sync conditions. The free-running frequency f of R

VOS

and C

. The recommended values should be

VOS

altered marginally only to preserve the excellent linearity and noise performance. The vertical drive currents I I

are in relation to the value of R

oscillator frequency must be determined only by C pin 16.

----------------------------------------------------

10.8 R

× C

VOS

is determined by the values

and

. Therefore, the

VOS

TDA4850

To achieve a stabilized amplitude the free-running frequency f lowest occurring sync frequency. The contributions shown in Table 1 can be assumed.

Table 1 Calculation of f

Minimum frequency offset between f the lowest trigger frequency

Spread of IC ±3 Spread of R (22 kΩ) ±1 Spread of C (0.1 µF) ±5 Total 19

Result for 50 to 110 Hz application:

(without adjustment) must be lower than the

total spread

CONTRIBUTING ELEMENTS %

and

50 Hz

---------------

1.19

42 Hz==

Table 2 VGA modes

MODE

HORIZONTAL/VERTICAL

SYNC POLARITY

HORIZONTAL

FREQUENCY

(kHz)

VERTICAL

FREQUENCY

(Hz)

NUMBER OF

ACTIVE LINES

OUTPUT PIN 7

1+/− 31.45 70 350 LOW 2 −/+ 31.45 70 400 LOW 3 −/− 31.45 60 480 LOW 4 +/+ ﬁxed by external circuitry −−HIGH

MODE

1997 Jun 05 6

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