Philips TDA4800 Datasheet

INTEGRATED CIRCUITS

DATA SH EET

TDA4800

Vertical deflection circuit for monitor applications

Product speciﬁcation Supersedes data of February 1992 File under Integrated Circuits, IC02

1997 Mar 27

Philips Semiconductors Product speciﬁcation

Vertical deﬂection circuit for monitor applications

FEATURES

• Fully integrated, few external components

• RC oscillator with wide sync range of 1 : 3 (e.g.

50 to 150 Hz)

• Synchronization by positive or negative going sync pulse

• Blanking pulse duration is determined externally

• Dual frequency criterion for automatic amplitude

switch-over (e.g. 50 to 60 Hz)

• Guard circuit for screen protection

• Sawtooth generator with buffer stage supplied by

external voltage

• Preamplifier

• Power output stage with thermal and SOAR protection

• Flyback generator

• Internal voltage stabilizer.

TDA4800

GENERAL DESCRIPTION

The TDA4800 is an integrated circuit for vertical deflection primarily in monitors (and TV receivers). The complete circuit consists of 11 main functional blocks as shown in Fig.1.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

7(p-p)

sync

amb

supply voltage (pin 6) 10 − 30 V supply voltage (pin 10) 10 − 45 V supply current (pins 6 and 10) note 1 − 215 − mA output current (peak-to-peak value) −−2.6 A picture frequency notes 1 and 2 −−135 Hz positive sync input pulse 1.0 − 6.0 V negative sync input pulse −0.5 −−0.7 V operating ambient temperature note 3 −20 − +70 °C

Notes

1. Measured in Fig.4.

2. f

3. P

= 45 Hz (f

= 3.6 W for R

tot

sync(max)

th(j-a)

=3fo).

= 20 K/W.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA4800 DBS13P

plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)

PACKAGE

SOT141-6

1997 Mar 27 2

Philips Semiconductors Product speciﬁcation

Vertical deﬂection circuit for monitor applications

BLOCK DIAGRAM

handbook, full pagewidth

SYNC

CIRCUIT

OSCILLATOR

TDA4800

RAMP

GENERATOR

BLANKING

PULSE

GENERATOR

BUFFER

STAGE

2 V

PRE-

AMPLIFIER

GUARD

CIRCUIT

POWER

OUTPUT STAGE

THERMAL AND

SOAR PROTECTION

TDA4800

VOLTAGE

STABILIZER

FLYBACK

GENERATOR

FREQUENCY

DETECTOR

R1 (frequency)

R17 R2

sync input

blank

output

4325679810 11 12 13

D2

BAX18

R14

C12

VP2 = 23 V

amplitude

R13

R12

MHA590

D1 1N4148

R3 R4

amplitude

linearity

vertical

deflection

unit

6.5 Ω

6.5 mH

R10

C11C10 R15

R16

R11

frequency criterion

Fig.1 Block diagram.

1997 Mar 27 3

Philips Semiconductors Product speciﬁcation

Vertical deﬂection circuit for monitor applications

PINNING

SYMBOL PIN DESCRIPTION

OSC

SYB

OUT

PRE

OUTP 7 deﬂection output GND 8 ground C

FLY

GEN

FRQ

1 oscillator resistor 2 oscillator capacitor 3 sync input; blanking pulse output 4 sawtooth output 5 preampliﬁer input 6 supply voltage 1

9 pin for the ﬂyback generator capacitor 10 supply voltage 2 11 sawtooth generator 12 blanking pulse duration 13 frequency criterion

handbook, halfpage

OSC OSC SYB S

OUT

PRE

OUTP

GND

FLY V

GEN

FRQ

R C O

TDA4800

1 2 3 4 5 6 7

TDA4800

9 10 11 12 13

MHA584

Fig.2 Pin configuration.

1997 Mar 27 4

Philips Semiconductors Product speciﬁcation

Vertical deﬂection circuit for monitor applications

FUNCTIONAL DESCRIPTION

The complete circuit consists of the following functional blocks as shown in Fig.1:

1. Oscillator

2. Synchronization circuit

3. Blanking pulse generator

4. Frequency detector and storage

5. Ramp generator

6. Buffer stage

7. Preamplifier

8. Power output stage

9. Flyback generator

10. Guard circuit

11. Voltage stabilizer.

Oscillator (pins 1 and 2)

The oscillator is an RC-oscillator with a threshold value switch, which ensures very good frequency stability.

The upper and lower threshold voltages are defined by an internal voltage divider.

An external capacitor C1 at pin 2 is charged by a constant current source. When the scan voltage of C1 reaches the upper threshold voltage, oscillator flyback starts. Capacitor C1 discharges via an internal resistor and transistor until the lower threshold is reached.

The constant charge current and free-running frequency f are adjusted by an external resistor R1 at pin 1:

-------------------------------KR1× C1×

Synchronization circuit (pin 3)

A positive- or negative-going pulse fed to pin 3 synchronizes the oscillator by lowering the upper threshold voltage. The synchronizing range is f fo=50Hz→ f

Blanking pulse generator (pin 3)

Also at pin 3 a blanking pulse is available. Diode D1 separates the synchronization pulse from the blanking pulse. During scanning, the external capacitor C6 at pin 12 is charged to an internal stabilized voltage V The blanking pulse starts with the beginning of oscillator flyback; then capacitor C6 discharges via the external resistor R13 at pin 12. The blanking pulse stops when the capacitor voltage is1⁄2V

with K = 0.68.

sync(max)

= 150 Hz.

stab2

to 3fo. For example:

stab2

TDA4800

The blanking pulse duration is determined by the values of external components R13 and C6 at pin 12:

= R13 × C6 × Ln2.

Frequency detector with storage (pin 13)

At the end of the scanning period a frequency detector detects the oscillator frequency (see “Note” below).

When this frequency is above the threshold a flip-flop is set to store this information. The output is an open collector output.

OTE

N Frequency detector change-over at pin 13 from low (= low

frequency) to high (= high frequency) is determined by fo: f

threshold

Ramp generator (pin 11)

The ramp generator consists of two external series capacitors C4 and C5, external charge resistor R12 (connected to pin 11), and an internal differential amplifier which is synchronously switched by the oscillator.

External capacitors C4 and C5 at pin 11 are charged by the charging current via the external charge resistor R12 until oscillator flyback starts. C4 and C5 are then discharged via pin 11 by an internal resistor and transistor. This generates a positive-going ramp voltage.

Buffer stage (pin 4)

The buffer stage consists of two emitter followers. The ramp voltage is fed via the buffer stage and is available at pin 4 with a low ohmic output impedance. With R4 and P1 it generates a ramp function, which, together with the feedback network of the deflection yoke, gives a high degree of linearity at the picture tube. The linearity can be adjusted by P1.

Preampliﬁer (pin 5)

The preamplifier is a differential amplifier. The non-inverting input is fixed at about 2 V by an internal voltage divider. The inverting input at pin 5 is connected to the ramp voltage via R3 and feedback network P2, R5 to R11, R15, R16, C7, C10 and C11.

Power output stage (pin 7)

The power output stage is an amplifier with a quasi-complementary class-B output. The output is connected to pin 7.

The power stage includes SOAR and thermal protection.

= 1.23 × fo.

1997 Mar 27 5

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