Philips tda4686 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA4686

Video processor with automatic cut-off control

Preliminary speciﬁcation File under Integrated Circuits, IC02

May 1993

Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control TDA4686

FEATURES

• Intended for double line frequency application (100/120 Hz)

• Operates from an 8 V DC supply

• Black level clamping of the colour difference, luminance

and RGB input signals with coupling-capacitor DC level storage

• Two analog RGB inputs, selected either by fast switch signals or the I2C-bus; brightness and contrast control of these RGB inputs

• Saturation, contrast, brightness and white adjustment via I2C-bus

• Same RGB output black levels for Y/CD and RGB input signals

• Timing pulse generation from either a 2- or 3-level sandcastle pulse for clamping, vertical synchronization and cut-off timing pulses

• Automatic cut-off control or clamped output selectable via I2C-bus

• Automatic cut-off control with picture tube leakage current compensation

• Cut-off measurement pulses after end of the vertical blanking pulse or end of an extra vertical flyback pulse

• Increased RGB signal bandwidths

• Two switch-on delays to prevent discolouration before

steady-state operation

• Average beam current and peak drive limiting

• PAL/SECAM or NTSC matrix selection via I2C-bus

• Emitter-follower RGB output stages to drive the video

output stages

• I2C-bus controlled DC output e. g. for hue-adjust of NTSC (multistandard) decoders

• No delay of clamping pulse

• Large luminance, colour difference and RGB bandwidth

GENERAL DESCRIPTION

The TDA4686 is a monolithic, integrated circuit with a luminance and a colour difference interface for video processing in TV receivers. Its primary function is to process the luminance and colour difference signals from a colour decoder which is equipped e. g. with the

multistandard decoder TDA4655 or TDA9160 plus delayline TD4661 and the Picture Signal Improvement (PSI) IC TDA467X or from a Feature Module. The required input signals are:

• luminance and negative colour difference signals

• 2- or 3-level sandcastle pulse for internal timing pulse

generation

C-bus data and clock signals for microprocessor

• I control.

Two sets of analog RGB colour signals can also be inserted, e.g. one from a peritelevision connector and the other from an on-screen display generator. The TDA4686 has I2C-bus control of all parameters and functions with automatic cut-off control of the picture tube cathode currents. It provides RGB output signals for the video output stages. The TDA4686 is a simplified, pin compatible (except pin 18) version of the TDA4680. The module address via the I2C-bus can be used for both ICs; where a function is not included in the TDA4686 then the I2C-bus command is not executed. The differences with the TDA4680 are:

• no automatic white level control; the white levels are determined directly by the I2C-bus data

• RGB reference levels for automatic cut-off control are not adjustable via I2C-bus

• no clamping delay

• only contrast and brightness adjust for the RGB input

signals

• the measurement lines are triggered either by the trailing edge of the vertical component of the sandcastle pulse or by the trailing edge of an optional external vertical flyback pulse (on pin 18), according to which occurs first.

The TDA4685 is like TDA4686 but intended for normal line frequency application.

May 1993 2

Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control TDA4686

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V I

V V V V

V T

8(p-p) 6(p-p) 7(p-p) 14

o(p-p) amb

supply voltage (pin 5) 7.2 8.0 8.8 V supply current (pin 5) − 60 − mA luminance input (peak-to-peak value) − 0.45 − V

−(B−Y) input (peak-to-peak value) − 1.33 − V

−(R−Y) input (peak-to-peak value) − 1.05 − V

three-level sandcastle pulse

H +V − 2.5 − V H − 4.5 − V BK − 8.0 − V

two-level sandcastle pulse

H +V − 2.5 − V BK − 4.5 − V

RGB input signals at pins 2, 3, 4, 10, 11 and 12 (black-to-white

− 0.7 − V

value) RGB outputs at pins 24, 22 and 20 (peak-to-peak value) − 2.0 − V operating ambient temperature 0 − +70 °C

ORDERING INFORMATION

EXTENDED

TYPE NUMBER

PINS PIN POSITION MATERIAL CODE

PACKAGE

TDA4686 28 DIL plastic SOT117

TDA4686WP 28 PLCC plastic SOT261CG

Note

1. SOT117-1; 1996 November 25.

2. SOT261-2; 1996 November 25.

(1)

(2)

May 1993 3

Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control

leakage

and cut-off

current input

hue control voltage



6-BIT D/A

cut-off

control

CUT-OFF

CONVERTER

leakage

storage

COMPARATORS

peak drive

limiting

storage

PEAK DRIVE

average

beam

current

AND

LIMITING

AVERAGE

BEAM CURRENT

BCOF

D/A

3 x 6-BIT

CONVERTERS

RGB

outputs

242220

OUTPUT

ADJUST,

CUT-OFF

POINT

WHITE

ADJUST

ADJUST,

BLANKING 2,

BRIGHTNESS

MEASUREMENT B

STAGES

PULSES

SUPPLY

MED715

21 23 25

cut-off storage

= 8 V

TDA4686

DELAYS

SWITCH-ON

1ST AND 2ND

A45 to A40, A55 to A50, A65 to A60

AA5 to AA0

C-BUS

TRANSCEIVER

SDA

SCL

C-bus

TDA4686

A05 to A00, A15 to A10, A25 to A20, A35 to A30

BREN

VFB

sandcastle

TIMING

GENERATOR

(H)

H + V

PULSE

DETECTOR

SANDCASTLE

SC5

pulse

timing

BCOF

FSDIS2, FSON2,

2 x 8-BIT

CONTROL

pulses

FSDIS1, FSON1

NMEN

REGISTERS

FSW

D/A

4 x 6-BIT

CONVERTERS

101112

ADJUST

CONTRAST

handbook, full pagewidth

Fig.1 Block diagram.

BLANKING 1

FAST SIGNAL

SOURCE SWITCH,

NTSC

MATRIX

PAL/SECAM,

C-bus data and

control signals

ADJUST

SATURATION

−(R−Y)

−(B−Y)

1 2

FSW

May 1993 4

Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control TDA4686

PINNING

SYMBOL PIN DESCRIPTION

FSW R

1 fast switch 2 input 2 red input 2 3 green input 2 4 blue input 2 5 supply voltage

−(B−Y) 6 colour difference input −(B−Y)

−(R−Y) 7 colour difference input −(R−Y)

Y 8 luminance input GND 9 ground R

FSW

10 red input 1 11 green input 1 12 blue input 1

13 fast switch 1 input SC 14 sandcastle pulse input BCL 15 average beam current limiting input

alfpage

FSW

R G B V

−(B−Y)

−(R−Y)

GND

R G B

FSW

2 2 2 2

1 1 1 1

1 2 3 4 5 6 7

TDA4686

9 10 11 12 13 14

MED716

SCL

SDA

HUE

PDL

BCL

SYMBOL PIN DESCRIPTION

PDL

16 storage capacitor for peak drive

limiting

17 storage capacitor for leakage current

18 vertical ﬂyback pulse input CI 19 cut-off measurement input B

20 blue output

21 blue cut-off storage capacitor

22 green output

23 green cut-off storage capacitor

24 red output

25 red cut-off storage capacitor HUE 26 hue control output SDA 27 I

C-bus serial data input /

acknowledge output

SCL 28 I

−(B−Y)

−(R−Y)

GND

B2G2R2FSW2SCL 4

FSW

C-bus serial clock input

TDA4686WP

BCLCPDL

SDA 27

HUE 26

25 24 23 22 21 20 19

MED717

Fig.2 Pin configuration for DIL

package.

May 1993 5

Fig.3 Pin configuration for PLCC package.

Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control TDA4686

I2C-BUS CONTROL

The I2C-bus transmitter provides the data bytes to select and adjust the following functions and parameters:

• brightness adjust

• saturation adjust

• contrast adjust

• DC output e. g. for hue control

• RGB gain adjust

• peak drive limiting level adjust

• selects either 3-level or 2-level (5 V) sandcastle pulse

• enables cut-off control / enables output clamping

• selects either PAL/SECAM or NTSC matrix

• enables/disables synchronization of the execution of

I2C-bus commands with the vertical blanking interval

• enables Y-CD, RGB1 or RGB2 input.

handbook, full pagewidth

MSB LSB

I2C-BUS TRANSMITTER AND DATA TRANSFER

C-bus speciﬁcation

The I2C-bus is a bi-directional, two-wire, serial data bus for intercommunication between ICs in an equipment. The microcontroller transmits data to the I2C-bus receiver in the TDA4686 over the serial data line SDA (pin 27) synchronized by the serial clock line SCL (pin 28). Both lines are normally connected to a positive voltage supply through pull-up resistors. Data is transferred when the SCL line is LOW. When SCL is HIGH the serial data line SDA must be stable. A HIGH-to-LOW transition of the SDA line when SCL is HIGH is defined as a start bit. A LOW-to-HIGH transition of the SDA line when SCL is HIGH is defined as a stop bit. Each transmission must start with a start bit and end with a stop bit. The bus is busy after a start bit and is only free again after a stop bit has been transmitted.

00100

ACK0

handbook, full pagewidth

module address

R/W

MED710

Fig.4 The module address byte.

STOSAD

STOP

condition

MED697

START

condition

MADSTA

data byte

Fig.5 Data transmission without auto-increment (BREN = 0 or 1).

SAD

START

condition

MADSTA

data byte

data bytes

STO

STOP

condition

MED698

Fig.6 Data transmission with auto-increment (BREN = 0).

May 1993 6

Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control TDA4686

I2C-bus receiver

(microcontroller write mode) Each transmission to the I2C-bus receiver consists of at least three bytes following the start bit. Each byte is acknowledged by an acknowledge bit immediately following each byte. The first byte is the Module ADdress (MAD) byte, also called slave address byte. This includes the module address, 10001002 for the TDA4686. The TDA4686 is a slave receiver (R/W = 0), therefore the module address byte is 100010002 (88 Hex), see Fig.4. The length of a data transmission is unrestricted, but the module address and the correct sub-address must be transmitted before the data byte(s). The order of data transmission is shown in Fig.5 and Fig.6. Without auto-increment (BREN = 0 or 1) the Module ADdress (MAD) byte is followed by a Sub-ADdress (SAD) byte and one data byte only (Fig.5).

Auto-increment

The auto-increment format enables quick slave receiver initialization by one transmission, when the I

C-bus control bit BREN = 0 (see control register bits of Table 1). If BREN = 1 auto-increment is not possible. If the auto-increment format is selected, the MAD byte is followed by an SAD byte and by the data bytes of consecutive sub-addresses (Fig.6). All sub-addresses from 00 to 0F are automatically incremented, the sub-address counter wraps round from 0F to 00. Reserved sub-addresses 07, 08, 09, 0B, 0E and 0F are treated as legal but have no effect. Sub-addresses outside the range 00 and 0F are not acknowledged by the device. The sub-addresses are stored in the TDA4686 to address the following parameters and functions, see Table 1:

• brightness adjust

• saturation adjust

• contrast adjust

• hue control voltage

• RGB gain adjust

• peak drive limiting adjust

• control register functions.

The data bytes (D7-D0 of Table 1) provide the data of the parameters and functions for video processing.

Control register 1

NMEN (NTSC-Matrix ENable):

0 = PAL/SECAM matrix 1 = NTSC matrix.

BREN (Buffer Register ENable):

0 = new data is executed as soon as it is received

1 = data is stored in buffer registers and is transferred to the data registers during the next vertical blanking interval. The I2C-bus receiver does not accept any new data until this data is transferred into the data registers.

SC5 (SandCastle 5 V):

0 = 3-level sandcastle pulse 1 = 2-level (5 V) sandcastle pulse.

Control register 2

FSON2 - Fast Switch 2 ON FSDIS2 - Fast Switch 2 DISable FSON1 - Fast Switch 1 ON FSDIS1 - Fast Switch 1 DISable The RGB input signals are selected by FSON2 and FSON1 or FSW

and

FSW1:

• FSON2 has priority over FSON1;

• FSW2 has priority over FSW1;

• FSDIS1 and FSDIS2 disable

FSW1 and FSW2 (see Table 2).

BCOF - Black level Control OFf:

0 = automatic cut-off control enabled

1 = automatic cut-off control disabled; RGB outputs are clamped to fixed DC levels.

May 1993 7

When the supply voltage has dropped below approximately 6.0 V (usually occurs when the TV receiver is switched on or the supply voltage is interrupted) all data and function bits are set to 01

Hex

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