Philips tda4685 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA4685

Video processor with automatic
cut-off control

Preliminary specification
File under Integrated Circuits, IC02

May 1993

Philips Semiconductors Preliminary specification

Video processor with automatic cut-off
control

FEATURES

• Operates from an 8 V DC supply

• Black level clamping of the colour difference, luminance

and RGB input signals with coupling-capacitor DC level
storage

• Two analog RGB inputs, selected either by fast switch
signals or the I2C-bus; brightness and contrast control of
these RGB inputs

• Saturation, contrast, brightness and white adjustment
via I2C-bus

• Same RGB output black levels for Y/CD and RGB input
signals

• Timing pulse generation from either a 2- or 3-level
sandcastle pulse for clamping, vertical synchronization
and cut-off timing pulses

• Automatic cut-off control or clamped output selectable
via I2C-bus

• Automatic cut-off control with picture tube leakage
current compensation

• Cut-off measurement pulses after end of the vertical
blanking pulse or end of an extra vertical flyback pulse

• Two switch-on delays to prevent discolouration before
steady-state operation

• Average beam current and peak drive limiting

• PAL/SECAM or NTSC matrix selection via I2C-bus

• Emitter-follower RGB output stages to drive the video

output stages

• I2C-bus controlled DC output e. g. for hue-adjust of
NTSC (multistandard) decoders

GENERAL DESCRIPTION

The TDA4685 is a monolithic, integrated circuit with a
luminance and a colour difference interface for video
processing in TV receivers.

Its primary function is to process the luminance and colour
difference signals from a colour decoder which is equipped
e. g. with the multistandard decoder TDA4655 or TDA9160
plus delayline TDA4661 and the Picture Signal

TDA4685

Improvement (PSI) IC TDA467X or from a Feature
Module. The required input signals are:

• luminance and negative colour difference signals

• 2- or 3-level sandcastle pulse for internal timing pulse

generation

2

C-bus data and clock signals for microprocessor

• I
control.

Two sets of analog RGB colour signals can also be
inserted, e.g. one from a peritelevision connector and the
other from an on-screen display generator. The TDA4685
has I2C-bus control of all parameters and functions with
automatic cut-off control of the picture tube cathode
currents. It provides RGB output signals for the video
output stages.

The TDA4685 is a simplified, pin compatible (except pin

18) version of the TDA4680. The module address via the

I2C-bus can be used for both ICs; where a function is not
included in the TDA4685 then the I2C-bus command is not
executed. The differences with the TDA4680 are:

• no automatic white level control; the white levels are
determined directly by the I2C-bus data

• RGB reference levels for automatic cut-off control are
not adjustable via I2C-bus

• clamping delay is fixed

• only contrast and brightness adjust for the RGB input

signals

• the measurement lines are triggered either by the
trailing edge of the vertical component of the sandcastle
pulse or by the trailing edge of an optional external
vertical flyback pulse (on pin 18), according to which
occurs first.

The TDA4686 is like TDA4685 but intended for double line
frequency application.

May 1993 2

Philips Semiconductors Preliminary specification

Video processor with automatic cut-off

TDA4685

control

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V
I

P

V
V
V
V

V
V
T

P

8(p-p)
6(p-p)
7(p-p)
14

i
o(p-p)
amb

supply voltage (pin 5) 7.2 8.0 8.8 V
supply current (pin 5) − 60 − mA
luminance input (peak-to-peak value) − 0.45 − V

−(B−Y) input (peak-to-peak value) − 1.33 − V

−(R−Y) input (peak-to-peak value) − 1.05 − V

three-level sandcastle pulse

H+V − 2.5 − V
H − 4.5 − V
BK − 8.0 − V

two-level sandcastle pulse

H + V − 2.5 − V

BK − 4.5 − V
RGB input signals at pins 2, 3, 4, 10, 11 and 12 (black-to-white value) − 0.7 − V
RGB outputs at pins 24, 22 and 20 (peak-to-peak value) − 2.0 − V
operating ambient temperature 0 − +70 °C

ORDERING INFORMATION

PACKAGE

EXTENDED

TYPE NUMBER

PINS

PIN

POSITION

MATERIAL CODE

TDA4685 28 DIL plastic SOT117

Note

1. SOT117-1; 1996 November 25.

(1)

May 1993 3

Philips Semiconductors Preliminary specification

Video processor with automatic cut-off
control

leakage

and cut-off

current input

hue control voltage

26



6-BIT D/A

C

R

cut-off

control

19

CUT-OFF

CONVERTER

leakage

storage

17

COMPARATORS

peak drive

limiting

storage

16

PEAK DRIVE

average

beam

current

15

AND

LIMITING

AVERAGE

BEAM CURRENT

D/A

3 x 6-BIT

CONVERTERS

BCOF

RGB

outputs

O

O

O

B

R

G

242220

OUTPUT

ADJUST,

CUT-OFF

B

R

G

POINT

WHITE

ADJUST

B

R

G

ADJUST,

BLANKING 2,

BRIGHTNESS

MEASUREMENT
B

R

G

STAGES

PULSES

SUPPLY

MED708

21 23 25

9

5

TDA4685

cut-off storage

R

GB

= 8 V

P

V

DELAYS

SWITCH-ON

1ST AND 2ND

A45 to A40, A55 to A50, A65 to A60

AA5 to AA0

C-BUS

2

I

TRANSCEIVER

27

28

SDA

SCL

C-bus

2

I

TDA4685

A05 to A00, A15 to A10, A25 to A20, A35 to A30

BREN

14

18

VFB

sandcastle

TIMING

GENERATOR

BK

(H)

H + V

PULSE

DETECTOR

SANDCASTLE

SC5

pulse

timing

BCOF

FSDIS2, FSON2,

2 x 8-BIT

CONTROL

pulses

FSDIS1, FSON1

NMEN

REGISTERS

13

1

FSW

D/A

4 x 6-BIT

CONVERTERS

101112

1

1

R

G

ADJUST

R

CONTRAST

B

G

handbook, full pagewidth

Fig.1 Block diagram.

BLANKING 1

FAST SIGNAL

SOURCE SWITCH,

B

R

G

NTSC

MATRIX

PAL/SECAM,

C-bus data and

2

control signals

I

ADJUST

SATURATION

8

7

6

1

B

Y

−(R−Y)

−(B−Y)

1
2

FSW

2

3

4

2

2

2

B

R

G

May 1993 4

Philips Semiconductors Preliminary specification

Video processor with automatic cut-off
control

PINNING

SYMBOL PIN DESCRIPTION

FSW

2

R

2

G

2

B

2

V

P

−(B−Y) 6 colour difference input −(B−Y)

−(R−Y) 7 colour difference input −(R−Y)

Y 8 luminance input
GND 9 ground
R

1

G

1

B

1

FSW

1

SC 14 sandcastle pulse input
BCL 15 average beam current limiting input
C

PDL

C

L

V

FB

CI 19 cut-off measurement input
B

O

C

B

G

O

C

G

R

O

C

R

HUE 26 hue control output
SDA 27 I
SCL 28 I

1 fast switch 2 input
2 red input 2
3 green input 2
4 blue input 2
5 supply voltage

10 red input 1
11 green input 1
12 blue input 1
13 fast switch 1 input

16 storage capacitor for peak drive limiting
17 storage capacitor for leakage current
18 vertical flyback pulse input

20 blue output
21 blue cut-off storage capacitor
22 green output
23 green cut-off storage capacitor
24 red output
25 red cut-off storage capacitor

2

C-bus serial data input / acknowledge output

2

C-bus serial clock input

lfpage

FSW

1

2

R

2

2

G

3

2

B

4

2

V

5

P

−(B−Y)

6

−(R−Y)

7

Y

8

GND

9

R

10

1

G

11

1

B

12

1

FSW

13

1

SC

14

Fig.2 Pin configuration.

TDA4685

TDA4685

MED709

SCL

28

SDA

27

HUE

26

C

25

R

R

24

O

C

23

G

G

22

O

C

21

B

B

20

O

CI

19

V

18

FB

C

17

L

C

16

PDL

BCL

15

May 1993 5

Philips Semiconductors Preliminary specification

Video processor with automatic cut-off
control

I2C-BUS CONTROL

The I2C-bus transmitter provides the
data bytes to select and adjust the
following functions and parameters:

• brightness adjust

• saturation adjust

• contrast adjust

• DC output e. g. for hue control

• RGB gain adjust

• peak drive limiting level adjust

• selects either 3-level or 2-level

(5 V) sandcastle pulse

• enables cut-off control / enables
output clamping

• selects either PAL/SECAM or
NTSC matrix

• enables/disables synchronization
of the execution of I2C-bus
commands with the vertical
blanking interval

• enables Y-CD, RGB1 or RGB2
input.

I2C-BUS TRANSMITTER AND
DATA TRANSFER

2

I

C-bus specification

The I2C-bus is a bi-directional,
two-wire, serial data bus for
intercommunication between ICs in
an equipment. The microcontroller
transmits data to the I2C-bus receiver
in the TDA4685 over the serial data
line SDA (pin 27) synchronized by the
serial clock line SCL (pin 28).
Both lines are normally connected to
a positive voltage supply through
pull-up resistors. Data is transferred
when the SCL line is LOW. When
SCL is HIGH the serial data line SDA
must be stable. A HIGH-to-LOW
transition of the SDA line when SCL is
HIGH is defined as a start bit.
A LOW-to-HIGH transition of the SDA
line when SCL is HIGH is defined as
a stop bit. Each transmission must
start with a start bit and end with a
stop bit. The bus is busy after a start
bit and is only free again after a stop
bit has been transmitted.

TDA4685

2

C-bus receiver

I

(microcontroller write mode)
Each transmission to the I2C-bus
receiver consists of at least three
bytes following the start bit. Each byte
is acknowledged by an acknowledge
bit immediately following each byte.
The first byte is the Module ADdress
(MAD) byte, also called slave address
byte. This includes the module
address, 10001002 for the TDA4685.
The TDA4685 is a slave receiver
(R/W = 0), therefore the module
address byte is 100010002(88 Hex),
see Fig.3.
The length of a data transmission is
unrestricted, but the module address
and the correct sub-address must be
transmitted before the data byte(s).
The order of data transmission is
shown in Fig.4 and Fig.5. Without
auto-increment (BREN = 0 or 1) the
Module ADdress (MAD) byte is
followed by a Sub-ADdress (SAD)
byte and one data byte only (Fig.4).

May 1993 6

Philips Semiconductors Preliminary specification

Video processor with automatic cut-off
control

handbook, full pagewidth

MSB LSB

01

module address

Fig.3 The module address byte.

TDA4685

00100

ACK0

R/W

MED710

handbook, full pagewidth

handbook, full pagewidth

STOSAD

STOP

condition

MED697

START

condition

MADSTA

data byte

Fig.4 Data transmission without auto-increment (BREN = 0 or 1).

SAD

START

condition

MADSTA

data byte

data bytes

STO

STOP

condition

MED698

May 1993 7

Fig.5 Data transmission with auto-increment (BREN = 0).