INTEGRATED CIRCUITS
PCF8593
Low power clock/calendar
Product specification |
1997 Mar 25 |
Supersedes data of July 1994
File under Integrated Circuits, IC12
Philips Semiconductors |
Product specification |
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Low power clock/calendar |
PCF8593 |
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CONTENTS
1FEATURES
2GENERAL DESCRIPTION
3QUICK REFERENCE DATA
4ORDERING INFORMATION
5BLOCK DIAGRAM
6PINNING
7FUNCTIONAL DESCRIPTION
7.1Counter function modes
7.2Alarm function modes
7.3Control/status register
7.4Counter registers
7.5Alarm control register
7.6Alarm registers
7.7Timer
7.8Event counter mode
7.9Interrupt output
7.10Oscillator and divider
7.10.1Designing
7.11Initialization (see Fig.12)
8 |
CHARACTERISTICS OF THE I2C-BUS |
8.1Bit transfer
8.2Start and stop conditions
8.3System configuration
8.4Acknowledge
9 |
I2C-BUS PROTOCOL |
9.1Addressing
9.2Clock/calendar READ/WRITE cycles
10LIMITING VALUES
11HANDLING
12DC CHARACTERISTICS
13AC CHARACTERISTICS
14APPLICATION INFORMATION
14.1Quartz frequency adjustment
14.1.1Method 1: Fixed OSCI capacitor
14.1.2Method 2: OSCI Trimmer
14.1.3Method 3: direct output
15PACKAGE OUTLINES
16SOLDERING
16.1Introduction
16.2DIP
16.2.1Soldering by dipping or by wave
16.2.2Repairing soldered joints
16.3SO
16.3.1Reflow soldering
16.3.2Wave soldering
16.3.3Repairing soldered joints
17DEFINITIONS
18LIFE SUPPORT APPLICATIONS
19PURCHASE OF PHILIPS I2C COMPONENTS
1997 Mar 25 |
2 |
Philips Semiconductors |
Product specification |
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Low power clock/calendar |
PCF8593 |
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1 FEATURES
∙I2C-bus interface operating supply voltage: 2.5 to 6.0 V
∙Clock operating supply voltage (Tamb = 0 to +70 °C): 1.0 to 6.0 V
∙8 bytes scratchpad RAM (when alarm not used)
∙Data retention voltage: 1.0 to 6.0 V
∙External RESET input resets I2C interface (only)
∙Operating current (fscl = 0 Hz, 32 kHz time base, VDD = 2.0 V): typ. 1 μA
∙Clock function with four year calendar
∙Universal timer with alarm and overflow indication
∙24 or 12 hour format
∙32.768 kHz or 50 Hz time base
∙Serial input/output bus (I2C-bus)
∙Automatic word address incrementing
∙Programmable alarm, timer and interrupt function
∙Space-saving SO8 package available
∙Slave address:
–READ A3
–WRITE A2.
3 QUICK REFERENCE DATA
2 GENERAL DESCRIPTION
The PCF8593 is a CMOS clock/calendar circuit, optimized for low power consumption. Addresses and data are transferred serially via the two-line bidirectional I2C-bus. The built-in word address register is incremented automatically after each written or read data byte.
The built-in 32.768 kHz oscillator circuit and the first 8 bytes of RAM are used for the clock/calendar and counter functions. The next 8 bytes may be programmed as alarm registers or used as free RAM space.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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V |
supply voltage operating mode |
I2C-bus active |
2.5 |
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6.0 |
V |
DD |
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I2C-bus inactive |
1.0 |
− |
6.0 |
V |
IDD |
supply current operating mode |
fscl = 100 kHz |
− |
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200 |
μA |
IDD |
supply current clock mode |
fscl = 0 Hz; VDD = 5 V |
− |
4.0 |
15.0 |
μA |
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fscl = 0 Hz; VDD = 2 V |
− |
1.0 |
8.0 |
μA |
Tamb |
operating ambient temperature |
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−40 |
− |
+85 |
°C |
Tstg |
storage temperature |
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−65 |
− |
+150 |
°C |
4 ORDERING INFORMATION
TYPE |
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PACKAGE |
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NUMBER |
NAME |
DESCRIPTION |
VERSION |
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PCF8593P |
DIP8 |
plastic dual in-line package; 8 leads (300 mil) |
SOT97-1 |
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PCF8593T |
SO8 |
plastic small outline package; 8 leads; body width 3.9 mm |
SOT96-1 |
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1997 Mar 25 |
3 |
Philips Semiconductors |
Product specification |
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Low power clock/calendar |
PCF8593 |
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5 BLOCK DIAGRAM
handbook, full pagewidth |
VDD |
1 |
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8 |
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DIVIDER |
100 Hz |
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OSCI |
OSCILLATOR |
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2 |
1 : 256 |
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32.768 kHz |
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100 : 128 |
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OSCO |
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control/status |
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7 |
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00 |
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INT |
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hundredths of a second |
01 |
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seconds |
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3 |
RESET |
CONTROL |
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minutes |
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RESET |
LOGIC |
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hours |
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year/date |
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weekdays/months |
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PCF8593 |
timer |
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07 |
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6 |
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alarm control |
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08 |
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SCL |
I 2 C-BUS |
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5 |
INTERFACE |
ADDRESS |
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SDA |
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REGISTER |
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alarm registers |
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or RAM |
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0F |
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MBD808 |
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VSS |
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Fig.1 Block diagram.
6 PINNING |
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PIN |
DESCRIPTION |
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OSCI |
1 |
oscillator input, 50 Hz or event-pulse |
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input |
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OSCO |
2 |
oscillator output |
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OSCI |
1 |
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8 |
VDD |
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3 |
reset input (active LOW) |
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RESET |
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OSCO |
2 |
PCF8593P |
7 |
INT |
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VSS |
4 |
negative supply |
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PCF8593T |
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RESET |
3 |
6 |
SCL |
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SDA |
5 |
serial data input/output |
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VSS |
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SDA |
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4 |
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5 |
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SCL |
6 |
serial clock input |
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MBD809 |
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INT |
7 |
open drain interrupt output |
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(active LOW) |
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Fig.2 |
Pin configuration. |
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VDD |
8 |
positive supply |
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1997 Mar 25 |
4 |
Philips Semiconductors |
Product specification |
|
|
Low power clock/calendar |
PCF8593 |
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7 FUNCTIONAL DESCRIPTION
The PCF8593 contains sixteen 8-bit registers with an 8-bit auto-incrementing address register, an on-chip
32.768 kHz oscillator circuit, a frequency divider and a serial two-line bidirectional I2C-bus interface.
The first 8 registers (memory addresses 00 to 07) are designed as addressable 8-bit parallel registers. The first register (memory address 00) is used as a control/status register. The memory addresses 01 to 07 are used as counters for the clock function. The memory addresses 08 to 0F may be programmed as alarm registers or used as free RAM locations.
7.1Counter function modes
When the control/status register is programmed, a 32.768 kHz clock mode, a 50 Hz clock mode or an event-counter mode can be selected.
In the clock modes the hundredths of a second, seconds, minutes, hours, date, month (four year calendar) and weekday are stored in a BCD format. The timer register stores up to 99 days. The event counter mode is used to count pulses applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6 digits of data.
When one of the counters is read (memory locations 01 to 07), the contents of all counters are strobed into
capture latches at the beginning of a read cycle. Therefore, faulty reading of the count during a carry condition is prevented.
When a counter is written, other counters are not affected.
7.2Alarm function modes
By setting the alarm enable bit of the control/status register the alarm control register (address 08) is activated.
By setting the alarm control register a dated alarm, a daily alarm, a weekday alarm or a timer alarm may be programmed. In the clock modes, the timer register (address 07) may be programmed to count hundredths of
a second, seconds, minutes, hours or days. Days are counted when an alarm is not programmed.
Whenever an alarm event occurs the alarm flag of the control/status register is set. A timer alarm event will set the alarm flag and an overflow condition of the timer will set the timer flag. The open-drain interrupt output is switched on (active LOW) when the alarm or timer flag is set (enabled). The flags remain set until directly reset by a write operation.
When the alarm is disabled (Bit 2 of control/status register = 0) the alarm registers at addresses 08 to 0F may be used as free RAM.
7.3Control/status register
The control/status register is defined as the memory location 00 with free access for reading and writing via the I2C-bus. All functions and options are controlled by the contents of the control/status register (see Fig.3).
7.4Counter registers
In the clock modes 24 h or 12 h format can be selected by setting the most significant bit of the hours counter register. The format of the hours counter is shown in Fig.5.
The year and date are packed into memory location 05 (see Fig 6). The weekdays and months are packed into memory location 06 (see Fig.7). When reading these memory locations the year and weekdays are masked out when the mask flag of the control/status register is set. This allows the user to read the date and month count directly.
In the event-counter mode events are stored in BCD format. D5 is the most significant and D0 the least significant digit. The divider is by-passed.
In the different modes the counter registers are programmed and arranged as shown in Fig.4. Counter cycles are listed in Table 1.
1997 Mar 25 |
5 |
Philips Semiconductors |
Product specification |
|
|
Low power clock/calendar |
PCF8593 |
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handbook, full pagewidth |
MSB |
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LSB |
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7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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memory location 00
timer flag (50% duty factor seconds flag if alarm enable bit is 0)
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alarm flag (50% duty factor |
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minutes flag if alarm |
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enable bit is 0) |
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alarm enable bit: |
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0 |
alarm disabled: flags toggle |
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alarm control register disabled |
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(memory locations 08 to 0F |
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can be treated as RAM) |
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1 |
enable Alarm Control register |
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(memory location 08 is the |
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Alarm Control register) |
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mask flag: |
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0 |
read locations 05 to 06 |
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unmasked |
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1 |
read date and month count |
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directly |
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function mode : |
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00 clock mode 32.768 kHz |
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01 clock mode 50 Hz |
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10 event-counter mode |
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11 |
test modes |
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hold last count flag : |
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0 |
count |
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1 |
store and hold last count in |
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capture latches |
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stop counting flag : |
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MBD810 |
0 |
count pulses |
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1 |
stop counting, reset divider |
Fig.3 Control/status register.
1997 Mar 25 |
6 |
Philips Semiconductors |
Product specification |
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Low power clock/calendar |
PCF8593 |
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control/status |
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control/status |
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00 |
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hundredths of a second |
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D1 |
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D0 |
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1/10 s |
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1/100 s |
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01 |
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seconds |
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D3 |
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D2 |
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10 s |
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1 s |
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02 |
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minutes |
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D5 |
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D4 |
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10 min |
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1 min |
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03 |
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hours |
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free |
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10 h |
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1 h |
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04 |
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year/date |
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free |
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10 day |
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1 day |
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05 |
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weekday/month |
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free |
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10 month |
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1 month |
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06 |
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timer |
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T1 |
timer |
T0 |
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10 day |
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1 day |
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07 |
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alarm control |
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alarm control |
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08 |
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hundredths of a second |
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alarm |
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alarm |
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1/10 s |
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1/100 s |
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D1 |
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D0 |
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09 |
alarm seconds |
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D3 |
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D2 |
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0A |
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alarm minutes |
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D5 |
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D4 |
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0B |
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alarm hours |
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free |
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0C |
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alarm date |
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free |
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0D |
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alarm month |
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free |
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0E |
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alarm timer |
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alarm timer |
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0F |
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CLOCK MODES |
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EVENT COUNTER |
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MBD811 |
Fig.4 Register arrangement.
1997 Mar 25 |
7 |
Philips Semiconductors |
Product specification |
|
|
Low power clock/calendar |
PCF8593 |
|
|
handbook, full pagewidth |
MSB |
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LSB |
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7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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memory location 04 (hours counter) |
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unit hours BCD |
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ten hours (0 to 12 binary) |
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AM/PM flag: |
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0 |
AM |
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1 |
PM |
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format: |
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MBD812 |
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remains unchanged |
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1 |
12 h format, AM/PM flag |
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will be updated |
Fig.5 Format of the hours counter.
handbook, full pagewidth |
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memory location 05 (year/date)
unit hours BCD
ten days (0 to 3 binary)
year (0 to 3 binary, read as 0 if the mask flag is set)
MBD813
Fig.6 Format of the year/date counter.
handbook, full pagewidth |
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MBD814
memory location 06 (weekdays/months)
unit months BCD
ten months
weekdays (0 to 6 binary, read as 0 if the mask flag is set)
Fig.7 Format of the weekdays/months counter.
1997 Mar 25 |
8 |
Philips Semiconductors |
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Product specification |
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Low power clock/calendar |
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PCF8593 |
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Table 1 Cycle length of the time counters, clock modes. |
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UNIT |
COUNTING CYCLE |
CARRY TO NEXT UNIT |
CONTENTS OF THE |
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MONTH COUNTER |
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Hundredths of a second |
00 to 99 |
99 to 00 |
− |
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Seconds |
00 to 59 |
59 to 00 |
− |
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Minutes |
00 to 59 |
59 to 00 |
− |
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Hours (24 h) |
00 to 23 |
23 to 00 |
− |
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Hours (12 h) |
12 AM |
− |
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01 AM to 11 AM |
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12 PM |
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01 PM to 11 PM |
11 PM to 12 AM |
− |
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Date |
01 to 31 |
31 to 01 |
1, 3, 5, 7, 8, 10 and 12 |
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01 to 30 |
30 to 01 |
4, 6, 9 and 11 |
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01 to 29 |
29 to 01 |
2, year = 0 |
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01 to 28 |
28 to 01 |
2, year = 1, 2 and 3 |
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Months |
01 to 12 |
12 to 01 |
− |
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Year |
0 to 3 |
− |
− |
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Weekdays |
0 to 6 |
6 to 0 |
− |
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Timer |
00 to 99 |
no carry |
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7.5Alarm control register
When the alarm enable bit of the control/status register is set (address 00, bit 2) the alarm control register (address 08) is activated. All alarm, timer, and interrupt output functions are controlled by the contents of the alarm control register (see Fig.8).
7.6Alarm registers
All alarm registers are allocated with a constant address offset of hexadecimal 08 to the corresponding counter registers (see Fig.4,Register arrangement).
An alarm signal is generated when the contents of the alarm registers matches bit-by-bit the contents of the involved counter registers. The year and weekday bits are ignored in a dated alarm. A daily alarm ignores the month and date bits. When a weekday alarm is selected, the contents of the alarm weekday/month register will select the weekdays on which an alarm is activated (see Fig.9).
Remark: in the 12 h mode, bits 6 and 7 of the alarm hours register must be the same as the hours counter.
1997 Mar 25 |
9 |