Philips pcf8593 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

PCF8593

Low power clock calendar

Product speciﬁcation Supersedes data of June 1994 File under Integrated Circuits, IC12

Philips Semiconductors

July 1994

Philips Semiconductors Product speciﬁcation

Low power clock calendar PCF8593

FEATURES

• I2C-bus interface operating supply voltage: 2.5 to 6.0 V

• Clock operating supply voltage (T

1.0 to 6.0 V

• Data retention voltage: 1.0 to 6.0 V

• External RESET input pin

• Operating current (f

= 0 Hz, 32 kHz time base,

scl

VDD= 2.0 V): typ. 1 µA

• Clock function with four year calendar

• Universal timer with alarm and overflow indication

• 24 or 12 hour format

• 32.768 kHz or 50 Hz time base

• Serial input/output bus (I2C-bus)

• Automatic word address incrementing

• Programmable alarm, timer and interrupt function

• Space-saving SO8 package

• Slave address:

– READ A3H – WRITE A2H.

= 0 to +70 °C):

amb

GENERAL DESCRIPTION

The PCF8593 is a CMOS Real-time clock/calendar optimized for low power consumption. Addresses and data are transferred serially via a two-line bidirectional bus (I2C-bus). The built-in word address register is incremented automatically after each written or read data byte. The built-in 32.768 kHz oscillator circuit and the first 8 registers are used for the clock/calendar and counter functions. The next 8 registers may be programmed as alarm registers or used as free RAM space.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

amb

stg

supply voltage operating mode I2C-bus active 2.5 6.0 V

C-bus inactive 1.0 6.0 V

I supply current operating mode f supply current clock mode f

= 100 kHz − 200 µA

scl

= 0 Hz; VDD= 5 V 4.0 15.0 µA

scl

= 0 Hz; VDD= 2 V 1.0 8.0 µA

scl

operating ambient temperature −40 +85 °C storage temperature −65 +150 °C

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

PINS PIN POSITION MATERIAL CODE

PCF8593P 8 DIL plastic SOT97-1 PCF8593T 8 SO8 plastic SOT96-1

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Philips Semiconductors Product speciﬁcation

Low power clock calendar PCF8593

BLOCK DIAGRAM

handbook, full pagewidth

OSCI

OSCO

INT

RESET

SCL

SDA

1 2 7

6 5

OSCILLATOR

32.768 kHz

RESET

I C-BUS

INTERFACE

DIVIDER

1 : 256

100 : 128

CONTROL

LOGIC

100 Hz

PCF8593

ADDRESS

Fig.1 Block diagram.

control/status

hundredths of a second

seconds

minutes

hours

year/date

weekdays/months

timer

alarm control

alarm registers

or RAM

00 01

07 08

MBD808

PINNING

SYMBOL PIN DESCRIPTION

OSCI 1 oscillator input, 50 Hz or event-pulse input OSCO 2 oscillator output RESET 3 reset input (active LOW) V

4 negative supply SDA 5 serial data input/output SCL 6 serial clock input INT 7 open drain interrupt output (active LOW) V

8 positive supply

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OSCI

OSCO

RESET

3 4

PCF8593P PCF8593T

MBD809

Fig.2 Pin configuration.

INT SCL

SDA

Philips Semiconductors Product speciﬁcation

Low power clock calendar PCF8593

FUNCTIONAL DESCRIPTION

The PCF8593 contains sixteen 8-bit registers with an 8-bit auto-incrementing address register, an on-chip

32.768 kHz oscillator circuit, a frequency divider and a serial two-line bidirectional I2C-bus interface.

The first 8 registers (memory addresses 00 to 07) are designed as addressable 8-bit parallel registers. The first register (memory address 00) is used as a control/status register. The memory addresses 01 to 07 are used as counters for the clock function. The memory addresses 08 to 0F may be programmed as alarm registers or used as free RAM locations.

Counter function modes

When the control/status register is programmed, a

32.768 kHz clock mode, a 50 Hz clock mode or an event-counter mode can be selected.

In the clock modes the hundredths of a second, seconds, minutes, hours, date, month (four year calendar) and week day are stored in a BCD format. The timer register stores up to 99 days. The event counter mode is used to count pulses applied to the oscillator input (OSCO left open-circuit). The event counter stores up to 6 digits of data.

(address 07) may be programmed to count hundredths of a second, seconds, minutes, hours or days. Days are counted when an alarm is not programmed.

Whenever an alarm event occurs the alarm flag of the control/status register is set. A timer alarm event will set the alarm flag and an overflow condition of the timer will set the timer flag. The open-drain interrupt output is switched on (active LOW) when the alarm or timer flag is set (enabled). The flags remain set until directly reset by a write operation.

When a timer function without any function is programmed the remaining alarm registers (addresses 09 to 0F) may be used as free RAM space.

Control/status register

The control/status register is defined as the memory location 00 with free access for reading and writing via the

C-bus. All functions and options are controlled by the

I contents of the control/status register (see Fig.3).

Counter registers

In the clock modes 24 h or 12 h format can be selected by setting the most significant bit of the hours counter register. The format of the hours counter is shown in Fig.5.

When one of the counters is read (memory locations 01 to 07), the contents of all counters are strobed into capture latches at the beginning of a read cycle. Therefore, faulty reading of the count during a carry condition is prevented.

When a counter is written, other counters are not affected.

Alarm function modes

By setting the alarm enable bit of the control/status register the alarm control register (address 08) is activated.

By setting the alarm control register a dated alarm, a daily alarm, a week day alarm or a timer alarm may be programmed. In the clock modes, the timer register

The year and date are packed into memory location 05 (see Fig 6). The weekdays and months are packed into memory location 06 (see Fig.7). When reading these memory locations the year and weekdays are masked out when the mask flag of the control/status register is set. This allows the user to read the date and month count directly.

In the event-counter mode events are stored in BCD format. D5 is the most significant and D0 the least significant digit. The divider is by-passed.

In the different modes the counter registers are programmed and arranged as shown in Fig.4. Counter cycles are listed in Table 1.

July 1994 4

Philips Semiconductors Product speciﬁcation

Low power clock calendar PCF8593

handbook, full pagewidth

MSB LSB

76543210

MBD810

memory location 00

timer flag (50% duty factor seconds flag if alarm enable bit is 0)

alarm flag (50% duty factor minutes flag if alarm enable bit is 0)

alarm enable bit:

0 alarm disabled: flags toggle alarm control register disabled (memory locations 08 to 0F can be treated as RAM) 1 enable Alarm Control register (memory location 08 is the Alarm Control register)

mask flag:

0 read locations 05 to 06 unmasked 1 read date and month count directly

function mode :

00 clock mode 32.768 kHz 01 clock mode 50 Hz 10 event-counter mode 11 test modes

hold last count flag :

0 count 1 store and hold last count in capture latches

stop counting flag :

0 count pulses 1 stop counting, reset divider

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Fig.3 Control/status register.

Philips Semiconductors Product speciﬁcation

Low power clock calendar PCF8593

handbook, full pagewidth

control/status

hundredths of a second

1/10 s

10 s

10 min

10 h

10 day

weekday/month

10 month

10 day

alarm control

hundredths of a second 1/10 s 1/100 s

alarm seconds

alarm minutes

alarm hours

alarm month

alarm timer

1/100 s

seconds

1 s

minutes

1 min

hours

1 h

year/date

1 day

1 month

timer

1 day

alarm date

control/status

alarm control

alarm alarm

D1 D3

alarm timer

free

timer

free free

free

D0 D2

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CLOCK MODES EVENT COUNTER

Fig.4 Register arrangement.

MBD811

Philips Semiconductors Product speciﬁcation

Low power clock calendar PCF8593

handbook, full pagewidth

MSB LSB

76543210

MBD812

Fig.5 Format of the hours counter.

MSB LSB

76543210

MBD813

memory location 04 (hours counter)

unit hours BCD ten hours (0 to 12 binary) AM/PM flag:

0 AM 1 PM

format: 0 24 h format, AM/PM flag remains unchanged 1 12 h format, AM/PM flag will be updated

memory location 05 (year/date)

unit hours BCD ten days (0 to 3 binary)

year (0 to 3 binary, read as 0 if the mask flag is set)

Fig.6 Format of the year/date counter.

handbook, full pagewidth

MSB LSB

76543210

MBD814

Fig.7 Format of the weekdays/months counter.

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memory location 06 (weekdays/months)

unit months BCD ten months weekdays (0 to 6 binary, read as 0 if

the mask flag is set)

Philips Semiconductors Product speciﬁcation

Low power clock calendar PCF8593

Table 1 Cycle length of the time counters, clock modes.

UNIT COUNTING CYCLE CARRY TO NEXT UNIT

Hundredths of a second 00 to 99 99 to 00 − Seconds 00 to 59 59 to 00 − Minutes 00 to 59 59 to 00 − Hours (24 h) 00 to 23 23 to 00 − Hours (12 h) 12 AM −−

01 AM to 11 AM −− 12 PM −− 01 PM to 11 PM 11 PM to 12 AM −

Date 01 to 31 31 to 01 1, 3, 5, 7, 8, 10 and 12

01 to 30 30 to 01 4, 6, 9 and 11 01 to 29 29 to 01 2, year = 0

01 to 28 28 to 01 2, year = 1, 2 and 3 Months 01 to 12 12 to 01 − Year 0 to 3 −− Weekdays 0 to 6 6 to 0 − Timer 00 to 99 no carry −

Alarm control register

When the alarm enable bit of the control/status register is set (address 00, bit 2) the alarm control register (address 08) is activated. All alarm, timer, and interrupt output functions are controlled by the contents of the alarm control register (see Fig.8).

An alarm signal is generated when the contents of the alarm registers matches bit-by-bit the contents of the involved counter registers. The year and weekday bits are ignored in a dated alarm. A daily alarm ignores the month and date bits. When a weekday alarm is selected, the contents of the alarm weekday/month register will select the weekdays on which an alarm is activated (see Fig.9).

CONTENTS OF THE

MONTH COUNTER

Alarm registers

All alarm registers are allocated with a constant address offset of hexadecimal 08 to the corresponding counter registers (see Fig.4; Register arrangement).

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Remark: in the 12 h mode, bits 6 and 7 of the alarm hours register must be the same as the hours counter.

Philips Semiconductors Product speciﬁcation

Low power clock calendar PCF8593

handbook, full pagewidth

MSB LSB

76543210

MBD815

memory location 08

timer function :

000 no timer 001 hundredths of a second 010 seconds 011 minutes 100 hours 101 days 110 not used 111 test mode, all counters in parallel

timer interrupt enable :

0 timer flag, no interrupt 1 timer flag, interrupt

clock alarm function :

00 no clock alarm 01 daily alarm 10 weekday alarm 11dated alarm

timer alarm enable :

0 no timer alarm 1 timer alarm

alarm interrupt enable :

(valid only when 'alarm enable' in control/status register is set

Fig.8 Alarm control register; clock mode.

July 1994 9

0 alarm flag, no interrupt 1 alarm flag, interrupt

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