Philips PCF8548U-2-F1 Datasheet

DATA SH EET

Product specification
Supersedes data of 1999 Mar 22
File under Integrated Circuits, IC12

1999 Aug 16

INTEGRATED CIRCUITS

PCF8548

65 × 102 pixels matrix LCD driver

1999 Aug 16 2

Philips Semiconductors Product specification

65 × 102 pixels matrix LCD driver PCF8548

CONTENTS

1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION

3.1 Packages
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 PIN FUNCTIONS

7.1 R0 to R64: row driver outputs

7.2 C0 to C101: column driver outputs

7.3 V

SS1

and V

SS2

: negative power supply rails

7.4 V

DD1

to V

DD3

: positive power supply rails

7.5 V

LCDIN

: LCD power supply

7.6 V

LCDOUT

: LCD power supply

7.7 V

LCDSENSE

: voltage multiplier regulation input

(V

LCD

)

7.8 T1 to T12: test pads

7.9 SDAIN and SDAOUT: I2C-bus data lines

7.10 SCL: I2C-bus clock signal

7.11 SA0: slave address

7.12 OSC: oscillator

7.13 RES: reset
8 BLOCK DIAGRAM FUNCTIONS

8.1 Oscillator

8.2 I2C-bus interface

8.3 Display control logic

8.4 Display Data RAM (DDRAM)

8.5 Timing generator

8.6 LCD row and column drivers
9 INITIALIZATION
10 ADDRESSING

10.1 Display data RAM structure

10.2 RAM access
11 I2C-BUS INTERFACE

11.1 Characteristics of the I2C-bus

11.1.1 Bit transfer

11.1.2 START and STOP conditions

11.1.3 System configuration

11.1.4 Acknowledge

11.2 I2C-bus protocol

12 INSTRUCTIONS

12.1 External reset (RES)

12.2 Function set

12.2.1 Power-Down (PD)

12.2.2 V

12.2.3 H

12.2.4 MX

12.2.5 MY

12.3 Display control

12.3.1 D and E

12.4 Display configuration

12.4.1 TRS

12.4.2 BRS

12.5 Set Y address of RAM

12.6 Set X address of RAM

12.7 Set HV generator stages

12.7.1 S[1:0]

12.8 Temperature control

12.9 Bias system

12.10 Set VOP value
13 LIMITING VALUES
14 HANDLING
15 DC CHARACTERISTICS
16 AC CHARACTERISTICS
17 RESET
18 APPLICATION INFORMATION
19 CHIP INFORMATION
20 PAD INFORMATION
21 DEVICE PROTECTION DIAGRAM
22 TRAY INFORMATION
23 DEFINITIONS
24 LIFE SUPPORT APPLICATIONS
25 PURCHASE OF PHILIPS I2C COMPONENTS
26 BARE DIE DISCLAIMER

1999 Aug 16 3

Philips Semiconductors Product specification

65 × 102 pixels matrix LCD driver PCF8548

1 FEATURES

• Single-chip LCD controller/driver

• 65 row and 102 column outputs

• Display data RAM 65 × 102 bits

• On-chip:

– Configurable 5 (4, 3 and 2) × voltage multiplier

generating V

LCD

(external V

LCD

also possible)
– Generation of intermediate LCD bias voltages
– Oscillator requires no external components

(external clock also possible).

• 400 kbits/s fast I2C-bus interface

• CMOS compatible inputs

• Mux rate: 1 : 65

• Logic supply voltage range V

DD1

to VSS:

– 1.9 to 5.5 V.

• High voltage generator supply voltage range V

DD2

to

VSS and V

DD3

to VSS:

– 2.4 to 4.5 V with LCD voltage internally generated

(voltage generator enabled).

• Display supply voltage range V

LCD

to VSS:

– 4.5 to 9.0 V

• Low power consumption, suitable for battery operated
systems

• Temperature compensation of V

LCD

• Slim chip layout, suitable for Chip-On-Glass (COG)
applications

• Programmable bottom row pads mirroring and top row
pads mirroring, for compatibility with both Tape Carrier
Package (TCP) and COG applications.

2 APPLICATIONS

• Telecom equipment

• Portable instruments

• Point of sale terminals.

3 GENERAL DESCRIPTION

The PCF8548is a low power CMOS LCD controller driver,
designed to drive a graphic display of 65 rows and
102 columns. All necessary functions for the display are
provided in a single chip, including on-chip generation of
LCD supply and bias voltages, resulting in a minimum of
external components and low power consumption.
The PCF8548 interfaces to most microcontrollers via an
I2C-bus interface.

3.1 Packages

The PCF8548is available aschip with bumpsin tray;tape
carrier package is available on request.

4 ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

PCF8548U/2 Tray chip with bumps in tray −
PCF8548U/9 Bumped wafer quarter wafer −

1999 Aug 16 4

Philips Semiconductors Product specification

65 × 102 pixels matrix LCD driver PCF8548

5 BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGS393

DISPLAY DATA RAM

65 × 102 BITS

DATA LATCHES

COLUMN DRIVERS

SHIFT REGISTER

ROW DRIVERS

C0 to C101

PCF8548

R0 to R64

102

DISPLAY CONTROL LOGIC

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12

TIMING

GENERATOR

OSCILLATOR

OSC

I

2

C-BUS

INTERFACE

SA0SDAOUT SDAIN SCL

V

LCDOUT

V

LCDSENSE

V

LCDIN

RES

V

SS2

V

SS1

V

DD1

V

DD2VDD3

HIGH

VOLTAGE

GENERATOR

4 STAGES

BIAS

VOLTAGE

GENERATOR

65

6 PINNING

SYMBOL PAD DESCRIPTION

RES 1 external reset input (active

LOW)

SDAOUT 2 I

2

C-bus data output

SDAIN 3 and 4 I

2

C-bus data input

SCL 5 and 6 I

2

C-bus clock input
T2 7 test 2 output
SA0 8 least significant bit of slave

address
T7 to T5 9 to 11 test inputs
T4 and T3 12 and 13 test input/output
T1 14 test input
V

SS1

15 to 20 negative power supply 1

V

SS2

21 to 26 negative power supply 2

V

LCDOUT

28 to 33 voltage multiplier output

V

LCDSENSE

34 voltage multiplier

regulation input (V

LCD

)

V

LCDIN

35 to 40 LCD supply voltage
R32 to R19 41 to 54 LCD row driver outputs
R0 to R18 57 to 75 LCD row driver outputs
C0 to C101 76 to 177 LCD column driver outputs
R50 to R33 178 to 195 LCD row driver outputs
R51 to R64 198 to 211 LCD row driver outputs
T12 to T9 212 to 215 test outputs
OSC 216 oscillator
T8 217 test input
V

DD1

218 to 223 supply voltage 1

V

DD3

224 to 226 supply voltage 3

V

DD2

227 to 233 supply voltage 2
27, 55, 56,

196 and 197

dummy pads

SYMBOL PAD DESCRIPTION

1999 Aug 16 5

Philips Semiconductors Product specification

65 × 102 pixels matrix LCD driver PCF8548

7 PIN FUNCTIONS

7.1 R0 to R64: row driver outputs

These pads output the row signals.

7.2 C0 to C101: column driver outputs

These pads output the column signals.

7.3 V

SS1

and V

SS2

: negative power supply rails

V

SS2

is related to V

DD2

and V

DD3

and V

SS1

is related to

V

DD1

.

7.4 V

DD1

to V

DD3

: positive power supply rails

V

DD2

and V

DD3

are the supply voltages for the internal
voltage generator. Both have to be at the same voltage
and must beconnected together outside of the chip. If the
internal voltagegenerator isnot used, they should bothbe
connected to power or to the V

DD1

pad.

V

DD1

is used as the power supply for the rest of the chip.

This voltage can be a different voltage than V

DD2

and

V

DD3

.

7.5 V

LCDIN

: LCD power supply

Internally generated positive power supply for the liquid
crystal display. An external LCD supply voltage can be
supplied using the V

LCDIN

pad. In this case, V

LCDOUT

has
to be connected to ground, and the internal voltage
generator has to be programmed to zero. If the PCF8548
is in power-down mode, the external LCD supply voltage
must be switched off.

7.6 V

LCDOUT

: LCD power supply

Positive power supply for the liquid crystal display. If the
internal voltage generator is used, the two supply rails
V

LCDIN

and V

LCDOUT

must be connected together and an

external capacitor must be connected (see Fig.19).

7.7 V

LCDSENSE

: voltage multiplier regulation input

(V

LCD

)

V

LCDSENSE

is the input voltage for the internal voltage

multiplier regulation.
If the internal voltage generator is used then V

LCDSENSE

must be connected to V

LCDOUT

. If an external supply

voltage is used then V

LCDSENSE

must be connected to

ground.

7.8 T1 to T12: test pads

T1 and T3 to T7 must be connected to V

SS1

. T8 must be

connected to V

DD1

. T2 and T9 to T12 must be left

open-circuit; not accessible to user.

7.9 SDAIN and SDAOUT: I

2

C-bus data lines

Serial data and acknowledge lines for the I2C-bus.
By connecting SDAINto SDAOUT,the SDA linebecomes
fully I2C-bus compatible. Having the acknowledge output
(SDAOUT) separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications.
In COG applications where the track resistance from the
SDAOUT padto the system SDA line can besignificant, a
potential divider is generated by the bus pull-up resistor
and the Indium Tin Oxide (ITO) track resistance. It is
possible that during the acknowledge cycle the PCF8548
will not be able to create a valid logic 0 level. By splitting
the SDA input from the output thedevice could be used in
a mode that ignores the acknowledge bit. In COG
applications wherethe acknowledge cycleis required, it is
necessary to minimize the track resistance from the
SDACK pad to the system SDA line to guarantee a valid
LOW level.

7.10 SCL: I

2

C-bus clock signal

I2C-bus serial clock signal input.

7.11 SA0: slave address

Two different slave addresses can be selected using the
SA0 pad. This allows two PCF8548 LCD drivers to be
connected to the same I2C-bus.

7.12 OSC: oscillator

When the on-chip oscillator is used this input must be
connected to V

DD1

. An external clock signal, if used, is

connected to this input.

7.13 RES: reset

This signalis used toreset the device.The signal isactive
LOW.

1999 Aug 16 6

Philips Semiconductors Product specification

65 × 102 pixels matrix LCD driver PCF8548

8 BLOCK DIAGRAM FUNCTIONS

8.1 Oscillator

The on-chip oscillator provides the clock signal for the
display system.No external componentsare required and
the OSC input must be connected to V

DD1

. An external

clock signal (if used), is connected to this input.

8.2 I

2

C-bus interface

The I2C-bus interface receives and executes the
commands sent viathe I2C-bus. It alsoreceives RAMdata
and sends it to the RAM.

8.3 Display control logic

The display control logic generates the control signals to
read from the RAM via the 102 bits parallel port. It also
generates the control signals for the row and column
drivers.

8.4 Display Data RAM (DDRAM)

The PCF8548 contains a 65 × 102 bit static RAM which
storesthe displaydata. TheRAM is dividedinto 8 banksof
102 bytes and 1 bank of 102 bits [(8 × 8+1)×102 bits].
DuringRAM access,data istransferred tothe RAMvia the
I2C-bus interface. There is a direct correspondence
between the X address and column output number.

8.5 Timing generator

The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the I

2

C-bus.

8.6 LCD row and column drivers

The PCF8548 contains 65 row and 102 column drivers,
which connect the appropriate LCD bias voltages to the
display in accordance with the data to be displayed.
Figure 2shows typicalwaveforms.Unused outputsshould
be left unconnected.

9 INITIALIZATION

Immediately following Power-on, all internal registers and
theRAM contentare undefined.A resetpulse mustfirst be
applied.

Reset isaccomplished by applying an external RES pulse
(active LOW).When reset occurswithin the specified time
allinternal registersareinitialized, howeverthe RAM isstill
undefined. The state after reset is described in
Section 12.1.

The RES input must be ≤0.3 VDD when VDD reaches
V

DD(min)

(or higher)within a maximumtime t

VHRL

after V

DD

goes HIGH (see Fig.17).

1999 Aug 16 7

Philips Semiconductors Product specification

65 × 102 pixels matrix LCD driver PCF8548

MGS671

ROW 0
R0 (t)

ROW 1
R1 (t)

COL 0
C0 (t)

COL 1
C1 (t)

0 V

0 V

V3 − V

SS

frame n frame n + 1

012345678... ... 64 012345678... ... 64

V

state1

(t)

V

state1

(t)

V

state2

(t)

V

LCD

V

2

V

3

V

4

V

5

V

SS

V

LCD

V

2

V

3

V

4

V

5

V

SS

V

LCD

V

2

V

3

V

4

V

5

V

SS

V

LCD

V

2

V

3

V

4

V

5

V

SS

V

LCD

− V

SS

V

LCD

− V

2

V4 − V

5

VSS − V

5

V4 − V

LCD

V3 − V

SS

V

SS

− V

LCD

0 V

0 V

V3 − V

SS

V

state2

(t)

V

LCD

− V

SS

V

LCD

− V

2

V4 − V

5

V4 − V

LCD

V3 − V

SS

VSS − V

5

V

SS

− V

LCD

Fig.2 Typical LCD driver waveforms.

V

state1

(t) = C1(t) − R0(t).

V

state2

(t) = C1(t) − R1(t).

1999 Aug 16 8

Philips Semiconductors Product specification

65 × 102 pixels matrix LCD driver PCF8548

Fig.3 DDRAM to display mapping.

top of LCD

MGS395

DDRAM

bank 0

bank 1

bank 2

bank 3

bank 7

bank 8

LCD

1999 Aug 16 9

Philips Semiconductors Product specification

65 × 102 pixels matrix LCD driver PCF8548

10 ADDRESSING

The Display Data RAM (DDRAM) of the PCF8548 is accessed as indicated in Figs 3, 6, 7, 8 and 9. The DDRAM has a
matrix of 65 × 102 bits. The RAM cells are addressed by the X and Y address pointers. The address ranges are X0 to
X101 (1100101b) and Y0 to Y8(1000b). Addressesoutside ofthese rangesare not allowed. In verticaladdressing mode
(V = 1) the Y address increments after each byte (see Fig.5). After the last Y address (Y = 8), Y wraps around to 0 and
X incrementsto addressthe nextcolumn. Inthe horizontaladdressing mode (V = 0)the X addressincrements aftereach
byte (see Fig.4). After thelast X address(X = 101), X wraps around to 0 andY increments toaddress thenext row. After
the very last address (X = 101 and Y = 8) the address pointers wrap around to address X = 0 andY=0.

10.1 Display data RAM structure

Fig.4 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).

handbook, full pagewidth

MGS396

012
102 103 104
204 205 206
306 307 308
408 409 410
510 511 512
612 613 614
714 715 716
816 817 818

0

8917

0 101X address

Y address

1999 Aug 16 10

Philips Semiconductors Product specification

65 × 102 pixels matrix LCD driver PCF8548

The DO bit defines the bit order (MSB on top or MSB on bottom) for writing to the RAM (see Figs 6 and 7).

Fig.5 Sequence of writing data bytes into RAM with vertical addressing (V = 1).

handbook, full pagewidth

MGS397

09

110

2

3

4

5

6

7

8

0

8917

0 101X address

Y address

Fig.6 RAM byte organization, if DO = 0.

handbook, full pagewidth

MGS398

MSB

LSB

MSB

LSB

1999 Aug 16 11

Philips Semiconductors Product specification

65 × 102 pixels matrix LCD driver PCF8548

The MX bit allows a horizontal mirroring; when MX = 1, the X address space is mirrored. The address X = 0 is then
located at the right side (column 101) of the display(see Fig.9). When MX = 0 the mirroringis disabled and the address
X = 0 is located at the left side (column 0) of the display (see Fig.8).

Fig.7 RAM byte organization, if DO = 1.

handbook, full pagewidth

MGS399

LSB

MSB

LSB

MSB

Fig.8 RAM format addressing (MX = 0).

handbook, full pagewidth

MGS400

0

8

0 101X address

Y address

1999 Aug 16 12

Philips Semiconductors Product specification

65 × 102 pixels matrix LCD driver PCF8548

10.2 RAM access

If the D/C bit is logic 1 the RAM can be written to. The data is written to the RAM during the acknowledge cycle.

Fig.9 RAM format addressing (MX = 1).

handbook, full pagewidth

MBL044

0

8

101 0X address

Y address