Philips PCF8535 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

PCF8535

65 × 133 pixel matrix driver

Objective specification			1999 Aug 24
File under Integrated Circuits, IC12

Philips Semiconductors	Objective specification
65 × 133 pixel matrix driver	PCF8535

CONTENTS

1FEATURES

2APPLICATIONS

3GENERAL DESCRIPTION

4ORDERING INFORMATION

5BLOCK DIAGRAM

5.1Block diagram functions

5.1.1Oscillator

5.1.2Power-on reset

5.1.3I2C-bus controller

5.1.4Input filters

5.1.5Display data RAM

5.1.6Timing generator

5.1.7Address counter

5.1.8Display address counter

6 PINNING

6.1Pin functions

6.1.1R0 to R64

6.1.2C0 to C132

6.1.3VSS1 and VSS2

6.1.4VDD1 to VDD3

6.1.5VLCDOUT

6.1.6VLCDIN

6.1.7VLCDSENSE

6.1.8SDA

6.1.9SDAOUT

6.1.10SCL

6.1.11SA0 and SA1

6.1.12OSC

6.1.13RES

6.1.14T1, T2, T3, T4 and T5

7	FUNCTIONAL DESCRIPTION

7.1Reset

7.2Power-down

7.3LCD voltage selector

7.4Oscillator

7.5Timing

7.6Column driver outputs

7.7Row driver outputs

7.8Drive waveforms

7.9Set multiplex rate

7.10Bias system

7.10.1Set bias system

7.11Temperature measurement

7.11.1Temperature read back

7.12Temperature compensation

7.12.1Temperature coefficients

7.13VOP

7.13.1Set VOP value

7.14Voltage multiplier control

7.14.1S[1:0]

7.15Addressing

7.15.1Input addressing

7.15.2Output addressing

7.16Instruction set

7.16.1RAM read/write command page

7.16.2Function and RAM command page

7.16.3Display setting command page

7.16.4HV-gen command page

7.16.5Special feature command page

7.16.6Instruction set

7.17I2C-bus interface

7.17.1Characteristics of the I2C-bus

7.17.2I2C-bus protocol

8LIMITING VALUES (PROVISIONAL)

9HANDLING

10DC CHARACTERISTICS

11AC CHARACTERISTICS

12RESET TIMING

13APPLICATION INFORMATION

14BONDING PAD LOCATIONS

15DEVICE PROTECTION DIAGRAM

16TRAY INFORMATION

17DEFINITIONS

18LIFE SUPPORT APPLICATIONS

19PURCHASE OF PHILIPS I2C COMPONENTS

20BARE DIE DISCLAIMER

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Philips Semiconductors	Objective specification
65 × 133 pixel matrix driver	PCF8535

1 FEATURES

∙Single-chip LCD controller/driver

∙65 row, 133 column outputs

∙Display data RAM 65 × 133 bits

∙133 icons (last row is used for icons)

∙Fast mode I2C-bus interface (400 kbits/s)

∙Software selectable multiplex rates: 1 : 17, 1 : 26, 1 : 34, 1 : 49 and 1 : 65

∙On-chip:

– Generation of intermediate LCD bias voltages

– Oscillator requires no external components (external clock also possible)

– Generation of VLCD.

∙CMOS compatible inputs

∙Software selectable bias configuration

∙Logic supply voltage range VDD1 to VSS1 4.5 to 5.5 V

∙Supply voltage range for high voltage part VDD2 and VDD3 to VSS2 and VSS3 4.5 to 5.5 V

∙Display supply voltage range VLCD to VSS:

– Mux rate 1 : 65: 8 to 16 V.

∙Low power consumption, suitable for battery operated systems

∙Internal Power-on reset and/or external reset

∙Temperature read back available

∙Manufactured in N-well silicon gate CMOS process.

4 ORDERING INFORMATION

2 APPLICATIONS

∙Automotive information systems

∙Telecommunication systems

∙Point-of-sale terminals

∙Instrumentation.

3 GENERAL DESCRIPTION

The PCF8535 is a low power CMOS LCD row/column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 17, 1 : 26, 1 : 34, 1 : 49 and 1 : 65. Furthermore, it can drive up to 133 icons. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and low power consumption. The PCF8535 is compatible with most microcontrollers and communicates via an industry standard two-line bidirectional I2C-bus serial interface. All inputs are CMOS compatible.

	TYPE NUMBER		PACKAGE
		NAME	DESCRIPTION	VERSION
	PCF8535U	−	chip with bumps in tray	−

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Philips Semiconductors	Objective specification
65 × 133 pixel matrix driver	PCF8535
5 BLOCK DIAGRAM

		R0 to R64	C0 to C132	VDD1	VDD2	VDD3
		65	133
VSS1		ROW	COLUMN	POWER-ON RESET
VSS2		DRIVERS	DRIVERS
T4, T5		PCF8535			INTERNAL
					RESET
T1, T2, T3							RES
			DATA LATCHES		OSCILLATOR		OSC
	BIAS
VLCDIN			MATRIX
	VOLTAGE
			LATCHES
	GENERATOR
					TIMING
					GENERATOR
VLCDSENSE		DISPLAY DATA RAM
	VLCD		MATRIX DATA		DISPLAY
					ADDRESS
VLCDOUT	GENERATOR
			RAM		COUNTER
SCL	INPUT	I2C-BUS		COMMAND	ADDRESS
SDA
	FILTERS	CONTROL		DECODER	COUNTER
SDAOUT
						MGS669
		SA1	SA0

Fig.1 Block diagram.

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65 × 133 pixel matrix driver	PCF8535

5.1Block diagram functions

5.1.1OSCILLATOR

The on-chip oscillator provides the display clock for the system; it requires no external components. Alternatively, an external display clock may be provided via the OSC

input. The OSC input must be connected to VDD1 or VSS1 when not in use. During power-down additional current

saving can be made if the external clock is disabled.

5.1.2POWER-ON RESET

The on-chip Power-on reset initializes the chip after power-on or power failure.

5.1.3I2C-BUS CONTROLLER

The I2C-bus controller detects the I2C-bus protocol, slave address, commands and display data bytes. It performs the conversion of the data input (serial-to-parallel).

The PCF8535 acts as an I2C-bus slave and therefore cannot initiate bus communication.

5.1.4INPUT FILTERS

Input filters are provided to enhance noise immunity in electrically adverse environments; RC low-pass filters are provided on the SDA, SCL and RES lines.

5.1.5DISPLAY DATA RAM

The PCF8535 contains a 65 × 133 bit static RAM which stores the display data. The RAM is divided into 9 banks of 133 bytes. The last bank is used for icon data and is only one bit deep. During RAM access, data is transferred to the RAM via the I2C-bus interface. There is a direct correspondence between the X address and the column output number.

5.1.6TIMING GENERATOR

The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data bus.

5.1.7ADDRESS COUNTER

The Address Counter (AC) sends addresses to the Display Data RAM (DDRAM) for writing.

5.1.8DISPLAY ADDRESS COUNTER

The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The display status (all dots on or off, normal or inverse video) is set via the I2C-bus.

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Philips Semiconductors					Objective specification
	65 × 133 pixel matrix driver				PCF8535
6 PINNING
		SYMBOL	PAD		DESCRIPTION
			1		dummy pad
			2		bump/alignment mark 1
R0 to R15			3 to 18		LCD row driver outputs
C0 to C132			19 to 151		LCD column driver outputs
R47 to R33			152 to 166		LCD row driver outputs
			167		bump/alignment mark 2
			168		dummy pad
R48 to R64			169 to 185		LCD row driver outputs; R64 is icon row
			186		bump/alignment mark 3
			187 to 189		dummy pad
OSC			190		oscillator
VLCDIN			191 to 196		LCD supply voltage
VLCDOUT			197 to 203		voltage multiplier output
VLCDSENSE			204		voltage multiplier regulation input (VLCD)
			205 and 206		dummy pad
			207		external reset input (active LOW)
	RES
T3			208		test output 3
T2			209		test output 2
T1			210		test output 1
VDD2			211 to 218		supply voltage 2
VDD3			219 to 222		supply voltage 3
VDD1			223 to 228		supply voltage 1
			229		dummy pad
SDA			230 and 231		I2C-bus serial data inputs
SDAOUT			232		I2C-bus serial data output
SA1			233		I2C-bus slave address input
SA0			234		I2C-bus slave address input
VSS2			235 to 242		ground 2
VSS1			243 to 250		ground 1
T5			251		test input 5
T4			252		test input 4
			253		dummy pad
SCL			254 and 255		I2C-bus serial clock inputs
			256		bump/alignment mark 4
R32 to R16			257 to 273		LCD row driver outputs

6.1Pin functions

6.1.1R0 TO R64

These pads output the display row signals.

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65 × 133 pixel matrix driver	PCF8535

6.1.2C0 TO C132

These pads output the display column signals.

6.1.3VSS1 AND VSS2

VSS1 and VSS2 must be connected together.

6.1.4VDD1 TO VDD3

VDD1 is the logic supply. VDD2 and VDD3 are for the voltage multiplier. For split power supplies VDD2 and VDD3 must be

connected together. If only one supply voltage is available, all three supplies must be connected together.

6.1.5VLCDOUT

If, in the application, an external VLCD is used, VLCDOUT must be left open-circuit; otherwise (if the internal voltage

multiplier is enabled) the chip may be damaged. VLCDOUT should not be driven when VDD1 is below its minimum

allowed value otherwise a low impedance path between VLCDOUT and VSS1 will exist.

6.1.6VLCDIN

This is the VLCD supply for when an external VLCD is used. If the internal VLCD generator is used, then VLCDOUT and VLCDIN must be connected together. VLCDIN should not be driven when VDD1 is below its minimum allowed value,

otherwise a low impedance path between VLCDIN and VSS1 will exist.

6.1.7VLCDSENSE

This is the input to the internal voltage multiplier regulator.

It must be connected to VLCDOUT when the internal voltage generator is used otherwise it may be left open-circuit.

VLCDSENCE should not be driven when VDD1 is below its minimum allowed value, otherwise a low impedance path

between VLCDSENCE and VSS1 will exist.

6.1.8SDA

I2C-bus serial data input.

6.1.9SDAOUT

SDAOUT is the serial data acknowledge for the I2C-bus. By connecting SDAOUT to SDA externally, the SDA line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in Chip-On-Glass (COG) applications.

In COG applications where the track resistance from the SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor

and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the PCF8535 will not be able to create a valid logic 0 level. By splitting the SDA input from the SDAOUT output the device could be used in a mode that ignores the acknowledge bit.

In COG applications where the acknowledge cycle is required or where read back is required, it is necessary to minimize the track resistance from the SDAOUT pad to the system SDA line to guarantee a valid LOW level.

6.1.10SCL

I2C-bus serial clock input.

6.1.11SA0 AND SA1

Least significant bits of the I2C-bus slave address.

Table 1 Slave address; see note 1

SA1 AND SA0	MODE	SLAVE ADDRESS
0 and 0	write	78H
	read	79H
0 and 1	write	7AH
	read	7BH
1 and 0	write	7CH
	read	7DH
1 and 1	write	7EH
	read	7FH

Note

1.The slave address is a concatination of the following bits {01111, SA1, SA0 and R/W}.

6.1.12OSC

If the on-chip oscillator is used this input must be connected to VDD1 or VSS1.

6.1.13RES

External reset pad: when this pad is LOW the chip will be reset; see Section 7.1. If an external reset is not required,

this pad must be tied to VDD1. Timing for the RES pad is given in Chapter 12.

6.1.14T1, T2, T3, T4 AND T5

In applications T4 and T5 must be connected to VSS. T1, T2 and T3 are to be left open-circuit.

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Philips Semiconductors	Objective specification
65 × 133 pixel matrix driver	PCF8535

7 FUNCTIONAL DESCRIPTION

The PCF8535 is a low power LCD driver designed to interface with microprocessors/microcontrollers and a wide variety of LCDs.

The host microprocessor/microcontroller and the PCF8535 are both connected to the I2C-bus. The SDA and SCL lines must be connected to the positive power supply via pull-up resistors. The internal oscillator requires no external components. The appropriate intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and suitable capacitors for decoupling VLCD and VDD.

						VLCD
VDD1 to VDD3
VDD(I2C)				DD1,	DD3	DD2	133 column drivers
				V	V	V	65 row drivers
		HOST
					PCF8535
Rpu	Rpu	MICROPROCESSOR/					LCD PANEL
		MICROCONTROLLER
			SS1		SS2
			V	V
		VSS
RES
SA0
SA1
SCL
SDA
VSS1, VSS2							MGS670
		Fig.2	Typical system configuration.
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Philips Semiconductors	Objective specification
65 × 133 pixel matrix driver	PCF8535

7.1Reset

The PCF8535 has two reset modes; internal Power-on reset or external reset. Reset initiated from either the RES pad or the internal Power-on reset block will initialize the chip to the following starting condition:

∙Power-down mode (PD = 1)

∙Horizontal addressing (V = 0); no mirror X or Y (MX = 0 and MY = 0)

∙Display blank (D = 0 and E = 0)

∙Address counter X[6:0] = 0, Y[2:0] = 0 and XM0 = 0

∙Bias system BS[2:0] = 0

∙Multiplex rate M[2:0] = 0 (Mux rate 1 : 17)

∙Temperature control mode TC[2:0] = 0

∙HV-gen control, HVE = 0 the HV generator is switched off, PRS = 0 and S[1:0] = 00

∙VLCDOUT is equal to 0 V

∙RAM data is unchanged (Note: RAM data is undefined after power-up)

∙All row and column outputs are set to VSS (display off)

∙TRS and BRS are set to zero

∙Direct mode is disabled (DM = 0)

∙Internal oscillator is selected, but not running (EC = 0)

∙Bias current set to low current mode (IB = 0).

7.2Power-down

During power-down all static currents are switched off (no internal oscillator, no timing and no LCD segment drive system) and all LCD outputs are internally connected to VSS. The serial bus function remains active.

7.3LCD voltage selector

The practical value for VOP is determined by equating

Voff(rms) with defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast.

7.4Oscillator

The internal logic operation and the multi-level drive signals of the PCF8535 are clocked by the built-in RC oscillator. No external components are required.

7.5Timing

The timing of the PCF8535 organizes the internal data flow of the device. The timing also generates the LCD frame frequency which is derived from the clock frequency generated in the internal clock generator.

7.6Column driver outputs

The LCD drive section includes 133 column outputs (C0 to C132) which should be connected directly to the LCD. The column output signals are generated in

accordance with the multiplexed row signals and with the data in the display latch. When less than 133 columns are required the unused column outputs should be left open-circuit.

7.7Row driver outputs

The LCD drive section includes 65 row outputs

(R0 to R64) which should be connected directly to the LCD. The row output signals are generated in accordance with the selected LCD drive mode. If lower Mux rates or less than 65 rows are required, the unused outputs should be left open-circuit.

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65 × 133 pixel matrix driver	PCF8535

7.8Drive waveforms

ROW 0

R0 (t)

VLCD

V2

V3

V4

V5

VSS

ROW 1

R1 (t)

VLCD

V2

V3

V4

V5

VSS

COL 0

C0 (t)

VLCD

V2

V3

V4

V5

VSS

COL 1

C1 (t)

VLCD

V2

V3

V4

V5

VSS

VLCD − VSS

V3 − VSS

VLCD − V2

Vstate1(t) 0 V

V3 − VSS

VLCD − VSS

V3 − VSS

VLCD − V2

Vstate2(t) 0 V

V3 − VSS

frame n

frame n + 1

Vstate1(t)

Vstate2(t)

V4 − V5 0 V

VSS − V5

V4 − VLCD

VSS − VLCD

V4 − V5 0 V

VSS − V5

V4 − VLCD

VSS − VLCD

0 1 2 3 4 5 6 7 8...

... 64 0 1 2 3 4 5 6 7 8...

... 64

MGS671

Vstate1(t) = C1(t) − R0(t).

Vstate2(t) = C1(t) − R1(t).

Fig.3 Typical LCD driver waveforms.

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65 × 133 pixel matrix driver	PCF8535

7.9Set multiplex rate

The PCF8535 can be used to drive displays of varying sizes. The multiplex mode selected controls which rows are used. In all cases, the last row is always driven and is intended for icons. If Top Row Swap (TRS) is at logic 1 then the icon row will be output on pad R48. M[2:0] selects the multiplex rate (see Table 2).

Table 2 Multiplex rates

M[2]	M[1]	M[0]	MULTIPLEX RATE	ACTIVE ROWS
0	0	0	1 : 17	R0 to R15 and R64
0	0	1	1 : 26	R0 to R24 and R64
0	1	0	1 : 34	R0 to R32 and R64
0	1	1	1 : 49	R0 to R47 and R64
1	0	0	1 : 65	R0 to R64
	101 − 111		do not use	−

7.10Bias system

7.10.1SET BIAS SYSTEM

The bias voltage levels are set in the ratio of R − R − nR − R − R. Different multiplex rates require different factors n. This

is programmed by BS[2:0]. For optimum bias values, n can be calculated from: n = Mux rate –3

Changing the bias system from the optimum will have a consequence on the contrast and viewing angle. One reason to come away from the optimum would be to reduce the required VOP. A compromise between contrast and VOP must be found for any particular application.

Table 3 Programming the required bias system

BS[2]	BS[1]	BS[0]	n	BIAS MODE	TYPICAL MUX RATES
0	0	0	7	1/	1 : 100
				11
0	0	1	6	1/	1 : 80
				10
0	1	0	5	1/9	1 : 65
0	1	1	4	1/8	1 : 49
1	0	0	3	1/7	1 : 33
1	0	1	2	1/6	1 : 26
1	1	0	1	1/5	1 : 17
1	1	1	0	1/4	1 : 9

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65 × 133 pixel matrix driver	PCF8535

Table 4 Example of LCD bias voltage for 1/7bias, n = 3

SYMBOL	BIAS VOLTAGE FOR 1/ BIAS
	7
V1	VLCD
V2	6/7 × VLCD
V3	5/7 × VLCD
V4	2/7 × VLCD
V5	1/7 × VLCD
V6	VSS

7.11Temperature measurement

7.11.1TEMPERATURE READ BACK

The PCF8535 has an in-built temperature sensor. For power saving, the sensor should only be enabled when a measurement is required. It will not operate in

power-down mode. The temperature read back requires a clock to operate. Normally the internal clock is used but, if the device is operating from an external clock, then this must be present for the measurement to work. VDD2 and VDD3 must also be applied. A measurement is initialized by setting the SM bit. Once started the SM bit will be automatically cleared. An internal oscillator will be initialized and allowed to warm-up for approximately

2 frame periods. After this the measurement starts and lasts for a maximum of 2 frame periods.

Temperature data is returned via a status register. During the measurement the register will contain zero. Once the measurement is completed the register will be updated with the current temperature (non zero value). Because the I2C-bus interface is asynchronous to the temperature measurement, read back prior to the end of the measurement is not guaranteed. If this mode is required the register should be read twice to validate the data.

For calibrating the temperature read-out a measurement must be taken at a defined temperature. The offset between the ideal read-out and the actual result has to be stored into a non-volatile register (e.g. EEPROM);

Offset = TRideal –TRmeas

(2)

where TRmeas is the actual temperature read-out of the PCF8535.

The calibrated temperature read-out can be calculated for each measurement as follows:

TRcal = TRmeas + Offset

(3)

The accuracy after the calibration is ±6.7% (plus ±1 lsb) of the difference between the current temperature and the calibration temperature. For this reason a calibration at or near the most sensitive temperature for the display is recommended.

E.g. for a calibration at 25 °C with the current temperature at −20 °C, the absolute error may be calculated as:

Absolute error = 0.067 × (25 °C − −20 °C) = ±3 °C + ±1 lsb = ±4.17 °C.

7.12Temperature compensation

7.12.1TEMPERATURE COEFFICIENTS

Due to the temperature dependency of the liquid crystals viscosity the LCD controlling voltage, V must be increased at lower temperatures to maintain optimum contrast.

Figure 4 shows VLCD as a function of temperature for a typical high multiplex rate liquid.

In the PCF8535 the temperature coefficient of VLCD can be selected from 8 values by setting bits TC[2:0],

see Table 5.

The ideal temperature read-out can be calculated as follows;

TR		= 128	1	(1)
	ideal		+ (T –27 °C) × --
			c

where T is the on-chip temperature in °C and c is the conversion constant; c = 1.17 °C/lsb.

To improve the accuracy of the temperature measurement a calibration is recommended during the assembly of the final product.

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65 × 133 pixel matrix driver	PCF8535

MGS473

VLCD

0 °C

T

Fig.4 VLCD as function of liquid crystal temperature (typical values).

Table 5 Selectable temperature coefficients

TC[2]	TC[1]	TC[0]		TC VALUE		UNIT
0	0	0		0		1/°C
0	0	1		-0.44 ´ 10−3		1/°C
0	1	0		-1.10 ´ 10−3		1/°C
0	1	1		-1.45 ´ 10−3		1/°C
1	0	0		-1.91 ´ 10−3		1/°C
1	0	1		-2.15 ´ 10−3		1/°C
1	1	0		-2.32 ´ 10−3		1/°C
1	1	1		-2.74 ´ 10−3		1/°C
7.13 VOP
7.13.1 SET VOP VALUE
The voltage at the reference temperature can be
calculated as: [VLCD (T = Tcut)]
VLCD(Tcut)	= (a + VOP ´ b)					(4)

The operating voltage, VOP, can be set by software. The generated voltage is dependent on the temperature, programmed Temperature Coefficient (TC) and the programmed voltage at the reference temperature (Tcut):

VLCD = (a + VOP ´ b) ´ (1 + ((T –Tcut) ´ TC))

(5)

The values for Tcut, a and b are given in Table 6.

The maximum voltage that can be generated is dependent on the voltage VDD2 and the display load current.

Two overlapping VOP ranges are selectable via the command page “Hv-gen control”, see Fig.5.

The low range offers programming from 4.5 to 10.215 V, with the high range from 10.215 to 15.93 V at the cut point temperature, Tcut. Care must be taken, when using temperature coefficients, that the programmed voltage does not exceed the maximum allowed VLCD voltage, see Chapter 10.

For a particular liquid, the optimum VLCD can be calculated for a given multiplex rate. For a Mux rate of 1 : 65, the optimum operating voltage of the liquid can be calculated as:

VLCD	=	1 +			65		´ Vth	= 6.85	´ Vth	(6)
			æ			1
	2	´		1	–		ö
			è			65ø

where Vth is the threshold voltage of the liquid crystal material used.

Table 6 Values for parameters of the HV generator programming

SYMBOL	BITS	VALUE	UNIT
a	PRS = 0	4.5	V
	PRS = 1	10.215	V
b		0.045	V
Tcut		27	°C

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65 × 133 pixel matrix driver																		PCF8535
VLCD
	b
a
00	01	02	03	04 05 06 . . .	5F	6F	7F	00	01	02	03	04	05	06	. . .	5F	6F	7F
				LOW									HIGH
																	MGS472

VOP[6:0] programming (00H to 7FH, programming range LOW and HIGH).

Fig.5 VOP programming of PCF8535.

7.14Voltage multiplier control

7.14.1S[1:0]

The PCF8535 incorporates a software configurable voltage multiplier. After reset (RES) the voltage multiplier is set to 2 × VDD2. Other voltage multiplier factors are set via the HV-gen command page. Before switching on the charge pump, the charge pump has to be pre-charged using the following sequence.

A starting state of HVE = 0, DOF = 0, PD = 1 and DM = 0 is assumed. A small delay between steps is indicated. The recommended wait period is 20 μs per 100 nF of capacitance on VLCD1.

1.Set DM = 1 and PD = 0

2.Delay

3.Set the multiplication factor to 2 by setting S[1:0] = 00

4.Set the required VOP and PRS.

5.Set HVE = 1 to switch-on the charge pump with a multiplication factor of 2

6.Delay

7.Increase the number of stages, one at a time, with a delay between each until the required level is achieved.

Table 7 HV generator multiplication factor

S[1]	S[0]	MULTIPLICATION FACTOR
0	0	2 × VDD2
0	1	3 × VDD2
1	0	4 × VDD2
1	1	5 × VDD2

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65 × 133 pixel matrix driver	PCF8535

7.15Addressing

Addressing of the RAM can be split into two parts; input addressing and output addressing. Input addressing is concerned with writing data into the RAM. Output addressing is almost entirely automatic and taken care of by the device, however, it is possible to affect the output mode.

7.15.1INPUT ADDRESSING

Data is down loaded byte wise into the RAM matrix of the PCF8535 as indicated in Figs 6 to 10.

The display RAM has a matrix of 65 × 133 bits.

The columns are addressed by a combination of the

X address pointer and the X-RAM page pointer, whilst the rows addressed in groups of 8 by the Y address pointer. The X address pointer has a range of 0 to 127 (7FH).

Its range can be extended by the X-RAM page pointer, XM0. The Y address pointer has a range of 0 to 8 (08H). The PCF8535 is limited to 133 columns by 65 rows, addressing the RAM outside of this area is not allowed.

Table 8 Effect of X-RAM page pointer

	X ADDRESS POINTER	X-RAM PAGE POINTER	ADDRESSED COLUMN	ADDRESSED COLUMN
		XM0	MX = 0	MX = 1
	0	0	C0	C132
	1	0	C1	C131
	2	0	C2	C130
	:	:	:	:
	125	0	C125	C7
	126	0	C126	C6
	127	0	C127	C5
	0	1	C128	C4
	1	1	C129	C3
	:	:	:	:
	4	1	C132	C0

Banks 1 to 7 use the entire byte

handbook, fullMSBpagewidth

LSB

Bank 8 is only 1 bit deep and uses the MSB

MSB

LSB

																				XM0 = 0																				XM0 = 1
																																													0
																																													1
																																													2
																																													3
																																													4	address
																																													5	Y
																																													6
																																													7
						icon data																																							8
																											.. ..		.. ..
0	1	2	3	4	5	6		7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22		23	24					119	120	121	122	123	124	125	126	127	0	1	2	3	4
																							X address																					MGS673

Fig.6 RAM format, input addressing.

1999 Aug 24

15

Philips Semiconductors	Objective specification
65 × 133 pixel matrix driver	PCF8535

MSB	bank 0
	top of LCD
Data byte in location	R0
X = 0, Y = 0, MX0 = 0
(MX = 0, MY = 0)

LSB

bank 1

R8

bank 2

R16

LCD

bank 3

R24

MSB	bank 7
Data byte in location	R56
Y = 7, X = 0, MX0 = 0
(MX = 0, MY = 0)

LSB

bank 8

R64

MGS674

Fig.7 DDRAM to display mapping.

1999 Aug 24

16