INTEGRATED CIRCUITS
DATA SHEET
PCF8533
Universal LCD driver for low multiplex rates
Product specification |
1999 Jul 30 |
Supersedes data of 1999 Mar 12
File under Integrated Circuits, IC12
Philips Semiconductors |
Product specification |
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Universal LCD driver for low multiplex rates |
PCF8533 |
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CONTENTS
1FEATURES
2GENERAL DESCRIPTION
3ORDERING INFORMATION
4BLOCK DIAGRAM
5PINNING
6FUNCTIONAL DESCRIPTION
6.1Power-on reset
6.2LCD bias generator
6.3LCD voltage selector
6.4LCD drive mode waveforms
6.4.1Static drive mode
6.4.21 : 2 multiplex drive mode
6.4.31 : 3 multiplex drive mode
6.4.41 : 4 multiplex drive mode
6.5Oscillator
6.5.1Internal clock
6.5.2External clock
6.6Timing
6.7Display register
6.8Segment outputs
6.9Backplane outputs
6.10Display RAM
6.11Data pointer
6.12Subaddress counter
6.13Output bank selector
6.14Input bank selector
6.15Blinker
7 |
CHARACTERISTICS OF THE I2C-BUS |
7.1Bit transfer
7.2START and STOP conditions
7.3System configuration
7.4Acknowledge
7.5PCF8533 I2C-bus controller
7.6Input filters
7.7I2C-bus protocol
7.8Command decoder
7.9Display controller
7.10Cascaded operation
8LIMITING VALUES
9HANDLING
10DC CHARACTERISTICS
11AC CHARACTERISTICS
12BONDING PAD LOCATIONS
13DEVICE PROTECTION
14TRAY INFORMATION
15DEFINITIONS
16LIFE SUPPORT APPLICATIONS
17PURCHASE OF PHILIPS I2C COMPONENTS
18BARE DIE DISCLAIMER
1999 Jul 30 |
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Philips Semiconductors |
Product specification |
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Universal LCD driver for low multiplex rates |
PCF8533 |
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1 FEATURES
·Single-chip LCD controller/driver
·Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing
·Selectable display bias configuration: static, 1¤2 or 1¤3
·Internal LCD bias generation with voltage-follower buffers
·80 segment drives: up to forty 8-segment numeric characters; up to twentyone 15-segment alphanumeric characters; or any graphics of up to 320 elements
·80 ´ 4-bit RAM for display data storage
·Auto-incremented display data loading across device subaddress boundaries
·Display memory bank switching in static and duplex drive modes
·Versatile blinking modes
·LCD and logic supplies may be separated
·Wide power supply range: from 1.8 to 5.5 V
·Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 6.5 V for guest-host LCDs and high threshold (automobile) twisted nematic LCDs
·Low power consumption
·400 kHz I2C-bus interface
·TTL/CMOS compatible
·Compatible with 4-bit, 8-bit or 16-bit microprocessors/microcontrollers
·May be cascaded for large LCD applications (up to 5120 segments possible)
·No external components
·Compatible with Chip-On-Glass (COG) technology
·Manufactured in silicon gate CMOS process.
3 ORDERING INFORMATION
2 GENERAL DESCRIPTION
The PCF8533 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 80 segments and can easily be cascaded for larger LCD applications. The PCF8533 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes).
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PCF8533U |
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chip with bumps in tray |
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1999 Jul 30 |
3 |
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30 Jul 1999 |
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BP0 BP1 BP2 BP3 |
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S0 to S79 |
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DIAGRAM BLOCK 4 |
LCD Universal |
Semiconductors Philips |
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80 |
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for driver |
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VLCD |
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BACKPLANE |
DISPLAY SEGMENT OUTPUTS |
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OUTPUTS |
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LCD |
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DISPLAY REGISTER |
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low |
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VOLTAGE |
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SELECTOR |
DISPLAY |
OUTPUT BANK SELECT |
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multiplex |
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CONTROL |
AND BLINK CONTROL |
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LCD BIAS |
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VSS |
GENERATOR |
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PCF8533 |
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DISPLAY |
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CLK |
CLOCK SELECT |
BLINKER |
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RAM |
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4 |
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rates |
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AND TIMING |
TIMEBASE |
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SYNC |
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OSC |
OSCILLATOR |
POWER-ON |
COMMAND |
WRITE DATA |
DATA POINTER AND |
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RESET |
DECODE |
CONTROL |
AUTO INCREMENT |
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SCL |
INPUT |
I2C-BUS |
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SUBADDRESS |
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SDA |
FILTERS |
CONTROLLER |
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COUNTER |
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MGL743 |
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SA0 |
SDAACK |
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VDD |
A0 |
A1 |
A2 |
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Fig.1 |
Block diagram. |
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PCF8533 |
specification Product |
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Philips Semiconductors |
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Product specification |
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Universal LCD driver for low multiplex rates |
PCF8533 |
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5 PINNING |
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SYMBOL |
PAD |
DESCRIPTION |
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SDAACK |
1 |
I2C-bus acknowledge output; note 1 |
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SDA |
2 and 3 |
I2C-bus serial data input; note 1 |
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SCL |
4 and 5 |
I2C-bus serial clock input |
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CLK |
6 |
external clock input/output |
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VDD |
7 |
supply voltage |
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8 |
cascade synchronization input/output |
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SYNC |
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OSC |
9 |
internal oscillator enable input |
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A0, A1 and A2 |
10, 11 and 12 |
subaddress inputs |
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SA0 |
13 |
I2C-bus slave address input; bit 0 |
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VSS |
14 |
logic ground |
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VLCD |
15 |
LCD supply voltage |
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BP0, BP1, BP2 and BP3 |
17, 99, 16 and 98 |
LCD backplane outputs |
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S0 to S79 |
18 to 97 |
LCD segment outputs |
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Note
1. For most applications SDA and SDAACK will be shorted together; see Chapter 7.
6 FUNCTIONAL DESCRIPTION
The PCF8533 is a versatile peripheral device designed to interface any microprocessor/microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 80 segments. The display configurations possible with the PCF8533 depend on the number of active backplane outputs required; a selection of display configurations is given in Table 1.
All of the display configurations given in Table 1 can be implemented in the typical system shown in Fig.2.
The host microprocessor/microcontroller maintains the 2-line I2C-bus communication channel with the PCF8533. The internal oscillator is selected by connecting pad OSC to VSS. The appropriate biasing voltages for the multiplexed
LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and the LCD panel selected for the application.
Table 1 Selection of display configurations
NUMBER OF |
7-SEGMENTS NUMERIC |
14-SEGMENTS |
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ALPHANUMERIC |
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DOT MATRIX |
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BACKPLANES |
SEGMENTS |
DIGITS |
INDICATOR |
CHARACTERS |
INDICATOR |
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SYMBOLS |
SYMBOLS |
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4 |
320 |
40 |
40 |
20 |
40 |
320 dots (4 × 80) |
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3 |
240 |
30 |
30 |
16 |
16 |
240 dots (3 × 80) |
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2 |
160 |
20 |
20 |
10 |
20 |
160 dots (2 × 80) |
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1 |
80 |
10 |
10 |
5 |
10 |
80 dots (1 × 80) |
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1999 Jul 30 |
5 |
Philips Semiconductors |
Product specification |
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Universal LCD driver for low multiplex rates |
PCF8533 |
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handbook, full pagewidthVDD
R |
tr |
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SDAACK |
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2CB |
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SDA |
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VDD |
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VLCD |
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HOST |
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80 segment drives |
LCD PANEL |
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MICRO- |
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SCL |
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PCF8533 |
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PROCESSOR/ |
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(up to 320 |
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MICRO- |
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OSC |
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elements) |
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CONTROLLER |
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4 backplanes |
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A0 |
A1 A2 |
SA0 VSS |
MGL744 |
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VSS
Fig.2 Typical system configuration.
1999 Jul 30 |
6 |
Philips Semiconductors |
Product specification |
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Universal LCD driver for low multiplex rates |
PCF8533 |
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6.1Power-on reset
At Power-on the PCF8533 resets to a starting condition as follows:
1.All backplane outputs are set to VLCD.
2.All segment outputs are set to VLCD.
3.The drive mode ‘1 : 4 multiplex with 1¤3bias’ is selected.
4.Blinking is switched off.
5.Input and output bank selectors are reset (as defined in Table 5).
6.The I2C-bus interface is initialized.
7.The data pointer and the subaddress counter are cleared.
8.Display disabled.
Data transfers on the I2C-bus should be avoided for 1 ms following Power-on to allow completion of the reset action.
6.2LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of the three series resistors connected between VLCD and VSS. The centre resistor can be switched out of the circuit to provide a 1¤2bias voltage level for the 1 : 2 multiplex configuration.
6.3LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by MODE SET commands from the command decoder.
The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VOP and the resulting discrimination ratios (D), are given in Table 2.
A practical value for VOP is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when
the LCD exhibits approximately 10% contrast. In the static drive mode a suitable choice is VOP > 3Vth.
Multiplex drive ratios of 1 : 3 and 1 : 4 with 1¤2bias are possible but the discrimination and hence the contrast
ratios are smaller ( 3 = 1.732 for 1 : 3 multiplex or
21
---------- = 1.528 for 1 : 4 multiplex). 3
The advantage of these modes is a reduction of the LCD full-scale voltage VOP as follows:
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1 : 3 multiplex (1¤2bias): |
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VOP |
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6 ´ Voff(rms) |
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1 : 4 multiplex (1¤2bias): |
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V |
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(4 ´ 3) |
2.309V |
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OP |
--------------------- = |
off(rms) |
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3 |
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These compare with VOP = 3Voff(rms) when 1¤3bias is used. Note: VOP = VLCD.
Table 2 Preferred LCD drive modes: summary of characteristics
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NUMBER OF |
LCD BIAS |
Voff(rms) |
Von(rms) |
Von(rms) |
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LCD DRIVE MODE |
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D = ------------------- |
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BACKPLANES |
LEVELS |
CONFIGURATION |
VOP |
VOP |
Voff(rms) |
static |
1 |
2 |
static |
0 |
1 |
¥ |
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1 : 2 |
2 |
3 |
1¤2 |
0.354 |
0.791 |
2.236 |
1 : 2 |
2 |
4 |
1¤3 |
0.333 |
0.745 |
2.236 |
1 : 3 |
3 |
4 |
1¤3 |
0.333 |
0.638 |
1.915 |
1 : 4 |
4 |
4 |
1¤3 |
0.333 |
0.577 |
1.732 |
1999 Jul 30 |
7 |
Philips Semiconductors |
Product specification |
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Universal LCD driver for low multiplex rates |
PCF8533 |
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6.4LCD drive mode waveforms
6.4.1STATIC DRIVE MODE
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig.3.
handbook, full pagewidth |
Tframe |
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VLCD |
LCD segments |
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BP0 |
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VSS |
state 1 |
state 2 |
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VLCD |
(on) |
(off) |
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Sn |
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VSS |
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VLCD |
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Sn + 1 |
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VSS |
(a) Waveforms at driver. |
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VLCD |
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state 1 |
0 V |
−VLCD
VLCD
state 2 |
0 V |
−VLCD
(b) Resultant waveforms |
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at LCD segment. |
MGL745 |
Vstate1(t) = Vsn(t) − VBP0(t).
Von(rms) = VLCD.
Vstate2(t) = Vsn + 1(t) − VBP0(t).
Voff(rms) = 0 V.
Fig.3 Static drive mode waveforms.
1999 Jul 30 |
8 |
Philips Semiconductors |
Product specification |
|
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Universal LCD driver for low multiplex rates |
PCF8533 |
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6.4.21 : 2 MULTIPLEX DRIVE MODE
When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies. The PCF8533 allows the use of 1¤2bias or 1¤3bias in this mode as shown in Figs 4 and 5.
handbook, full pagewidth
BP0
BP1
Sn
Sn + 1
state 1
state 2
Vstate1(t) = Vsn(t) − VBP0(t).
Von(rms) = 0.791VLCD.
Vstate2(t) = Vsn(t) − VBP1(t).
Voff(rms) = 0.354VLCD.
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Tframe |
VLCD |
LCD segments |
VLCD/2 |
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VSS |
state 1 |
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VLCD |
state 2 |
VLCD/2 |
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VSS |
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VLCD |
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VSS
VLCD
VSS
(a) Waveforms at driver.
VLCD
VLCD/2
0 V
−VLCD/2
−VLCD
VLCD
VLCD/2
0 V
−VLCD/2
−VLCD (b) Resultant waveforms
MGL746
at LCD segment.
Fig.4 Waveforms for the 1 : 2 multiplex drive mode with 1¤2bias.
1999 Jul 30 |
9 |
Philips Semiconductors |
Product specification |
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Universal LCD driver for low multiplex rates |
PCF8533 |
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BP0
BP1
Sn
Sn + 1
state 1
state 2
Tframe
VLCD 2VLCD/3
VLCD/3
VSS
VLCD 2VLCD/3 VLCD/3 VSS
VLCD 2VLCD/3 VLCD/3 VSS
VLCD 2VLCD/3 VLCD/3 VSS
(a) Waveforms at driver.
VLCD 2VLCD/3 VLCD/3
0 V
−VLCD/3 −2VLCD/3 −VLCD
VLCD 2VLCD/3 VLCD/3
0 V
−VLCD/3
−2VLCD/3
−VLCD
(b) Resultant waveforms at LCD segment.
LCD segments
state 1 state 2
MGL747
Vstate1(t) = Vsn(t) − VBP0(t).
Von(rms) = 0.745VLCD.
Vstate2(t) = Vsn(t) − VBP1(t).
Voff(rms) = 0.333VLCD.
Fig.5 Waveforms for the 1 : 2 multiplex drive mode with 1¤3bias.
6.4.31 : 3 MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies, as shown in Fig.6.
1999 Jul 30 |
10 |
Philips Semiconductors |
Product specification |
|
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Universal LCD driver for low multiplex rates |
PCF8533 |
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VLCD |
Tframe |
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LCD segments |
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2VLCD/3 |
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BP0 |
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VLCD/3 |
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VSS |
state 1 |
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VLCD |
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state 2 |
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2VLCD/3 |
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BP1 |
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VLCD/3 |
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VSS |
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VLCD |
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BP2 |
2VLCD/3 |
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VLCD/3 |
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VSS |
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VLCD |
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Sn |
2VLCD/3 |
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VLCD/3 |
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VSS |
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VLCD |
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Sn + 1 |
2VLCD/3 |
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VLCD/3 |
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VSS |
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VLCD |
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Sn + 2 |
2VLCD/3 |
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VLCD/3 |
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VSS |
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(a) Waveforms at driver. |
state 1
state 2
Vstate1(t) = Vsn(t) − VBP0(t).
Von(rms) = 0.638VLCD.
Vstate2(t) = Vsn(t) − VBP1(t).
Voff(rms) = 0.333VLCD.
VLCD
2VLCD/3 VLCD/3 0 V −VLCD/3
−2VLCD/3 −VLCD
VLCD |
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2VLCD/3 |
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VLCD/3 |
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0 V |
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−VLCD/3 |
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−2VLCD/3 |
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−VLCD |
(b) Resultant waveforms |
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MGL748 |
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at LCD segment. |
Fig.6 Waveforms for the 1 : 3 multiplex drive mode.
6.4.41 : 4 MULTIPLEX DRIVE MODE
When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies, as shown in Fig.7.
1999 Jul 30 |
11 |
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