Philips PCF8531U-2-F1 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

PCF8531

34 × 128 pixel matrix driver

Product specification

2000 Feb 11

Supersedes data of 1999 Aug 10

File under Integrated Circuits, IC12

Philips Semiconductors	Product specification
34 × 128 pixel matrix driver	PCF8531

CONTENTS

1FEATURES

2APPLICATIONS

3GENERAL DESCRIPTION

4PACKAGES

5ORDERING INFORMATION

6BLOCK DIAGRAM

7PINNING

8FUNCTIONAL DESCRIPTION

8.1Oscillator

8.2Power-on reset

8.3I2C-bus controller

8.4Input filters

8.5Display data RAM

8.6Timing generator

8.7Address counter

8.8Display address counter

8.9Command decoder

8.10Bias voltage generator

8.11VLCD generator

8.12Reset

8.13Power-down

8.14Column driver outputs

8.15Row driver outputs

8.16LCD waveforms and DDRAM to data mapping

8.17Addressing

8.18Instructions

8.18.1Reset

8.18.2Function set

8.18.3Set Y address

8.18.4Set X address

8.18.5Set multiplex rate

8.18.6Display control (D, E and IM)

8.18.7Set bias system

8.18.8LCD bias voltage

8.18.9Set VOP value:

8.18.10Voltage multiplier control S[1:0]

8.18.11Temperature compensation

9I2C-BUS INTERFACE

9.1Characteristics of the I2C-bus

9.1.1Bit transfer

9.1.2START and STOP conditions

9.1.3System configuration

9.1.4Acknowledge

9.2I2C-bus protocol

9.3Command decoder

10LIMITING VALUES

11HANDLING

12DC CHARACTERISTICS

13AC CHARACTERISTICS

14APPLICATION INFORMATION

15BONDING PAD LOCATIONS

16DEVICE PROTECTION DIAGRAM

17TRAY INFORMATION

18DEFINITIONS

19LIFE SUPPORT APPLICATIONS

20PURCHASE OF PHILIPS I2C COMPONENTS

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Philips Semiconductors	Product specification
34 × 128 pixel matrix driver	PCF8531

1 FEATURES

∙Single-chip LCD controller/driver

∙34 row and 128 column outputs

∙Display data RAM 34 × 128 bits

∙128 icons (last row is used for icons)

∙Fast mode I2C-bus interface (400 kbit/s)

∙Software selectable multiplex rates: 1 : 17, 1 : 26 and 1 : 34

∙Icon mode with Mux rate 1 : 2:

–Featuring reduced current consumption while displaying icons only.

∙On-chip:

–Generation of VLCD (external supply also possible)

–Selectable linear temperature compensation

–Oscillator requires no external components (external clock also possible)

–Generation of intermediate LCD bias voltages

–Power-on reset.

∙No external components required

∙Software selectable bias configuration

∙Logic supply voltage range VDD1 to VSS1 1.8 to 5.5 V

∙Supply voltage range for on-chip voltage generator VDD2 and VDD3 to VSS1 and VSS2 2.5 to 4.5 V

∙Display supply voltage range VLCD to VSS:

–Normal mode 4 to 9 V

–Icon mode 3 to 9 V.

∙Low power consumption, suitable for battery operated systems

∙CMOS compatible inputs

∙Manufactured in silicon gate CMOS process.

2 APPLICATIONS

∙Telecommunication systems

∙Automotive information systems

∙Point-of-sale terminals

∙Instrumentation.

3 GENERAL DESCRIPTION

The PCF8531 is a low power CMOS LCD row/column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 17, 1 : 26 and 1 : 34. Furthermore, it can drive up to 128 icons. All necessary functions for the display are provided in a single chip, including on-chip generation of VLCD and the LCD bias voltages, resulting in a minimum of external components and low power consumption. The PCF8531 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). All inputs are CMOS compatible.

Remark: The icon mode is used to save current. When only icons are displayed, a much lower operating voltage

(VLCD) can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible

to use VDD as VLCD.

4 PACKAGES

The PCF8531 is available as chip with bumps in tray.

5 ORDERING INFORMATION

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
PCF8531U/2	−	chip with bumps in tray	−

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Philips Semiconductors	Product specification
34 × 128 pixel matrix driver	PCF8531
6 BLOCK DIAGRAM

		R0 to R33	C0 to C127	VDD1	VDD2	VDD3
		34	128
VSS1		ROW	COLUMN
VSS2		DRIVERS	DRIVERS
				POWER-ON RESET			ENR
T1
T2		PCF8531			INTERNAL		RES
					RESET
T3
T4
			DATA LATCHES		OSCILLATOR		OSC
	BIAS
VLCDIN			MATRIX
	VOLTAGE
			LATCHES
	GENERATOR
					TIMING
					GENERATOR
VLCDSENSE		DISPLAY DATA RAM
	VLCD		MATRIX DATA		DISPLAY
					ADDRESS
VLCDOUT	GENERATOR
			RAM		COUNTER
SCL	INPUT	I2C-BUS		COMMAND	ADDRESS
SDA
	FILTERS	CONTROL		DECODER	COUNTER
SDACK
						MGS465
		SA0

Fig.1 Block diagram.

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Philips Semiconductors					Product specification
	34 × 128 pixel matrix driver				PCF8531
7 PINNING
	SYMBOL		PAD	DESCRIPTION
			1 to 14	dummy pads
	OSC		15	oscillator input; note 1
	VLCDSENSE		16	voltage multiplier regulation input (VLCD); note 2
	VLCDOUT		17 to 23	voltage multiplier output (VLCD); note 3
	VLCDIN		24 to 30	LCD supply voltage (VLCD); note 2
			31	external reset input (active LOW); note 4
	RES
	VDD3		32 to 34	supply voltage 3; note 5
	VDD2		35 to 42	supply voltage 2; note 5
	VDD1		43 to 49	supply voltage 1; note 5
	SDA		50 and 51	serial data line input of the I2C-bus
	SDACK		52	serial data acknowledge output; note 6
			53	dummy pad
	SA0		54	I2C-bus slave address input; bit 0
	ENR		55	enable internal Power-on reset input; note 7
	T4		56	test 4 input; note 8
	VSS2		57 to 63	ground 2; note 9
	VSS1		64 to 70	ground 1; note 9
	T3		71	test 3 input; note 8
	T1		72	test 1 input; note 8
	SCL		73 and 74	serial clock line input of the I2C-bus
			75 to 77	dummy pads
	T2		78	test 2 output; note 10
			79 to 86	dummy pads
	R0		87	LCD row driver output
	R2		88	LCD row driver output
	R4		89	LCD row driver output
	R6		90	LCD row driver output
	R8		91	LCD row driver output
	R10		92	LCD row driver output
	R12		93	LCD row driver output
	R14		94	LCD row driver output
	R16		95	LCD row driver output
	R18		96	LCD row driver output
	R20		97	LCD row driver output
	R22		98	LCD row driver output
	R24		99	LCD row driver output
	R26		100	LCD row driver output
	R28		101	LCD row driver output
	R30		102	LCD row driver output
	R32		103	LCD row driver output

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Philips Semiconductors			Product specification
34 × 128 pixel matrix driver			PCF8531
SYMBOL	PAD		DESCRIPTION
C0 to C127	104 to 231	LCD column driver outputs
R33	232	LCD row driver output; icon row
R31	233	LCD row driver output
R29	234	LCD row driver output
R27	235	LCD row driver output
R25	236	LCD row driver output
R23	237	LCD row driver output
R21	238	LCD row driver output
R19	239	LCD row driver output
R17	240	LCD row driver output
R15	241	LCD row driver output
R13	242	LCD row driver output
R11	243	LCD row driver output
R9	244	LCD row driver output
R7	245	LCD row driver output
R5	246	LCD row driver output
R3	247	LCD row driver output
R1	248	LCD row driver output

Notes

1.If the on-chip oscillator is used, this input must be connected to VDD1.

2.If the internal VLCD generation is used, VLCDOUT, VLCDIN and VLCDSENSE must be connected together.

3.If an external VLCD is used in the application, then pin VLCDOUT must be left open circuit, otherwise the chip will be damaged.

4.If only the internal Power-on reset is used, this input must be connected to VDD1.

5.VDD1 is for the logic supply, VDD2, and VDD3 are for the voltage multiplier. For split power supplies, VDD2 and VDD3 must be connected together. If only one supply voltage is available, VDD1, VDD2 and VDD3 must be connected together.

6.Serial data acknowledge for the I2C-bus. By connecting SDACK to SDA externally, the SDA line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDACK pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that the PCF8531 will not be able to create a valid logic 0 level during the acknowledge cycle. By splitting the SDA input from the SDACK output, the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level.

7.If ENR is connected to VSS, Power-on reset is disabled; to enable Power-on reset ENR should be connected to VDD1.

8.In the application, this input must be connected to VSS.

9.VSS1 and VSS2 must be connected together.

10.In the application, T2 must be left open circuit.

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Philips Semiconductors	Product specification
34 × 128 pixel matrix driver	PCF8531

8 FUNCTIONAL DESCRIPTION

8.1Oscillator

The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD. An external clock signal, if used, is connected to this input.

8.2Power-on reset

The on-chip Power-on reset initializes the chip after Power-on or power failure.

8.3I2C-bus controller

The I2C-bus controller receives and executes the commands. The PCF8531 acts as an I2C-bus slave receiver and therefore cannot control bus communication.

8.4Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.

8.5Display data RAM

The PCF8531 contains a 34 × 128 bits static RAM, which stores the display data. The RAM is divided into 6 banks of 128 bytes (6 × 8 × 128 bits). Bank 6 is used for icon data. During RAM access, data is transferred to the RAM via the I2C-bus interface. There is a direct correspondence between the X address and column output number.

8.6Timing generator

The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses.

8.7Address counter

The address counter sets the addresses of the display data RAM for writing.

8.8Display address counter

The display address counter generates the addresses for read out of the display data.

8.9Command decoder

The command decoder identifies command words that arrive on the I2C-bus and determines the destination for the following data bytes.

8.10Bias voltage generator

The bias voltage generator generates four buffered intermediate bias voltages. This block contains the generator for the reference voltages and the four buffers. This block can operate in two voltage ranges:

∙Normal mode; 4.0 to 9.0 V

∙Power save mode; 3.0 to 9.0 V.

8.11VLCD generator

The VLCD voltage generator contains a configurable 2 to 5 times voltage multiplier; this is software programmable.

8.12Reset

The PCF8531 has the possibility of two reset modes, internal Power-on reset or external reset (RES). The reset mode is selected using the ENR signal. After a reset, the chip has the following state:

∙All row and column outputs are set to VSS (display off)

∙RAM data is undefined

∙Power-down mode.

8.13Power-down

During power-down, all static currents are switched off (no internal oscillator, no timing and no LCD segment drive system), and all LCD outputs are internally connected to VSS. The I2C-bus function remains operational.

8.14Column driver outputs

The LCD drive section includes 128 column outputs (C0 to C127) which should be connected directly to the LCD. The column output signals are generated in

accordance with the multiplexed row signals and with the data in the display latch. When less than 128 columns are required, the unused column outputs should be left open circuit.

8.15Row driver outputs

The LCD drive section includes 34 row outputs

(R0 to R33), which should be connected directly to the LCD. The row output signals are generated in accordance with the selected LCD drive mode. If less than 34 rows or lower Mux rates are required, the unused outputs must be left open circuit. The row signals are interlaced i.e. the selection order is R0, R2, ..., R1, R3 etc.

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Philips Semiconductors	Product specification
34 × 128 pixel matrix driver	PCF8531
8.16 LCD waveforms and DDRAM to data mapping
The LCD waveforms and the DDRAM to display data mapping are shown in Figs 2, 3 and 4.

ROW 0

R0 (t)

VLCD

V2

V3

V4

V5

VSS

ROW 2

R2 (t)

VLCD

V2

V3

V4

V5

VSS

COL 0

C0 (t)

VLCD

V2

V3

V4

V5

VSS

COL 1

C1 (t)

VLCD

V2

V3

V4

V5

VSS

VLCD

V3 − VSS

VLCD − V2

Vstate1(t) 0 V V3 − V2

VLCD

V3 − VSS

VLCD − V2

Vstate2(t) 0 V V3 − V2

frame n

frame n + 1

Vstate1(t)

Vstate2(t)

V4 − V5 0 V

VSS − V5

V4 − VLCD −VLCD

V4 − V5 0 V

VSS − V5

V4 − VLCD −VLCD

0 2 4 6 8...

... 32 1 3 5 7...

... 33 0 2 4 6 8...

... 32 1 3 5 7...

... 33

MGS466

Vstate1(t) = C1(t) − R0(t).

Vstate2(t) = C1(t) − R2(t).

Fig.2 Typical LCD driver waveforms.

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Philips Semiconductors	Product specification
34 × 128 pixel matrix driver	PCF8531

VLCD V2 V3

ROW 0 to 32

V4

V5

VSS

VLCD V2 V3

ROW 33

V4

V5

VSS

VLCD V2 V3

COL 1 on/off

V4

V5

VSS

VLCD V2 V3

COL 2 off/on

V4

V5

VSS

VLCD V2 V3

COL 3 on/on

V4

V5

VSS

VLCD V2 V3

COL 4 off/off

V4

V5

VSS

frame n frame n + 1

only icons are driven

MGS467

Fig.3 Icon mode; Mux 1 : 2 LCD waveforms.

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Philips Semiconductors	Product specification
34 × 128 pixel matrix driver	PCF8531

DDRAM

bank 0

top of LCD

R0

bank 1

R8

bank 2

R16

LCD

bank 3

R24

bank 4

R32

R33 (icon row)

bank 5

MGS468

Fig.4 DDRAM to display mapping.

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Philips Semiconductors	Product specification
34 × 128 pixel matrix driver	PCF8531

8.17Addressing

Data is written in bytes into the RAM matrix of the PCF8531 as illustrated in Figs 5, 6 and 7. The display RAM has a matrix of 34 × 128 bits. The columns are addressed by the address pointer. The address ranges are X 0 to X 127 (7FH) and Y 0 to Y 5 (5H). Addresses outside of these ranges are not allowed. In vertical addressing mode (V = 1), the Y address increments after each byte (see Fig.6). After the last Y address (Y = 4),

Y wraps around to 0 and X increments to address the next

column. In horizontal addressing mode (V = 0), the

Xaddress increments after each byte (see Fig.7). After the last X address (X = 127), X wraps around to 0 and

Yincrements to address the next row. After the very last address (X = 127 and Y = 4), the address pointers wrap around to address (X = 0 and Y = 0). It should be noted that in bank 4 only the LSB (DB0) of the data will be written into the RAM. The Y address 5 is reserved for icon data and is not affected by the addressing mode; it should be noted that in bank 5 only the 5th data bit (DB4) will be written into the RAM.

LSB
MSB																																				0
																																				1
LSB
																																				2
																																				Y address
MSB																																				3
																																				4
LSB
										icon data																										5
MSB													0							X address							127									MGS469

Fig.5 RAM format and addressing.

0		5										0
												1
1		6
												2
2														Y address
												3
3											638
												4
4											639	5
0		1					icon data
0						X address					127			MGS470

Fig.6 Sequence of writing data bytes into RAM with vertical addressing (V = 1).

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Philips Semiconductors	Product specification
34 × 128 pixel matrix driver	PCF8531

0		1	2								127	0
128		129	130								255	1
256		257	258								383	2
													Y address
384		385	386								511
												3
512		513	514								639	4
													5
0		1					icon data
0						X address					127		MGS471

Fig.7 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).

8.18Instructions

Only two PCF8531 registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the MPU. Before internal operation, control information is stored temporarily in these registers to allow interfacing to various types of MPUs which operate at different speeds or to allow interfacing to peripheral control ICs.

The PCF8531 operation is controlled by the instructions given in Table 1. Details are explained in subsequent sections.

Instructions are of four types:

1.Those that define PCF8531 functions such as display configuration, etc.

2.Those that set internal RAM addresses

3.Those that perform data transfer with internal RAM

4.Others.

In normal use, category 3 instructions are used most frequently. Automatic incrementing by 1 of internal RAM addresses after each data write reduces the MPU program load.

8.18.1RESET

After reset or internal Power-on reset (depending on application), the LCD driver will be set to the following state:

∙Power-down mode (PD = 1)

∙Horizontal addressing (V = 0)

∙Display blank (D = 0; E = 0), no icon mode (IM = 0)

∙Address counter X[6:0] = 0; Y[2:0] = 0

∙Bias system BS[2:0] = 0

∙Multiplex rate M[1:0] = 0 (Mux rate 1 : 17)

∙Temperature control mode TC[2:0] = 0

∙HV-gen control, HVE = 0 the HV generator is switched off, PRS = 0 and S[1:0] = 0

∙VLCD = 0 V

∙RAM data is undefined

∙Command page definition H[1:0] = 0.

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Philips Semiconductors	Product specification
34 × 128 pixel matrix driver	PCF8531

8.18.2FUNCTION SET

8.18.2.1PD

When PD = 1, the Power-down mode of the LCD driver is active:

·All LCD outputs at VSS (display off)

·Power-on reset detection active, oscillator off

·VLCD can be disconnected

·I2C-bus is operational, commands can be executed

·RAM contents not cleared; RAM data can be written

·Register settings remain unchanged.

8.18.2.2V

When V = 0 the horizontal addressing is selected. The data is written into the DDRAM as shown in Fig.7.

When V = 1 the vertical addressing is selected. The data is written into the DDRAM as shown in Fig.6. Icon data is written independently of V when Y address is 5.

8.18.3SET Y ADDRESS

8.18.4SET X ADDRESS

The X address points to the columns. The range of X is 0 to 127 (7FH).

8.18.5SET MULTIPLEX RATE

M[1:0] selects the multiplex rate (see Table 8).

8.18.6DISPLAY CONTROL (D, E AND IM)

Bits D and E select the display mode (see Table 6). Bit IM sets the display to icon mode.

8.18.7SET BIAS SYSTEM

Different multiplex rates require different bias settings. These are programmed by BS[2:0], which sets the binary number n. The optimum value for n is given by

n = Mux rate –3

Supported values of n are given in Table 2. Table 3 shows the intermediate bias voltages.

Bits Y2, Y1 and Y0 define the Y address vector of the display RAM.

Table 1 Y address
Y2	Y1	Y0	BANK
0	0	0	0
0	0	1	1
0	1	0	2
0	1	1	3
1	0	0	4
1	0	1	5 (icons)
Table 2 Programming the required bias system
BS[2]	BS[1]	BS[0]	n	BIAS SYSTEM	COMMENT
0	0	0	7	1¤11
0	0	1	6	1¤10
0	1	0	5	1¤9
0	1	1	4	1¤8
1	0	0	3	1¤7	recommended for 1 : 34
1	0	1	2	1¤6	recommended for 1 : 26
1	1	0	1	1¤5	recommended for 1 : 17
1	1	1	0	1¤4	recommended for icon mode

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Philips Semiconductors	Product specification
34 × 128 pixel matrix driver	PCF8531

8.18.8LCD BIAS VOLTAGE

Table 3 Intermediate LCD bias voltages

	SYMBOL			BIAS		EXAMPLE FOR
		VOLTAGES						1¤7 BIAS
V1		VLCD				VLCD
V2		n +	3			6¤	7	´ V
				´ V				LCD
		------------			LCD
		n +	4
V3		n +	2			5¤	7	´ V
				´ V				LCD
		------------			LCD
		n +	4
V4		2				2¤	7	´ V
				´ V				LCD
		------------			LCD
		n +	4
V5		1				1¤	7	´ V
				´ V				LCD
		------------			LCD
		n +	4
V6		VSS				VSS

8.18.9SET VOP VALUE:

The operating voltage VLCD can be set by software.

The voltage at reference temperature [VLCD (T = Tcut)] can be calculated as: VLCD (Tcut) = (a + VOP ´ b).

The generated voltage is dependent on the temperature, programmed Temperature Coefficient (TC) and the programmed voltage at reference temperature (Tcut). VLCD = VLCD (Tcut) ´ [1 + TC ´ (T - Tcut)].

The parameter values are given in Table 4.

Two overlapping VLCD ranges can be selected via the command ‘HV-gen control’ (see Table 4 and Fig.8).

The maximum voltage that can be generated depends on the VDD2 and VDD3 voltages and the display load current. For Mux 1 : 34, the optimum operating voltage of the liquid can be calculated as:

VLCD	=	1 +			34		´ Vth	= 5.30 ´ Vth
		---------------------------------------	æ			1
		2 ´		1	–		ö
	----------		è			34ø

Where Vth is the threshold voltage of the liquid crystal material used.

The practical value for VOP is determined by equating

Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately

10% contrast.

As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user has to ensure, while setting the VOP register and selecting the temperature compensation, that the VLCD limit of maximum 9 V will never be exceeded under all conditions and including all tolerances.

Table 4 Parameter values for the HV generator programming

SYMBOL		VALUE		UNIT
	PRS = 0		PRS = 1
Tcut	27		27	°C
a	2.94		6.75	V
b	0.03		0.03	V
Programming range	2.94 to 6.75		6.75 to 10.56	V

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