Philips pcd5093 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

PCD5093

DECT baseband controller

Objective speciﬁcation File under Integrated Circuits, IC17

1997 Jul 21

Philips Semiconductors Objective speciﬁcation

DECT baseband controller PCD5093

1 FEATURES

1.1 DSP software features 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING INFORMATION

5.1 Pinning

5.2 Pin description 6 FUNCTIONAL DESCRIPTION 7 PACKAGE OUTLINE 8 SOLDERING

8.1 Introduction

8.2 Reflow soldering

8.3 Wave soldering

8.4 Repairing soldered joints 9 DEFINITIONS 10 LIFE SUPPORT APPLICATIONS 11 PURCHASE OF PHILIPS I2C COMPONENTS

1997 Jul 21 2

Philips Semiconductors Objective speciﬁcation

DECT baseband controller PCD5093

1 FEATURES

• 80C51 ports P0, P1, P2 and P3 available for interfacing to display, keyboard, I2C-bus, interrupt sources and/or external memory. Integrated 64 kbyte ROM, 3 kbytes of data memory and 1 kbyte SDR-RAM. External program memory is addressable up to 128 kbytes

• +2.7 to +5 V port (P0 to P3) interface

• TDMA frame (de)multiplexing. Transmission or

reception can be programmed for any slot

• Ciphering, scrambling, CRC checking/generation and protected B-fields

• Speech and data buffering space for six handsets

• Local call and B-field loop-back

• Two interrupt lines for BML and DSP to interrupt 80C51

• On-chip, three-channel time-multiplexed 8-bit

Analog-to-Digital Converter (ADC) for RSSI measurement, one for battery voltage measurement and one channel available for other purposes

• On-chip 8-bit Digital-to-Analog Converter (DAC) for electronic potentiometer function

• Phase error measurement and phase error correction by hardware

• DACs and ADCs for dynamic earpiece and dynamic or electret microphone

• On-chip reference voltage

• On-chip supply for electret microphone

• Very low ohmic buzzer output

• Serial interface to external ADPCM CODEC (PCD5032)

or 8 kHz u-law samples

• Speech switch for Digital Telephone Answering Machine (DTAM) connected to SPI interface

• IOM-2 interface (Siemens registered trademark)

• Serial interface to synthesizer for frequency

programming

• Programmable polarity and timing of radio-control signals

• GMSK pulse shaper

• Easy interfacing with radio circuits, operating at other

supply voltages (RF supply pin with level shifter for RF signals)

• On-chip comparator for use as data-slicer

• Low power oscillator with integrated frequency

adjustment

• QFP100 package

• Power-on-reset

• Low supply voltage (2.7 to 3.6 V)

• CMOS technology.

1.1 DSP software features

• ADPCM encoding and decoding complying with G.721

• Up to two A-law channels

• Network echo suppressor

• Support of local corded handset with handsfree feature

• Speech filters

• Programmable gain in speech paths

• Side tone and soft mute

• Ringer and tone (DTMF) generator

• Automatic gain control

• Direct connection to universal codec PCD5096

• Conference between IOM-2 buffer(s) and two handsets.

For each DSP software version a separate manual is available in which detailed information is provided on how parameters must be set. For further information please contact Philips Semiconductors.

2 GENERAL DESCRIPTION

The PCD5093 is designed as GAP-compliant basestation chip for ISDN or n lines (PCD5096) business systems. It has an embedded 80C51 microcontroller with twice the performance of the classic architecture, 64 kbytes of PROM program memory and 3 kbytes of data memory on chip. In addition there is 1 kbyte of on-chip data memory that is shared with on-chip Burst Mode Logic (BML) and DSP, the System Data RAM (SDR).

3 ORDERING INFORMATION

TYPE

NUMBER

PCD5093H QFP100 plastic quad ﬂat package; 100 leads (lead length 1.95 mm);

1997 Jul 21 3

NAME DESCRIPTION VERSION

body 14 × 20 × 2.8 mm

PACKAGE

SOT317-2

Philips Semiconductors Objective speciﬁcation

DECT baseband controller PCD5093

4 BLOCK DIAGRAM

digital pins

analog pins

TST1

TST2

CLK3

DCK

BZP

BZM

EARP

FS1

EARM

LIFP

LIFM

MICP

MICM

VMIC

ref

VANLI

RSSI_AN

VBAT

3 ×

DD5V

DDA

SSA

2 ×

DD3V

5 ×

DD_RF

PORT 3.7

PORT 3.0 to

PORT 2.7

PORT 2.0 to

8 8 8

PORT 1.7

PORT 1.0 to

PORT 0.7

PORT 0.0 to

PORT 3

PORT 1 PORT 2

PORT 0

PCD5093

IB-BUS

80CL51- CORE

(TCB)

TEST CONTROL BLOCK

C-BUS

(256 BYTES)

MICROCONTROLLER-RAM

AUX-RAM

(3 kBYTES)

ROM

(64 kBYTES)

(SPI)

IOM/ADPCM

SPEECH INTERFACE

(ABB)

BUZZER BUFFER

MICROCONTROLLER

INTERFACE (ABCIF)

AB-MICROCONTROLLER

DD_RF

ref

PEAK-HOLD

3 : 1

MUX

ANALOG

SOURCE

VOLTAGE

(AVR)

REFERENCE

(DCA)

ANALOG

(IBC)

RESET

(TICB)

WATCHDOG

XTAL

(CLG)

SUBTRACT

ADC

(AVS)

(POR)

POWER-ON-RESET

(RGE)

GENERATOR

(WDT)

TIMER

(XOSC)

OSCILLATOR

ARA

ARF

ARD

1-BIT ADC

DDA

108f

(DNS)

NOISE

DIGITAL

LEVEL

SHIFTER

SHAPER

BURST

DIGITAL

MODE

LOGIC

(DSP)

SIGNAL

PROCESSOR

RAM

DATA

SYSTEM

(BML)

DIGITAL

AMP

Σ ∆

ATS

1-BIT ADC

108f

(DDF)

FILTER

DECIMATING

(SDR)

(1 kBYTE)

CDC-on

DDA

CODEC

AGM

AUXILIARY ADC (AAD)

DDA

DIGITAL

CONTROL

ISB BUS

CONTROLLER

BLOCK

TIMING CONTROL

CLOCK

GENERATOR

ref

ANALOG VOLTAGE

MBH941

VANLO

EN_WATCHDOG RESET_OUT M_RESET VBGP

SSO

DDO

handbook, full pagewidth

Fig.1 Block diagram.

PSE

ALE

A16

R_PWR

R_ENABLE

SLICE_CTR

REF_CLK

S_ENABLE

SYNTH_LOCK

S_CLK

S_DATA

S_PWR

VCO_BND_SW

1997 Jul 21 4

ANT_SW1

ANT_SW0

T_ENABLE

T_DATA

R_DATAP

R_DATAM

T_PWR_RMP

R_SLICED

T_GMSK

GP_CLK7

DPLL_DATA

XTAL1

XTAL2

CLK100

Philips Semiconductors Objective speciﬁcation

DECT baseband controller PCD5093

5 PINNING INFORMATION

5.1 Pinning

handbook, full pagewidth

T_ENABLE

T_PWR_RMP

VCO_BND_SW

SYNTH_LOCK

S_ENABLE

SLICE_CTR

R_ENABLE

ANT_SW1 ANT_SW0

CLK100

T_DATA

T_GMSK

S_DATA

S_CLK

S_PWR

REF_CLK

SS1

DD_RF

DD3V_1

R_PWR

R_DATAP

R_DATAM

RSSI_AN

VANLI

VBAT

CLK3

DCK

FS1

RESET_OUT

M_RESET

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

99989796959493929190898887868584838281

100

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

20 21 22 23 24 25 26 27

28 29 30

P0.6

P0.7

PCD5093

DD5V_3VSS5

ALE

PSE

P2.7

P2.6

P2.5

P2.4

P2.3

TST2

TST1

V V

A16

76 75

P2.2 P2.1

P2.0

P3.7

72 71

P3.6 P3.5

P3.4

P3.3

68 67

P3.2 P3.1

P3.0

BZP

BZM

60 59

P1.7 P1.6

P1.5

P1.4

56 55

P1.3 V

R_SLICED

DPLL_DATA

GP_CLK7

SS4 DD5V_2

SS3 SS2

DD3V_2

DD5V_1

31323334353637383940414243444546474849

XTAL2

XTAL1

SSO

VANLO

DDO

LIFM

LIFP

SSA

MICM

Fig.2 Pin configuration (QFP100).

1997 Jul 21 5

MICP

VMIC

MBH940

ref

DDA

VBGP

EARM

P1.0

EARP

EN_WATCHDOG

P1.1

P1.2

+ 11 hidden pages

Philips pcd5093 DATASHEETS

CONTENTS

1 FEATURES

1.1 DSP software features

2 GENERAL DESCRIPTION

3 ORDERING INFORMATION

4 BLOCK DIAGRAM

5 PINNING INFORMATION

5.1 Pinning