Philips PCD50922H, PCD50912H Datasheet

DATA SH EET
Objective specification File under Integrated Circuits, IC17
1998 Apr 27
INTEGRATED CIRCUITS
PCD509x2/zuu/v family
Low cost; low power DECT baseband controllers (ABC-PRO)
1998 Apr 27 2
Philips Semiconductors Objective specification
Low cost; low power DECT baseband controllers (ABC-PRO)
PCD509x2/zuu/v family
CONTENTS
1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING INFORMATION
5.1 Pinning
5.2 Pin description 6 FUNCTIONAL DESCRIPTION
6.1 DECT baseband controller system 7 PACKAGE OUTLINES 8 SOLDERING
8.1 Introduction
8.2 Reflow soldering
8.3 Wave soldering
8.4 Repairing soldered joints 9 DEFINITIONS 10 LIFE SUPPORT APPLICATIONS 11 PURCHASE OF PHILIPS I2C COMPONENTS
1998 Apr 27 3
Philips Semiconductors Objective specification
Low cost; low power DECT baseband controllers (ABC-PRO)
PCD509x2/zuu/v family
1 FEATURES
The PCD50912 is designed for GAP compatible DECT handsets
The PCD50922 is designed for GAP compatible DECT base stations serving up to six handsets
Fully static 80C51 microcontroller
Emulation supported for 80C51 program development
Four 8-bit ports (P0, P1, P2 and P3), 32 I/O lines
Dedicated port pins for keyboard, I2C-bus, interrupt
sources and/or external memory
Fifteen interrupt sources (including those from TICB, BML and DSP) with two priority levels
I
2
C-bus interface
UART with IrDA-compatible Data Transmission Mode
256 bytes of microcontroller main RAM
3 kbytes of microcontroller AUX RAM
1 kbyte of shared System Data RAM
64 kbytes of mask programmable ROM
128 kbyte address space for external ROM access,
maximum 192 kbytes together with internal ROM
128 kbytes of external RAM addressable
Embedded DSP with 6.912, 13.824 or 27.648 Mips
Speech and IOM-2 interface
BML for TDMA frame (de)multiplexing. Transmission or
reception can be programmed for any slot
Ciphering, scrambling, CRC checking/generation, protected B-fields
Local call and B-field loop-back
Automatic receiver delay adjustment programmable per
slot to correct for terminal mobility
Phase error measurement and phase error correction by hardware
Serial interface to synthesizer for frequency programming
Programmable timing and polarity of radio-control signals
Easy interfacing with radio circuits, operating at different supply voltages
GMSK pulse shaper with two different pulse shapes (BT = 0.5 and BT = 0.8)
Comparator for use as bit-slicer
3 channel time-multiplexed 8-bit ADC for RSSI, battery
and general input voltage measurement
Battery management supported by programmable current source for temperature or charge current measurement
On-chip 8-bit DAC for various purposes
Low power crystal oscillator at 13.824 MHz
Programmable on-chip capacitors for frequency
adjustment to 13.824 MHz with large pulling range
High performance DAC and ADC for dynamic earpiece and dynamic or electret microphone
Analog-to-digital path switchable sensitivity for microphone or line interface input
On-chip reference voltage and supply for electret microphone
Very low ohmic buzzer output
Pulse density modulated or pulse width modulated
buzzer output signal
Power-on-reset
Low power operation optimized for 2 battery cells in
handset
Long standby time due to reduced digital supply voltage and reduced activity in idle-locked mode
Flexible supply voltage concept due to use of level shifters between each supply voltage domain
Eight independent supply voltage domains: – 1.8 to 3.6 V for digital core, microcontroller ports P0
and P2, and also P1 and P3 – 1.8 to 3.6 V for buzzer, oscillator and battery – 2.7 to 3.6 V for RF interface and analog circuits
CMOS technology
Small and flat LQFP80 package.
1998 Apr 27 4
Philips Semiconductors Objective specification
Low cost; low power DECT baseband controllers (ABC-PRO)
PCD509x2/zuu/v family
2 GENERAL DESCRIPTION
The PCD509x2 family is designed for low power GAP compatible DECT handset (PP) and base station (FP) applications. The circuit includes the audio interface, the DSP, the microcontroller and the Burst Mode Logic, and contains all functionality to convert speech and data signals from/to the analog side (microphone and earpiece or line interface circuit) to/from the radio side (1.152 Mbits/s data).
This circuit is a member of the ABC family, where A stands for ‘ADPCM codec’, B for ‘Burst Mode Logic’ and C for ‘microController’. The name ABC-PRO stands for PROfessional ABC.
The PCD509x2/zuu/v contains on-chip ROM for the embedded DSP code and on-chip ROM for the embedded microcontroller code. It is these ROM codes that differentiate between various chip derivatives. For each DSP code a separate DSP user manual is published. Please contact Philips Semiconductors for more information.
This family specification contains the hardware description that is independent of the used ROM codes.
The numerical digit ‘x’ in PCD509x2 determines the intended application area (e.g. PCD50912 for use in handsets or PCD50922 for use in simple base stations, etc.). The last numerical digit ‘2’ is used to denote hardware derivatives. The extension digits ‘z’ (A to Z) and ‘uu’ (00 to 99) denote the DSP and the microcontroller software version, respectively. The extension ‘v’ denotes the hardware version updates of the circuit.
Although the microcontroller ROM code is present on-chip, an external program memory for the microcontroller code can be used. This is not the case for the DSP ROM code which is fixed by the chip version.
Throughout this family specification the term PCD509x2 is used to cover all sub types and versions. If any specific feature or parameter is connected to a certain sub type or version this will be specifically written. Until otherwise stated this family specification is valid for hardware version 1 (v = 1).
3 ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
PCD50912H LQFP80 plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm SOT315-1 PCD50922H
1998 Apr 27 5
Philips Semiconductors Objective specification
Low cost; low power DECT baseband
controllers (ABC-PRO)
PCD509x2/zuu/v family
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4 BLOCK DIAGRAM
o
k, full pagewidth
MGM858
R_DATAM
R_DATAP
REF_CLK
SLICE_CTR
R_PWR
R_ENABLE
S_PWR
S_CLK
S_DATA
S_ENABLE
GPP
T_PWR
T_ENABLE
ANT_SW1
ANT_SW0
LEVEL
SHIFTER
AGM
BURST MODE LOGIC
(BML)
CLOCK
GENERATOR
(CLG)
TIMING
CONTROL
BLOCK
(TICB)
WATCHDOG
TIMER
(WDT)
ISB
RESET
GENERATOR
(RGE)
DIGITAL
CONTROL
OF
ANALOG
(DCA)
80CL51 CORE
ROM
(64 kBYTES)
AB-MICROCONTROLLER
INTERFACE (ABCIF)
LEVEL SHIFTER
PORT 0
8
8 8 8
LEVEL SHIFTER
PORT 2
LEVEL SHIFTER
PORT 1
LEVEL SHIFTER
PORT 3
AUX-RAM
(3 kBYTES)
MICROCONTROLLER-RAM
(256 BYTES)
I2C-BUS UART
SYSTEM
DATA
RAM
(SDR)
(1 kBYTE)
DIGITAL SIGNAL
PROCESSOR
(DSP)
MEMORY
DIGITAL
DECIMATING
FILTER
(DDF)
DIGITAL
NOISE
SHAPER
(DNS)
DIGITAL
PULSE
SHAPER
(DPS)
DIGITAL
PULSE
SHAPER
(DPS)
LEVEL
SHIFTER
DIGITAL
RECEIVE
FILTER
(DRF)
ANALOG VOLTAGE
REFERENCE
(AVR)
POWER-ON-RESET
(POR)
ANALOG
VOLTAGE
SOURCE
(AVS)
AUXILIARY
ADC
(AAD)
Σ ∆
1-BIT ADC
ATS
1-BIT DAC (ARD)
AMP
V
ref
BUZZER BUFFER
(ABB)
CODEC
V
DDD
V
DDD
V
DDD
V
DD(BZ)
V
DDD
V
DDA
V
DD(RF)
V
DDD
ALE A16
V
DD(OSC)
V
DDD
V
DD(BAT)
V
DDA
T_GSMK/
T_DATA
XTAL1
XTAL2
M_RESET
VBGP
VANLO
MICM/LIFP
MICP/LIFM
EARM
EARP
BZM
BZP
ANALOG SWITCH (ASW)
V
ref
ANALOG SUBTRACTOR (ASU)
V
DD(BAT)
ANALOG RSSI TREATMENT (ART)
RSSI_AN
ADJUSTABLE CURRENT SOURCE (ACS)
VANLI
V
DDD
P0 P2 P3
(1)
P1
(1)
V
DDD
V
DD(P0, P2)
V
DD(P1, P3)
MICROCONTROLLER
PCD509x2
IB BUS
LEVEL
SHIFTER
EA
PSEN
digital pins
supply pins
analog pins
V
SSD
V
DD(P1, P3)
V
DD(P0, P2)
V
SS(P0, P2)
V
DD(BZ)
V
SS(BZ)
V
DD(RF)
V
SS(RF)
V
DDA
V
SSA
V
DD(OSC)
V
SS(OSC)
V
DD(BAT)
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
LEVEL
SHIFTER
SPEECH
INTERFACE
IOM
ADPCM
(SPI)
ISB BUS
CONTROLLER
(IBC)
Fig.1 Block diagram.
(1) Ports 1 and 3 are shared with alternative functions.
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