Philips pca9504a DATASHEETS

INTEGRATED CIRCUITS

PCA9504A

Glue chip 4

Product specification Supersedes data of 2000 Jul 25

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2000 Aug 16

Philips Semiconductors Product specification

PCA9504AGlue chip 4

FEA TURES

•Dual, Strapping, Selectable Feature Sets

•Audio-disable Circuit

•Mute Audio Circuit

•5 V reference generation

•5 V standby reference generation

•HD single color LED driver

•IDE reset signal generation/PCIRST# buffers

•PWROK (PWRGD_3V) signal generation

•Power Sequencing / BACKFEED_CUT

•Power Supply turn on circuitry

•RMSRST# generation

•Voltage translation for DDC to VGA monitor

•HSYNCH / VSYNCH voltage translation to VGA monitor

•Tri-state buffers for test

•Extra GP Logic gates

•Power LED Drivers

•Flash FLUSH# / INIT# circuit

DESCRIPTION

The Glue 4 is a combinational part, integrating miscellaneous logic functions into a single chip.

The Glue 4 has two V pins. There are two sets of I has a Strap Selection pin used to select from FLUSH mode or General-Purpose mode.

Design optimized for the Intel 82801BA I/O controller hub (ICH2).

references (3 V and 5 V) and three Ground

CC

2

C interface pins (3 V and 5 V). The part

PIN CONFIGURATION

1 V_5P0_STBY V_3P3_STBY

GPO_FLUSH_CACHE/GP1_IN

A20M/GP1_INB

INIT/GP1_INA

FLUSH_OUT_CPU/GP1_OUT

INIT_OUT/GP2_OUT

SEL_33_66

AUD_EN

AUD_RST

IDE_RSTDRV

3V_DDCSCL 5V_DDCSCL 3V_DDCSDA

CPU_PRESENT

HD_LED

2

3

4

5

6

7

8

9

CLK_IN

10 11

GND

12 45 13 14 15 16 17 18 39 19 38 20 21 22

SLP_S3

23

PS_ON

24 25 32 26 31 FLUSH_OUT_FWHSCSI 27 30 LATCHED_BACKFED_CUTSECONDARY_HD 28 29BACKFEED_CUT GND

56VREF3IN

GP3_OUT

55

GP3_IN

54

STRAP

53

VCCP_VREF

52

VSYNC_5V

51

HSYNC_5V

50

VSYNC_3V HSYNC_3V

49 48

REF5V_STBY

47

AUD_SHDN

46

MUTE_AUD VREF5INPCIRST REF5V

44PCRIST_OUT

GND

43 42

RSMRST TEST_EN

41 40

GRN_LED YLW_LED YLW_BLNK GRN_BLNK

375V_DDCSDA 36

SLP_S5

35

SCK_BJT_GATE

34

PWRGD_3V

33

FPRST PWRGD_PSPRIMARY_HD

SW00578

ORDERING INFORMA TION

PACKAGE TEMPERATURE RANGE ORDER CODE DRAWING NUMBER

56-Pin Plastic TSSOP 0°C to +70°C PCA9504ADGG SOT364-1

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Philips Semiconductors Product specification

PCA9504AGlue chip 4

PIN DESCRIPTION

PIN(S) SYMBOL FUNCTION

1 3I VREF3IN 3.3 V input 2 P V_5P0_STBY 5 V system standby power supply 3 P V_3P3_STBY 3 V system standby power supply 4 3IU GPO_FLUSH_CACHE / GP2_IN GPO from SIO / ICH2 / Buffer 2 input 5 REF A20M / GP1_INB A20M signal from ICH2 / NAND 1 input B 6 REF INIT / GP1_INA INIT signal from the ICH2 / Buffer 1 input A 7 5V OD FLUSH_OUT_CPU / GP1_OUT Open drain signal, goes to the CPU / NAND 1 output 8 5V OD INIT_OUT / GP2_OUT Delayed INIT signal into the CPU / Buffer 2 output 9 3I CLK_IN Either 33MHz or 66MHz clock, based on SEL_33_66 pin 10 3IU SEL_33_66 Strapping option for 33MHz or 66MHz CLK_IN 11, 29, 43 G GND Ground 12 3I PCRIST PCI reset signal 13 3O PCRIST_OUT Copy of PCRIST, increased drive-strength 14 3IU AUD_EN Audio enable input (GPO from ICH2 / SIO) 15 3O AUD_RST Audio reset output 16 5O IDE_RSTDRV IDE reset output, 5 V push/pull 17 3IOD 3V_DDCSCL DDCSCL input/output 3.3 V side 18 5IOD 5V_DDCSCL DDCSCL input/output 5 V side 19 3IOD 3V_DDCSDA DDCSDA input/output 3.3 V side 20 5IOD 5V_DDCSDA DDCSDA input/output 5 V side 21 3IU CPU_PRESENT CPU present signal from the processor 22 3I SLP_S3 Signal from ICH2 for transitioning to the S3 power state 23 5V OD PS_ON Power supply turn-on signal 24 5V OD HD_LED Hard drive front panel LED output 25 5IU PRIMARY_HD IDE primary drive active input 26 5IU SCSI SCSI drive active input 27 5IU SECONDARY_HD IDE secondary drive active input 28 5V OD BACKFEED_CUT Signal used for STR circuitry 30 5O LATCHED_BACKFEED_CUT Signal used for STR circuitry 31 5V OD FLUSH_OUT_FWH Open drain signal, goes to the FWH 32 5IU PWRGD_PS Power good signal from power supply 33 5IU FPRST Reset signal from the front panel 34 3O PWRGD_3V 3.3 V power good output 35 5V OD SCK_BJT_GATE Gate signal from the SCK BJT in suspend to RAM 36 3I SLP_S5 Signal from the ICH2 for transitioning to the S5 power state 37 3IU GRN_BLNK Power LED input, from SIO GPIO 38 3IU YLW_BLNK Power LED input, from SIO GPIO 39 5V OD YLW_LED Power LED output 40 5V OD GRN_LED Power LED output 41 5ID TEST_EN Test enable, 100K internal pull-down to GND 42 3O RSMRST Reset for the ICH2 resume well 44 AO REF5V Highest system supply reference voltage 45 5I VREF5IN 5V system primary supply input 46 3IU MUTE_AUD Signal from SIO to mute audio on power up/down 47 5O AUD_SHDN Signal to audio amp to signal shutdown 48 AO REF5V_STBY Highest system standby voltage 49 3I HSYNC_3V HSYNCH input from chipset video

2000 Aug 16

3

Philips Semiconductors Product specification

PCA9504AGlue chip 4

PIN DESCRIPTION CONTINUED

PIN(S) SYMBOL FUNCTION

50 3I VSYNC_3V VSYNCH input from chipset video 51 5O HSYNC_5V HSYNCH output to monitor 52 5O VSYNC_5V VSYNCH output to monitor 53 AI V

54 3IV/3O STRAP Strapping option for GP or FLUSH mode 55 5I GP3_IN Generic logic gate 3 input 56 5V OD GP3_OUT Generic logic gate 3 output

TYPE DESCRIPTION

3I 3.3 V input signal 3IU 3.3 V input signal with internal pull-up 5I 5 V input signal 5IU 5 V input signal with internal pull-up 5ID 5 V input signal with internal pull-down P Power (input) G Ground (input) 3O 3.3 V output signal 5O 5 V output signal 3V OD 3.3 V open-drain output signal 5V OD 5 v open-drain output signal AO Analog output AI Analog input 3IOD 3.3 V input/output open-drain 5IOD 5 V input/output open-drain REFL Input voltage levels referenced to V

_VREF Analog voltage reference for determining INIT/A20M input thresh-

CCP

_VREF

olds

FUNCTION TABLES

Strapping Selection Pin

STRAP (pin 54) MODE

0 FLUSH GPO_FLUSH_CACHE (4) 0 FLUSH A20M (5) 0 FLUSH INIT (6) 0 FLUSH FLUSH_OUT_CPU (7) 0 FLUSH INIT_OUT (8) 1 GP GP2_IN (4) 1 GP GP1_INB (5) 1 GP GP1_INA (6) 1 GP GP1_OUT (7) 1 GP GP2_OUT (8)

NOTE:

1. The pin is internally pulled up to default to FLUSH mode.

2000 Aug 16

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4

PIN NAME & (PIN NUMBER)

Philips Semiconductors Product specification

SYMBOL

PARAMETER

CONDITION

UNIT

SYMBOL

PARAMETER

CONDITIONS

UNIT

PCA9504AGlue chip 4

ABSOLUTE MAXIMUM RATINGS

1

LIMITS

MIN MAX

V_5P0_STBY DC 5.0V supply –0.5 +6.0 V V_3P3_STBY DC 3.3V supply –0.5 +6.0 V V

I (5V)

V

O (5V)

V

I (3.3V)

V

O (3.3V)

DC input voltage (5 V pins) Note 2 –0.5 V_5P0_STBY+0.5 V Output voltage range (5 V pins) Note 2 –0.5 V_5P0_STBY+0.5 V DC input voltage (3.3 V pins) Note 2 –0.5 V_3P3_STBY+0.5 V

Output voltage range (3.3 V pins) Note 2 –0.5 V_3P3_STBY+0.5 V SPD Supply power dissipation 100 MW ESD Static Discharge voltage 2000 V T T

STG OTR

Storage temperature range –55 +150 °C

Operating Temperature Range 0 70 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated under “recommended operating condition” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage rating may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

LIMITS

MIN MAX

V

DD3

V

DDL

V

I

V

O

T

A

DC 3.3 V supply voltage 3.0 3.6 V DC 2.5 V supply voltage 4.75 5.25 V DC input voltage 0 V

DC output voltage 0

V V

DD3 DDL DD3

V V

Operating ambient temperature range in free air 0 +70 °C

2000 Aug 16

5

Philips Semiconductors Product specification

PCA9504AGlue chip 4

DC CHARACTERISTICS

V_5P0_STBY = 5V ± 5%; V_3P3_STBY = 3.3V ± 10%

LIMITS

SYMBOL PARAMETER TEST CONDITION

MIN TYP MAX

STRAP

V

IH

V

IL

I

IH

V

OL

V

OH

I

IL

HIGH level input voltage 2.0 V LOW level input voltage 0.8 V Input leakage high –1 1 µA LOW level output voltage IOL = 6 mA 0.4 V HIGH level output voltage IOH = –3 mA 2.4 V Input leakage low –88 –26 µA

AUD_EN

V

IH

V

IL

I

IL

I

IH

HIGH level input voltage 2.0 V LOW level input voltage 0.8 V Input leakage high VIL = 0 V –88 –26 µA Input leakage low –1 1 µA

PCIRST

V

IH

V

IL

I

L

HIGH level input voltage 2.2 V LOW level input voltage 0.8 V Input leakage –1 1 µA

Hys Input hysteresis 400 mV

MUTE_AUD

V

IH

V

IL

I

IH

I

IL

HIGH level input voltage 2.2 V LOW level input voltage 0.8 V Input leakage high –1 1 µA Input leakage low VIL = 0 V –88 –26 µA

VREF5IN

V

IH

V

IL

I

L

HIGH level input voltage

LOW level input voltage Input leakage –1 1 µA

0.85*V5P 0_STBY

VREF3IN

V

IH

V

IL

I

L

HIGH level input voltage 2.2 V LOW level input voltage 0.8 V Input leakage –1 1 µA

PRIMARY_HD

V

IH

V

IL

HIGH level input voltage 0.7*5VSB V

LOW level input voltage 0.2*5VSB V Hys Input hysteresis 400 mV I

IL

I

IH

Input leakage low V

Input leakage high VIH = 5VSB –1 1 µA

= 0 V –88 –26 µA

IL

SECONDARY_HD

V

IH

V

IL

HIGH level input voltage 0.7*5VSB V

LOW level input voltage 0.2*5VSB V Hys Input hysteresis 400 mV I

IL

Input leakage low VIL = 0 V –88 –26 µA

TA = 0°C to +70°C

V

0.2*V5P 0_STBY

UNIT

V

2000 Aug 16

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Philips Semiconductors Product specification

PCA9504AGlue chip 4

LIMITS

SYMBOL UNITTA = 0°C to +70°CTEST CONDITIONPARAMETER

SYMBOL UNIT

I

IH

Input leakage high VIH = 5VSB –1 1 µA

SCSI

V

IH

V

IL

HIGH level input voltage 0.7*5VSB V

LOW level input voltage 0.2*5VSB V Hys Input hysteresis 400 mV I

IL

I

IH

Input leakage low VIL = 0 V –88 –26 µA

Input leakage high VIH = 5VSB –1 1 µA

FPRST

V

IH

V

IL

HIGH level input voltage 0.7*5VSB V

LOW level input voltage 0.2*5VSB V Hys Input hysteresis 400 mV I

IL

I

IH

Input leakage low VIL = 0 V –88 –26 µA

Input leakage high VIH = 5VSB –1 1 µA

PWRGD_PS

V

IH

V

IL

HIGH level input voltage 0.7*5VSB V

LOW level input voltage 0.2*5VSB V Hys Input hysteresis 400 mV I

IL

I

IH

Input leakage low VIL = 0 V –88 –26 µA

Input leakage high VIH = 5VSB –1 1 µA

GPO_FLUSH_CACHE/GP2_IN

V

IH

V

IL

I

L

I

IH

HIGH level input voltage 2.2 V

LOW level input voltage 0.8 V

Input leakage VIL = 0 V –88 –26 µA

Input leakage VIH = 5 V –1 1 µA

INIT / GP1_INA (GP Mode)

V

IH

V

IL

I

L

VCCP_V

HIGH level input voltage Part is strapped for GP

LOW level input voltage Part is strapped for GP

Input leakage Part is strapped for GP

Bias voltage GP mode 1.95 2.1 V

ref

INIT / GP1_INA (Flush Mode)

V

IH

V

IL

I

IL

VCCP_V

HIGH level input voltage FLUSH mode 1.5 V

LOW level input voltage FLUSH mode 0.4 V

Input leakage FLUSH mode –1 1 µA

Bias voltage FLUSH mode 0.95 1.1 V

ref

TEST CONDITIONPARAMETER

mode

MAXTYPMIN

2.4 V

0.8 V

–1 1 µA

2000 Aug 16

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Philips Semiconductors Product specification

PCA9504AGlue chip 4

LIMITS

SYMBOL UNITTA = 0°C to +70°CTEST CONDITIONPARAMETER

SYMBOL UNIT

A20M / GP1_INB

V

IH

V

IL

I

IL

VCCP_V V

IH

V

IL

I

L

VCCP_V

HIGH level input voltage FLUSH mode 1.5 V

LOW level input voltage FLUSH mode 0.4 V

Input leakage FLUSH mode –1 1 µA

Bias voltage FLUSH mode 0.95 1.1 V

ref

HIGH level input voltage GP mode 2.4 V

LOW level input voltage GP mode 0.8 V

Input leakage GP mode –1 1 µA

Bias voltage GP mode 1.95 2.1 V

ref

CLK_IN

V

IH

V

IL

HIGH level input voltage 2.2 V

LOW level input voltage 0.8 V Hys Input hysteresis 250 mV I

L

Input leakage –1 1 µA

SEL_33_66

V

IH

V

IL

HIGH level input voltage 2.0 V

LOW level input voltage 0.8 V Hys Input hysteresis 400 mV I

IH

I

IL

Input leakage –1 1 µA

Input leakage VIL = 0 V –88 –26 µA

SLP_S3

V

IH

V

IL

HIGH level input voltage 2.2 V

LOW level input voltage 0.8 V Hys Input hysteresis 400 mV I

L

Input leakage –1 1 µA

SLP_S5

V

IH

V

IL

HIGH level input voltage 2.2 V

LOW level input voltage 0.8 V Hys Input hysteresis 400 mV I

L

Input leakage –1 1 µA

CPU_PRESENT

V

IH

V

IL

HIGH level input voltage 2.0 V

LOW level input voltage 0.8 V Hys Input hysteresis 400 mV I

IH

I

IL

Input leakage VIH = 3VSB –1 1 µA

Input leakage VIL = 0 V –88 –26 µA

TEST_EN

V

IH

V

IL

HIGH level input voltage 0.7*5VSB V

LOW level input voltage 0.2*5VSB V Hys Input hysteresis 400 mV I

IH

I

IL

Input leakage VIL = 0 V –1 1 µA

Input leakage VIH = 5VSB 20 88 µA

TEST CONDITIONPARAMETER

MAXTYPMIN

2000 Aug 16

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Philips Semiconductors Product specification

PCA9504AGlue chip 4

LIMITS

SYMBOL UNITTA = 0°C to +70°CTEST CONDITIONPARAMETER

SYMBOL UNIT

HSYNC_3V

V

IH

V

IL

I

L

HIGH level input voltage 2.2 V

LOW level input voltage 0.8 V

Input leakage –1 1 µA

VSYNC_3V

V

IH

V

IL

I

L

HIGH level input voltage 2.2 V

LOW level input voltage 0.8 V

Input leakage –1 1 µA

GRN_BLNK

V

IH

V

IL

I

IH

I

IL

HIGH level input voltage 2.2 V

LOW level input voltage 0.8 V

Input leakage –1 1 µA

Input leakage VIL = 0 V –88 –26 µA

YLW_BLNK

V

IH

V

IL

I

IH

I

IL

HIGH level input voltage 2.0 V

LOW level input voltage 0.8 V

Input leakage –1 1 µA

Input leakage VIL = 0 V –88 –26 µA

GP3_IN

V

IH

V

IL

I

L

HIGH level input voltage 2.2 V

LOW level input voltage 0.8 V

Input leakage –1 1 µA

AUD_RST

V

OL

V

OH

I

OZ

LOW level output voltage IOL = 6 mA 0.4 V

HIGH level output voltage IOH = –3 mA 2.4 V

Off state output current –1 1 µA

AUD_SHDN

V

OL

V

OH

I

OZ

LOW level output voltage IOL = 6 mA 0.4 V

HIGH level output voltage IOH = –6 mA 2.4 V

Off state output current –1 1 µA

REF5V

V

OUT5

V

OUT3

I

OUTL

LOW level output voltage V

HIGH level output voltage V

Off state output current –20 20 µA

REF5V_STBY

V

OUT5

V

OUT3

I

OUTL

LOW level output voltage V_5P0_STBY > 1.5 V V_5P0_STBY – 0.05 V_5P0_STBY + 0.05 V

HIGH level output voltage V_5P0_STBY > 1.5 V V_5P0_STBY – 0.05 V_5P0_STBY + 0.05 V

Off state output current –20 20 µA

HD_LED

V

OL

I

OZ

LOW level output voltage IOL = 12 mA 0.4 V

Off state output current –1 1 µA

TEST CONDITIONPARAMETER

> 1.5 V V

REF5in

> 1.5 V V

REF3in

– 0.05 V

REF5in

– 0.05 V

REF3in

MAXTYPMIN

+ 0.05 V

REF5in

+ 0.05 V

REF3in

2000 Aug 16

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