Philips PCA8581CT-F6, PCA8581T-F6, PCA8581T-F6L, PCF8581CT-F4 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

PCA8581; PCA8581C

128 × 8-bit EEPROM with I2C-bus interface

Product specification

1997 Apr 02

Supersedes data of 1996 Aug 19

File under Integrated Circuits, IC12

Philips Semiconductors	Product specification
128 × 8-bit EEPROM with I2C-bus interface	PCA8581; PCA8581C

CONTENTS

1FEATURES

2GENERAL DESCRIPTION

3QUICK REFERENCE DATA

4ORDERING INFORMATION

5BLOCK DIAGRAM

6PINNING

7CHARACTERISTICS OF THE I2C-BUS

7.1Bit transfer

7.2Start and stop conditions

7.3System configuration

7.4Acknowledge

7.5I2C-bus protocol

8LIMITING VALUES

9HANDLING

10DC CHARACTERISTICS

11AC CHARACTERISTICS

12APPLICATION INFORMATION

12.2Application example

12.2Slave address

12.3Diode protection

13PACKAGE OUTLINES

14SOLDERING

14.1Introduction

14.2DIP

14.2.1Soldering by dipping or by wave

14.2.2Repairing soldered joints

14.3SO

14.3.1Reflow soldering

14.3.2Wave soldering

14.3.3Repairing soldered joints

15DEFINITIONS

16LIFE SUPPORT APPLICATIONS

17PURCHASE OF PHILIPS I2C COMPONENTS

1997 Apr 02	2

Philips Semiconductors	Product specification
128 × 8-bit EEPROM with I2C-bus interface	PCA8581; PCA8581C

1 FEATURES

∙Operating supply voltage:

–4.5 to 5.5 V (PCA8581)

–2.5 to 6.0 V (PCA8581C)

∙Integrated voltage multiplier and timer for writing (no external components required)

∙Automatic erase before write

∙Low standby current; maximum 10 μA

∙8-byte page write mode

∙Serial input/output bus (I2C-bus)

∙Address by 3 hardware address pins

∙Automatic word address incrementing

∙Designed for minimum 10000 write cycles per byte

∙10 years minimum non-volatile data retention

∙Infinite number of read cycles

∙Pin and address compatibility to PCF8570C and PCF8582

∙Operating ambient temperature: −25 to +85 °C.

3 QUICK REFERENCE DATA

2 GENERAL DESCRIPTION

The PCA8581 and PCA8581C are low power CMOS EEPROMs with standard and wide operating voltages:

4.5 to 5.5 V (PCA8581)

2.5 to 6.0 V (PCA8581C).

In the following text, the generic term ‘PCA8581’ is used to refer to both types in all packages except when otherwise specified.

The PCA8581 is organized as 128 words of 8-bytes.

Addresses and data are transferred serially via a two-line bidirectional bus (I2C-bus). The built-in word address register is incremented automatically after each written or read data byte. All bytes can be read in a single operation. Up to 8 bytes can be written in one operation, reducing the total write time per byte. Three address pins, A0, A1 and A2 are used to define the hardware address, allowing the use of up to 8 devices connected to the bus without additional hardware.

SYMBOL		PARAMETER		CONDITIONS	MIN.	MAX.	UNIT
VDD	supply voltage
	PCA8581				4.5	5.5	V
	PCA8581C				2.5	6.0	V
IDD	supply current (standby)			fSCL = 0 Hz	−	10	μA
Tamb	operating ambient temperature				−25	+85	°C
Tstg	storage temperature			without EEPROM retention	−65	+150	°C
				with EEPROM retention	−65	+85	°C
4 ORDERING INFORMATION
TYPE				PACKAGE
NUMBER	NAME			DESCRIPTION		VERSION
PCA8581P	DIP8		plastic dual in-line package; 8 leads (300 mil)			SOT97-1
PCA8581CP	DIP8		plastic dual in-line package; 8 leads (300 mil)			SOT97-1
PCA8581T	SO8		plastic small outline package; 8 leads; body width 3.9 mm			SOT96-1
PCA8581CT	SO8		plastic small outline package; 8 leads; body width 3.9 mm			SOT96-1

1997 Apr 02

3

Philips Semiconductors	Product specification
128 × 8-bit EEPROM with I2C-bus interface	PCA8581; PCA8581C

5 BLOCK DIAGRAM

handbook, full pagewidth
		TIMER		VOLTAGE
				MULTIPLIER
	PCA8581
	PCA8581C
		WORD		ROW	MEMORY
		ADDRESS			CELL
			7	SELECT
		REGISTER			ARRAY
1
A0
2
A1
3
A2
6
SCL	INPUT	I2C BUS		COLUMN	MULTIPLEXER
5	FILTER	CONTROL		SELECT
SDA
8	POWER	SHIFT	8		R/W
		REGISTER			CONTROL
	ON
VDD
	RESET
4
VSS
7
TEST
					MLB887

			Fig.1	Block diagram.
6 PINNING
SYMBOL		PIN	DESCRIPTION
A0		1	hardware address input 0			fpage				V
A1		2	hardware address input 1			A0	1		8
										DD
A2		3	hardware address input 2			A1	2	PCA8581	7	TEST
VSS		4	negative supply			A2	3	PCA8581C	6	SCL
SDA		5	serial data input/output			VSS	4		5	SDA
SCL		6	serial clock input
								MLB888
TEST		7	test output can be connected to VSS, VDD or left
			open-circuit			Fig.2		Pin configuration.
VDD		8	positive supply

1997 Apr 02

4

Philips Semiconductors	Product specification
128 × 8-bit EEPROM with I2C-bus interface	PCA8581; PCA8581C

7 CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.

7.1Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the

HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal.

SDA

SCL

data line		change
stable;		of data
data valid		allowed		MBA607

Fig.3 Bit transfer.

7.2Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P).

SDA

SDA

SCL

S

P

SCL

START condition

STOP condition

MBA608

Fig.4 Definition of START and STOP conditions.

1997 Apr 02

5

Philips Semiconductors	Product specification
128 × 8-bit EEPROM with I2C-bus interface	PCA8581; PCA8581C

7.3System configuration

A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.

SDA

SCL

MASTER		SLAVE		SLAVE		MASTER		MASTER
TRANSMITTER /				TRANSMITTER /				TRANSMITTER /
		RECEIVER				TRANSMITTER
RECEIVER				RECEIVER				RECEIVER

MBA605

Fig.5 System configuration.

7.4Acknowledge

The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

handbook, full pagewidth		START				clock pulse for
		condition				acknowledgement
	SCL FROM
			1	2	8	9
	MASTER

DATA OUTPUT

BY TRANSMITTER

S

DATA OUTPUT

BY RECEIVER

MBA606 - 1

Fig.6 Acknowledgement on the I2C-bus.

1997 Apr 02

6