Philips PCA8550PW, PCA8550D, PCA8550DB Datasheet

INTEGRATED CIRCUITS

PCA8550

4-bit multiplexed/1-bit latched 5-bit I2C EEPROM

Product specification

1998 Sep 29

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Philips Semiconductors	Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM	PCA8550

FEATURES

•4-bit 2-to-1 multiplexer, 1-bit latch

•5-bit internal non-volatile register

•Override input forces all outputs to logic 0

•Internal non-volatile register write/readable via I2C bus

•Write-protect pin enables/disables I2C writes to register

•2.5V multiplexed outputs

•3.3V non-multiplexed output (latched)

•5V tolerant inputs

•Useful for 'jumperless' configuration of PC motherboards

•Designed for use in Pentium Pro/Pentium II systems

Pentium II is a registered trademark of Intel Corporation

DESCRIPTION

The primary function of the 4-bit 2-to-1 I2C multiplexer is to select either a 4-bit input or data from a non-volatile register and drive this value onto the output pins. One additional non-multiplexed register output is also provided. The non-multiplexed output is latched to prevent output value changes during I2C writes to the non-volatile register. A write protect input is provided to enable/disable the ability to write to the non-volatile register. An ``overrideº input feature forces all outputs to logic 0.

ORDERING INFORMATION

PIN CONFIGURATION

I2C SCL					VCC
		1		16
I2C SDA		2		15	WP
					NON_MUXED_OUT
OVERRIDE#		3		14
MUX_IN A					MUX_SELECT
		4		13
MUX_IN B					MUX_OUT A
		5		12
MUX_IN C		6		11	MUX_OUT B
MUX_IN D					MUX_OUT C
		7		10
GND 8					MUX_OUT D
				9
			SW00216

PACKAGES	TEMPERATURE RANGE	OUTSIDE NORTH AMERICA	NORTH AMERICA	DRAWING NUMBER
16-Pin Plastic SO	0°C to +70°C	PCA8550D	PCA8550D	SOT109-1
16-Pin Plastic SSOP	0°C to +70°C	PCA8550DB	PCA8550DB	SOT338-1
16-Pin Plastic TSSOP	0°C to +70°C	PCA8550PW	PCA8550PW DH	SOT403-1

FUNCTIONAL DESCRIPTION

When the MUX_SELECT signal is logic 0, the multiplexer will select the data from the non-volatile register to drive on the MUX_OUT pins. When the MUX_SELECT signal is logic 1, the multiplexer will select the MUX_IN lines to drive on the MUX_OUT pins. The

MUX_SELECT signal is also used to latch the NON_MUXED_OUT signal which outputs data from the non-volatile register. The

NON_MUXED_OUT signal latch is transparent when MUX_SELECT is in a logic 0 state, and will latch data when MUX_SELECT is in a logic 1 state. When the active-LOW OVERRIDE# signal is set to logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will be driven to logic 0. This information is summarized in Table 1.

The write protect (WP) input is used to control the ability to write the contents of the 5-bit non-volatile register. If the WP signal is logic 0, the I2C bus will be able to write the contents of the non-volatile register. If the WP signal is logic 1, data will not be allowed to be written into the non-volatile register.

The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I2C bus (described in the next section).

The OVERRIDE#, WP, MUX_IN, and MUX_SELECT signals have internal pullup resistors. See the DC and AC Characteristics for hysteresis and signal spike suppression figures.

1998 Sep 29

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853-2015 20105

Philips Semiconductors	Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM	PCA8550

PIN DESCRIPTION

	PIN	SYMBOL	FUNCTION
	NUMBER
	1	I2C SCL	I2C bus clock
	2	I2C SDA	Bi-directional I2C bus data
	3	OVERRIDE#	Forces all outputs to logic 0
	4	MUX_IN A
	5	MUX_IN B

External inputs to multiplexer

6MUX_IN C

7MUX_IN D

8	GND	Common ground voltage rail
9	MUX_OUT D
10	MUX_OUT C	2.5V multiplexed output

11MUX_OUT B

12MUX_OUT A

			Selects MUX_IN inputs or
	13	MUX_SELECT	register contents for
			MUX_OUT outputs
	14	NON_MUXED_OUT	TTL-level output from
			non-volatile memory
	15	WP	Non-volatile register
			write-protect
	16	VCC	Positive voltage rail

FUNCTION TABLE

Table 1. Function table

	OVERRIDE	MUX_SELECT	MUX_OUT	NON_MUXED_OUT
	#		OUTPUTS	OUTPUT
	0	0	All 0's	All 0's
	0	1	MUX_IN	Latched
			inputs	NON_MUXED_OUT1
			From non-	From non-volatile
	1	0	volatile
				register
			register
	1	1	MUX_IN	From non-volatile
			inputs	register

NOTE

1.Latched NON_MIXED_OUT state will be the value present on the NON_MUXED_OUT output at the time of the MUX_SELECT input transitioned from a logic 0 to a logic 1 state.

I2C Interface

Communicating with this device is initiated by sending a valid address on the I2C bus. The address format (see FIgure 1) is a fixed unique 7-bit value followed by a 1-bit read/write value which determines the direction of the data transfer.

	MSB							LSB
	1	0	0	1	1	1	0	R/W#
								SW00218

Figure 1. I2C Address Byte

Following the address and acknowledge bit are 8 data bits which, depending on the read/write bit in the address, will read data from or write data to the non-volatile register. Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be read from the register if the bit is logic 1. The three high-order bits (see FIgure 2) are logic 0. The next bit is data which is non-multiplexed. The low four bits are the data which will be multiplexed. A write with any of the first three bits non-zero will be aborted.

NOTE:

1.To ensure data integrity, the non-volatile register must be internally write protected when VCC to the I2C bus is powered down or VCC to the component is dropped below normal operating levels.

1998 Sep 29

3

Philips Semiconductors	Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM	PCA8550

	MSB							LSB
				NON-	MUX	MUX	MUX	MUX
	0	0	0	MUXED
					DATA D	DATA C	DATA B	DATA A
				DATA

SW00219

Figure 2. I2C Data Byte

BLOCK DIAGRAM

			10±30k Ω
	13	CRESET#
		MUX_SELECT
	3	OVERRIDE#
				5-BIT EEPROM
	VCC3.3 = 16				LATCH
		GND = 8					SELECT	14
			100±150k Ω		NMO		NON_MUX_OUT
			I
			2
		SCL	C		0
	1		iNTERFACE
		I2C CLOCK
CHIP	2	SDA
		I2C DATA	LOGIC
SET					3.3V	2.5V	A20M#	12
				4			MUX_OUT A
			10±30k Ω	-
				-2 BIT			/FSBM0
		WRITE			3.3V	2.5V	IGNNE#
	15		OE#	1-to				11
		PROTECT					MUX_OUT B
				MULTIPLEXER					PENTIUM PRO/
							/FSBM1
	4	A20M#			3.3V	2.5V	LINT0/INTR	10	PENTIUM II
		MUX_IN A					MUX_OUT C		PROCESSORS
	5	IGNNE#					/FSBM2
		MUX_IN B
					3.3V	2.5V	LINT1/NMI
								9
	6	LINT0/INTR					MUX_OUT D
		MUX_IN C					/FSBM3
	7	LINT1/NMI			1
		MUX_IN D	10±30k Ω
									SW00347
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