Philips PCA8514P, PCA8514T Datasheet

INTEGRATED CIRCUITS

DATA SH EET

PCA8514

Stand-alone OSD

Product speciﬁcation File under Integrated Circuits, IC14

1995 Nov 27

Philips Semiconductors Product speciﬁcation

Stand-alone OSD PCA8514

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING INFORMATION

5.1 Pinning

5.2 Pin description 6 SERIAL I/O

6.1 I2C-bus serial interface

6.2 High-speed serial interface (HIO) 7 CHARACTER FONTS

7.1 Character font address map

7.2 Character font ROM 8 DISPLAY RAM ORGANIZATION

8.1 Description of display RAM codes

8.2 Loading character data into display RAM

8.3 Writing character data to display RAM 9 COMMANDS

9.1 Command 0

9.2 Command 1

9.3 Command 2

9.4 Command 3

9.5 Command 4

9.6 Command 5

9.7 Command 6

9.8 Command 7

9.9 Command 8

9.10 Command 9

9.11 Command A

9.12 Commands B, C and D

9.13 Command E

9.14 Command F

9.15 Command G

10 MISCELLANEOUS

10.1 Space and Carriage Return Codes in different Background/Shadowing modes

10.2 Combination of character font cells

11 OSD CLOCK 12 OSD CLOCK SELECTION FOR DIFFERENT

TV STANDARDS

12.1 OSD frequency

12.2 Maximum number of characters per row

12.3 Maximum number of rows per frame

13 OUTPUT PORTS

13.1 Mask options

14 DEFAULT VALUES AFTER

POWER-ON-RESET

15 LIMITING VALUES 16 DC CHARACTERISTICS 17 AC CHARACTERISTICS 18 PACKAGE OUTLINES 19 SOLDERING

19.1 Introduction

19.2 DIP

19.3 SO

20 DEFINITIONS 21 LIFE SUPPORT APPLICATIONS 22 PURCHASE OF PHILIPS I2C COMPONENTS

1995 Nov 27 2

Philips Semiconductors Product speciﬁcation

Stand-alone OSD PCA8514

1 FEATURES

• Display RAM: 256 × 12 bits

• Display character fonts: 128 (fixed in ROM, mask

programmable)

• Starting position of the first character displayed: 64 vertical and 64 horizontal starting positions can be selected by software

• Character size: 4 different character sizes on a line-by-line basis (1 dot = 1H/1V; 2H/2V; 3H/3V and 4H/4V)

• Character matrix: 12 × 18 with no spacing between characters and no rounding function

• Foreground colours: 16 combinations of Red, Green, Blue and Intensity on character-by-character basis

• Background/shadowing modes: 4 modes available, No background, Box shadowing, North-West shadowing and Frame shadowing (raster blanking) on frame basis

• Background colours: 16 combinations of Red, Green, Blue and Intensity on word-by-word basis. Available when background mode is in either the Box shadowing, North-West shadowing or Frame shadowing mode

• OSD oscillator: on-chip Phase-Locked Loop (PLL)

• Character blinking ratio: 1 : 1, 1 : 3 and 3 : 1

(programmable frequency of f

) on character basis

VSYNC

⁄16,1⁄32,1⁄64or 1⁄

128

• Display format: flexible display format by using the Carriage Return Code, maximum number of characters per line is also flexible and depends upon the OSD clock frequency

• Spacing between lines: 4 choices comprising 0, 4, 8 and 12 horizontal scan lines

• Display character RAM address auto-post-increment when writing data

• Fast I

C-bus serial interface (400 kbaud) or High-speed 3-wire serial interface (1 Mbaud) for data/command transfer

• ACM (Active Character Monitor) specifically for use in camcorder applications on word basis; can also be used as a 5th colour control with R, G, B and I signals

• Programmable active input polarity of HSYNC and VSYNC

• Programmable output polarity of R, G, B, I and FB

• Supply voltage: 5 V ±10%

• Operating temperature: −20 to +70 °C

• Package: SDIP24 or SO24.

2 GENERAL DESCRIPTION

The PCA8514 is a member of the PCA85XX CMOS family and is an on-screen character display generator controlled by a microcontroller via the on-chip fast I

C-bus interface or the on-chip High-speed 3-wire serial interface. It is suitable for use in high-end TV or camcorder applications and has also been designed for use in conventional mid-end TV with advanced graphic features.

3 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

PCA8514P SDIP24 plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1 PCA8514T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

1995 Nov 27 3

Philips Semiconductors Product speciﬁcation

Stand-alone OSD PCA8514

4 BLOCK DIAGRAM

handbook, full pagewidth

P00 3

I/O

CONTROL

RAM

DISPLAY

CHARACTER

BUFFER

ADDRESS

SELECTOR

COUNTER

WRITE ADDRESS

P01

P04/ACM (VOB2)

PORT

BUFFERS

ROM

DISPLAY

VERTICAL

POSITION

COUNTER

AVDDAV

CONTROL

SIGNALS

ACM(VOB2)

DISPLAY CONTROL

AND OUTPUT STAGE

TESTING

CIRCUITRY

CRYSTAL

OSCILLATOR

MLC347

FB(VOB)

I(VOW3)

B(VOW2)

G(VOW1)

R(VOW0)

TEST2 TI00 to TI11

TEST1

Fig.1 Block diagram.

XTAL1(IN)

XTAL2(OUT)

POSITION

COUNTER

HORIZONTAL

CONTROL

CHARACTER SIZE

BUFFER

RECEIVER

I C SLAVE

RECEIVER OR

RESET

SCL/SCLK

HIGH-SPEED I/O

HIO/ I C

SDA/SIN

DATA SWITCHING

EXTERNAL/INTERNAL

1995 Nov 27 4

DECODER

INSTRUCTION

PLL

OSCILLATOR

CIRCUIT

INTERNAL

SYNCHRONOUS

HSYNC

CSYNC

VSYNC

HSYNC

SEPARATION

VSYNC

Philips Semiconductors Product speciﬁcation

Stand-alone OSD PCA8514

5 PINNING INFORMATION

5.1 Pinning

handbook, halfpage

P04/ACM (VOB2)

XTAL2 (OUT)

I (VOW3)

TEST2 TEST1

VSYNC HSYNC

SDA/SIN SCK/SCLK XTAL1 (IN)

1 2 3 4

5 6

PCA8514

7 8

9 10 11

24 23 22 21 20 19 18 17 16 15 14 13

MGC949

Fig.2 Pin configuration for SDIP24 and SO24.

SS FB (VOB) V

B (VOW2) P01 G (VOW1) P00 R (VOW0)

HIO/I C E RESET

1995 Nov 27 5

Philips Semiconductors Product speciﬁcation

Stand-alone OSD PCA8514

5.2 Pin description Table 1 SDIP24 and SO24 packages

SYMBOL PIN I/O DESCRIPTION

I (VOW3) 1 O Character output signal for intensity control. P04/ACM (VOB2) 2 O Port 04 output or Active Character Monitor output (VOB2). TEST2 3 I Test mode selection; for normal operation TEST2 is connected to V TEST1 4 I Test mode selection; for normal operation TEST1 is connected to VSS. C 5 I/O Capacitor connection for on-chip OSD PLL oscillator. VSYNC 6 I Vertical synchronization input, active polarity programmable. HSYNC 7 I Horizontal synchronization input, active polarity programmable.

SDA/SIN 8 I/O Data line of the I

C-bus interface or the data line for the High-speed

serial interface.

SCL/SCLK 9 I/O Clock line of the I

C-bus interface or the clock line for the High-speed

serial interface. XTAL1 (IN) 10 I System clock input. XTAL2 (OUT) 11 O System clock output. V

12 I Ground, digital. RESET 13 I Master reset input (active LOW). E 14 I Chip enable (active HIGH) for the High-speed serial interface. When the

C-bus interface is selected this pin should be connected to VSS.

HIO/I2C 15 I Serial interface selection. When this pin is LOW the High-speed serial

interface is selected; when this pin is HIGH the I2C-bus interface is

selected. R (VOW0) 16 O Character output signal: VOW0 for Red. P00 17 I/O General purpose I/O Port 00. G (VOW1) 18 O Character output signal: VOW1 for Green. P01 19 I/O General purpose I/O Port 01. B (VOW2) 20 O Character output signal: VOW2 for Blue. V

21 I Power supply, digital. FB (VOB) 22 O Fast Blanking output (VOB). AV AV

SS DD

23 I Ground, analog.

24 I Power supply, analog.

SS.

1995 Nov 27 6

Philips Semiconductors Product speciﬁcation

Stand-alone OSD PCA8514

6 SERIAL I/O

The PCA8514 has two means by which it can communicate with a microcontroller: a fast I2C-bus serial interface and a High-speed serial interface. Selection of either interface is achieved via pin 15, HIO/I2C. When HIO/I2C is LOW, the HIO serial interface is selected. When HIO/I2C is HIGH, the I2C-bus serial interface is selected.

The PCA8514 is programmed by a series of commands sent via one of these interfaces. There are 16 commands; each command selecting different functions of the PCA8514. The 16 commands are described in detail in Chapter 9.

6.1 I

C-bus serial interface

The I2C-bus serial interface is selected by driving pin 15 (HIO/I2C) HIGH. Data transmission conforms to the fast I2C-bus protocol; the maximum transmission rate being 400 kHz. The PCA8514 operates in the slave receiver mode and therefore in normal operation is ‘write only’ from the master device.

The format of the data streams sent via the I2C-bus interface is shown in Fig.3. The first data byte is the slave address 1011 101Xb. The last bit of the slave address is always a logic 0, except in the Test mode when it could be a logic 1. Subsequent data bytes contain the commands for control of the device. Upon the successful reception of a complete data byte by the shift register, an Acknowledge bit is sent. A STOP condition terminates the data transfer operation.

The I2C-bus interface is reset to its initial state (waiting for a slave address call) by the following conditions:

• After a master reset

• After a bus error has been detected on the I

C-bus

interface.

Under both these conditions the data held in the shift register is abandoned.

6.1.1 M

AXIMUM SPEED OF THE I

C-BUS

The maximum I2C-bus transmission rate that the PCA8514 can receive is 400 kHz. However, if the data byte being transmitted is for display RAM then internal synchronization of the write operation from the shift register to the display RAM location is necessary. This will reduce the maximum transmission speed.

The synchronization process is carried out by on-chip hardware and takes place during the HSYNC retrace period when VSYNC is inactive. The I

C-bus clock is pulled LOW if a complete display RAM data byte is received before HSYNC becomes active. The I2C-bus clock will be released when HSYNC becomes active and then the contents of the shift register will be written into the display RAM location.

6.2 High-speed serial interface (HIO)

The High-speed serial interface is selected when pin 15

HIO/I2C) is pulled LOW. The High-speed serial interface

( has a 3-wire communication protocol; the maximum transmission rate being 1 MHz. The interface protocol is illustrated in Fig.4 and described below.

1. Pin 14 (E) the chip enable pin is driven HIGH. This

LOW-to-HIGH transition clears the shift register and resets the serial input circuit.

2. On the first HIGH-to-LOW transition of SCLK after the

interface has been enabled, the first data bit (D0) must be present at the SIN pin.

3. On the following LOW-to-HIGH transition of SCLK, the

first data bit (D0) will be latched into the shift register.

4. On the next HIGH-to-LOW transition of SCLK the

second data bit (D1) must be present at the SIN pin. Data bit (D1) will be latched into the shift register on the following LOW-to-HIGH transition of SCLK.

5. The operation specified in step 4 above is repeated

another 6 times, thus loading the shift register with a complete data byte. This data byte is then transferred to the command interpreter which takes the appropriate action.

6. Providing the chip enable signal remains HIGH, a

2nd data byte can be transferred. The 1st data bit of the next data transfer takes place on the falling edge of the SCLK signal.

The following points should be noted:

• If the chip enable signal is pulled LOW at any time the

shift operation in progress is stopped and the HIO slave receiver is disabled

• The rising edge of the chip enable signal resets the HIO

slave receiver.

1995 Nov 27 7

Philips Semiconductors Product speciﬁcation

Stand-alone OSD PCA8514

handbook, full pagewidth

I C-bus

bit stream

S Slave address Ack Ack

1st data byte

Command

LSBMSB

870870

W O

0 1 1 1 1 0 0

2nd data byte

bit 7

Fig.3 I2C-bus write timing diagram - data stream.

bit 0

870

Ack

nth data byte

807

Ack

MRA818

handbook, full pagewidth

SCLK

(from HIO master and connected to SIN pin of HIO slave)

SCLK

(1) Ts≥ 1µs; Th≥ 1 µs.

falling edge of SCLK D changes

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7OUT

rising edge of SCLK SIN sampled

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7SIN

OUT

Fig.4 High-speed I/O format.

MLB395 - 1

1995 Nov 27 8

Philips Semiconductors Product speciﬁcation

Stand-alone OSD PCA8514

7 CHARACTER FONTS

128 character fonts may be held in ROM; 125 customer selected fonts and three reserved character font codes. Customer selected fonts are mask programmable. Each character font is stored in a 12 × 19 dot matrix, as shown in Fig.5. Elements in Rows 1 to 18 can be selected as visible dots on the screen; Row 0 is used only for the combination of two characters in a vertical direction, when the North-West shadowing mode is selected (see Sections 9.9 and 10.2). Extremely high resolution can be achieved by having no spacing between characters on the same line and by programming the inter-line spacing to zero. The 12 × 18 dot matrix is suitable for the display of semigraphic patterns, Kanji, Hiragana, Katagana or even Chinese characters.

7.1 Character font address map

Figure 6 shows the character font address map in ROM and RAM. Addresses 7FH and 7EH hold the reserved codes for space and carriage return functions respectively; address 7DH is reserved for testing purposes and addresses (00H to 7CH) contain the character font codes.

7.2 Character font ROM

The file format to submit to Philips for customized character sets is also shown in Fig.7. The following points should be noted:

1. Row 0 of each font is reserved for vertical combination

of two fonts.

2. When two font cells are combined in a vertical

direction Row 0 of the lower font must contain the same bit pattern as held in Row 18 of the character above it.

3. Binary 1 denotes visual dots; binary 0 denotes a blank

space.

4. ROM1 and ROM2 data files are in INTEL hex format

on a byte basis. Each byte is structured High nibble followed by Low nibble.

5. The remaining unused 16 bytes (one character font) in

ROM1/ROM2 must be filled with FFH.

6. CS denotes Checksum. A software package (OSDGEM) that assists in the design

of character fonts on-screen and that also automatically generates the bit pattern HEX files, is available on request. The package is run under the MS-DOS environment for IBM compatible PCs.

ROM is divided into two parts: ROM1 and ROM2. The organization of the bit patterns stored in ROM1 and ROM2 is shown in Fig.7.

01234567891011

0 1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18

MLC350

reserved code

124 (7CH) 125 (7DH) 126 (7EH) 127 (7FH)

Mask Programmable Font

Test code

Carriage return code

Space code

MGC948

Fig.5 Character dot matrix organization.

1995 Nov 27 9

Fig.6 ROM address map.

Philips Semiconductors Product speciﬁcation

Stand-alone OSD PCA8514

Column

MSB

1110987 6543210

0 1 2 3 4 5 6

Row

7 8

9 10 11 12 13 14 15 16 17 18

ROM1

: 1 0 0 0 0 0 0 0 00 00 22 FC 03 22 20 F2 3F 01 20 55 0C 00 03 : 1 0 0 0 1 0 0 0 < - - - DATA FOR FONT 2 - - - >

: 1 0 0 0 2 0 0 0 < - - - DATA FOR FONT 3 - - - >

byte #

0 1 2 3 4 5 6 7 8 9 A B C D E F

__ __ __ __ __ __ __ __ __ __ __ __ __ __ __

LSB

0 0 0 3 F C 2 2 0 2 2 0 3 F C 2 2 0 2 2 0

3 F C 2 2 0 2 2 0 3 F F 0 0 1 0 0 1 5 5 3 5 5 2 0 0 6 0 0 C 0 5 8 0 3 0

ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1

ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1 ROM2 ROM1

ROM2

: 1 0 0 0 0 0 0 0 FC 03 22 20 C2 3F 20 12 00 53 65 00 58 : 1 0 0 0 1 0 0 0 < - - - DATA FOR FONT 2 - - - >

: 1 0 0 0 2 0 0 0 < - - - DATA FOR FONT 3 - - - >

ROM1 ROM2

0 0 0

2 2 0 3 F C

2 2 0 2 2 0 3 F F

0 0 1

5 5 2 0 0 C

0 3 0

F F C S F F C S

F F C S

F 0 FF FF C S F X FF FF C S

F X FF FF C S

3 F C 2 2 0

2 2 0

3 F C 2 2 0

0 0 1 5 5 3 0 0 6

0 5 8

MLB345

Fig.7 Character font pattern stored in ROM1 and ROM2.

1995 Nov 27 10

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