INTEGRATED CIRCUITS
PCA8514
Stand-alone OSD
Product specification |
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1995 Nov 27 |
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File under Integrated Circuits, IC14 |
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Philips Semiconductors |
Product specification |
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Stand-alone OSD |
PCA8514 |
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CONTENTS
1FEATURES
2GENERAL DESCRIPTION
3ORDERING INFORMATION
4BLOCK DIAGRAM
5PINNING INFORMATION
5.1Pinning
5.2Pin description
6 |
SERIAL I/O |
6.1I2C-bus serial interface
6.2High-speed serial interface (HIO)
7 |
CHARACTER FONTS |
7.1Character font address map
7.2Character font ROM
8 |
DISPLAY RAM ORGANIZATION |
8.1Description of display RAM codes
8.2Loading character data into display RAM
8.3Writing character data to display RAM
9 COMMANDS
9.1Command 0
9.2Command 1
9.3Command 2
9.4Command 3
9.5Command 4
9.6Command 5
9.7Command 6
9.8Command 7
9.9Command 8
9.10Command 9
9.11Command A
9.12Commands B, C and D
9.13Command E
9.14Command F
9.15Command G
10 MISCELLANEOUS
10.1Space and Carriage Return Codes in different Background/Shadowing modes
10.2Combination of character font cells
11OSD CLOCK
12OSD CLOCK SELECTION FOR DIFFERENT TV STANDARDS
12.1OSD frequency
12.2Maximum number of characters per row
12.3Maximum number of rows per frame
13 OUTPUT PORTS
13.1Mask options
14DEFAULT VALUES AFTER POWER-ON-RESET
15LIMITING VALUES
16DC CHARACTERISTICS
17AC CHARACTERISTICS
18PACKAGE OUTLINES
19SOLDERING
19.1Introduction
19.2DIP
19.3SO
20DEFINITIONS
21LIFE SUPPORT APPLICATIONS
22PURCHASE OF PHILIPS I2C COMPONENTS
1995 Nov 27 |
2 |
Philips Semiconductors |
Product specification |
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Stand-alone OSD |
PCA8514 |
1 FEATURES
·Display RAM: 256 ´ 12 bits
·Display character fonts: 128 (fixed in ROM, mask programmable)
·Starting position of the first character displayed:
64 vertical and 64 horizontal starting positions can be selected by software
·Character size: 4 different character sizes on a line-by-line basis (1 dot = 1H/1V; 2H/2V; 3H/3V and 4H/4V)
·Character matrix: 12 ´ 18 with no spacing between characters and no rounding function
·Foreground colours: 16 combinations of Red, Green, Blue and Intensity on character-by-character basis
·Background/shadowing modes: 4 modes available, No background, Box shadowing, North-West shadowing and Frame shadowing (raster blanking) on frame basis
·Background colours: 16 combinations of Red, Green, Blue and Intensity on word-by-word basis. Available when background mode is in either the Box shadowing, North-West shadowing or Frame shadowing mode
·OSD oscillator: on-chip Phase-Locked Loop (PLL)
·Character blinking ratio: 1 : 1, 1 : 3 and 3 : 1 (programmable frequency of 1¤16, 1¤32, 1¤64 or 1¤128 of fVSYNC) on character basis
·Display format: flexible display format by using the Carriage Return Code, maximum number of characters per line is also flexible and depends upon the OSD clock frequency
3 ORDERING INFORMATION
·Spacing between lines: 4 choices comprising 0, 4, 8 and 12 horizontal scan lines
·Display character RAM address auto-post-increment when writing data
·Fast I2C-bus serial interface (400 kbaud) or High-speed 3-wire serial interface (1 Mbaud) for data/command transfer
·ACM (Active Character Monitor) specifically for use in camcorder applications on word basis; can also be used as a 5th colour control with R, G, B and I signals
·Programmable active input polarity of HSYNC and VSYNC
·Programmable output polarity of R, G, B, I and FB
·Supply voltage: 5 V ±10%
·Operating temperature: -20 to +70 °C
·Package: SDIP24 or SO24.
2 GENERAL DESCRIPTION
The PCA8514 is a member of the PCA85XX CMOS family and is an on-screen character display generator controlled by a microcontroller via the on-chip fast I2C-bus interface or the on-chip High-speed 3-wire serial interface. It is suitable for use in high-end TV or camcorder applications and has also been designed for use in conventional mid-end TV with advanced graphic features.
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PACKAGE |
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NAME |
DESCRIPTION |
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PCA8514P |
SDIP24 |
plastic shrink dual in-line package; 24 leads (400 mil) |
SOT234-1 |
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PCA8514T |
SO24 |
plastic small outline package; 24 leads; body width 7.5 mm |
SOT137-1 |
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1995 Nov 27 |
3 |
27 Nov 1995 |
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DIAGRAM BLOCK 4 |
OSD alone-Stand |
Semiconductors Philips |
VDD |
EXTERNAL/INTERNAL |
CHARACTER SIZE |
WRITE ADDRESS |
ADDRESS |
DISPLAY |
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CONTROL |
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DATA SWITCHING |
BUFFER |
CHARACTER |
REGISTER |
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VSS |
REGISTER/ |
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COUNTER |
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BUFFER |
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SELECTOR |
RAM |
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CONTROL |
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RESET |
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I/O |
3 |
P00 |
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SCL/SCLK |
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I 2 C SLAVE |
HORIZONTAL |
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PORT |
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P01 |
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SDA/SIN |
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RECEIVER OR |
POSITION |
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DISPLAY |
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BUFFERS |
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P04/ACM (VOB2) |
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E |
HIGH-SPEED I/O |
REGISTER/ |
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ROM |
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HIO/ I2 C |
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RECEIVER |
COUNTER |
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VERTICAL |
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POSITION |
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REGISTER/ |
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4 |
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COUNTER |
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CONTROL |
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AV DD |
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INSTRUCTION |
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AV SS |
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DECODER |
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SIGNALS |
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C |
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PLL |
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OSCILLATOR |
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TESTING |
DISPLAY CONTROL |
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INTERNAL |
CRYSTAL |
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CIRCUITRY |
AND OUTPUT STAGE |
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SYNCHRONOUS |
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OSCILLATOR |
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VSYNC |
HSYNC |
CIRCUIT |
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HSYNC |
CSYNC |
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VSYNC |
SEPARATION |
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ACM(VOB2) |
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12 |
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MLC347 |
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XTAL1(IN) |
TEST1 |
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R(VOW0) |
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FB(VOB) |
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XTAL2(OUT) |
TEST2 |
TI00 to TI11 |
G(VOW1) |
I(VOW3) |
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B(VOW2) |
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Fig.1 |
Block diagram. |
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PCA8514 |
specification Product |
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Philips Semiconductors |
Product specification |
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Stand-alone OSD |
PCA8514 |
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5 PINNING INFORMATION
5.1Pinning
handbook, halfpage |
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AVDD |
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I (VOW3) |
1 |
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24 |
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P04/ACM (VOB2) |
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AVSS |
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2 |
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23 |
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TEST2 |
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FB (VOB) |
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3 |
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22 |
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VDD |
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TEST1 |
4 |
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C |
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B (VOW2) |
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5 |
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20 |
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VSYNC |
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P01 |
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6 |
PCA8514 |
19 |
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HSYNC |
7 |
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18 |
G (VOW1) |
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SDA/SIN |
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P00 |
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8 |
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17 |
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SCK/SCLK |
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R (VOW0) |
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16 |
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HIO/I2C |
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XTAL1 (IN) |
10 |
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15 |
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XTAL2 (OUT) |
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E |
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11 |
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14 |
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VSS |
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12 |
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13 |
RESET |
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MGC949 |
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Fig.2 Pin configuration for SDIP24 and SO24.
1995 Nov 27 |
5 |
Philips Semiconductors |
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Product specification |
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Stand-alone OSD |
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PCA8514 |
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5.2 Pin description |
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Table 1 SDIP24 and SO24 packages |
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SYMBOL |
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PIN |
I/O |
DESCRIPTION |
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I (VOW3) |
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1 |
O |
Character output signal for intensity control. |
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P04/ACM (VOB2) |
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2 |
O |
Port 04 output or Active Character Monitor output (VOB2). |
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TEST2 |
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3 |
I |
Test mode selection; for normal operation TEST2 is connected to VSS. |
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TEST1 |
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4 |
I |
Test mode selection; for normal operation TEST1 is connected to VSS. |
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C |
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5 |
I/O |
Capacitor connection for on-chip OSD PLL oscillator. |
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VSYNC |
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6 |
I |
Vertical synchronization input, active polarity programmable. |
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HSYNC |
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7 |
I |
Horizontal synchronization input, active polarity programmable. |
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SDA/SIN |
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8 |
I/O |
Data line of the I2C-bus interface or the data line for the High-speed |
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serial interface. |
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SCL/SCLK |
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9 |
I/O |
Clock line of the I2C-bus interface or the clock line for the High-speed |
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serial interface. |
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XTAL1 (IN) |
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10 |
I |
System clock input. |
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XTAL2 (OUT) |
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11 |
O |
System clock output. |
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VSS |
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12 |
I |
Ground, digital. |
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13 |
I |
Master reset input (active LOW). |
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RESET |
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E |
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14 |
I |
Chip enable (active HIGH) for the High-speed serial interface. When the |
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I2C-bus interface is selected this pin should be connected to V . |
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SS |
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2C |
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15 |
I |
Serial interface selection. When this pin is LOW the High-speed serial |
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HIO/I |
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interface is selected; when this pin is HIGH the I2C-bus interface is |
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selected. |
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R (VOW0) |
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16 |
O |
Character output signal: VOW0 for Red. |
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P00 |
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17 |
I/O |
General purpose I/O Port 00. |
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G (VOW1) |
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18 |
O |
Character output signal: VOW1 for Green. |
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P01 |
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19 |
I/O |
General purpose I/O Port 01. |
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B (VOW2) |
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20 |
O |
Character output signal: VOW2 for Blue. |
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VDD |
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21 |
I |
Power supply, digital. |
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FB (VOB) |
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22 |
O |
Fast Blanking output (VOB). |
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AVSS |
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23 |
I |
Ground, analog. |
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AVDD |
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24 |
I |
Power supply, analog. |
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1995 Nov 27 |
6 |
Philips Semiconductors |
Product specification |
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Stand-alone OSD |
PCA8514 |
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6 SERIAL I/O
The PCA8514 has two means by which it can communicate with a microcontroller: a fast I2C-bus serial interface and a High-speed serial interface. Selection of
either interface is achieved via pin 15, HIO/I2C. When
HIO/I2C is LOW, the HIO serial interface is selected. When
HIO/I2C is HIGH, the I2C-bus serial interface is selected.
The PCA8514 is programmed by a series of commands sent via one of these interfaces. There are 16 commands; each command selecting different functions of the PCA8514. The 16 commands are described in detail in Chapter 9.
6.1I2C-bus serial interface
The I2C-bus serial interface is selected by driving pin 15
(HIO/I2C) HIGH. Data transmission conforms to the fast I2C-bus protocol; the maximum transmission rate being 400 kHz. The PCA8514 operates in the slave receiver mode and therefore in normal operation is ‘write only’ from the master device.
The format of the data streams sent via the I2C-bus interface is shown in Fig.3. The first data byte is the slave address 1011 101Xb. The last bit of the slave address is always a logic 0, except in the Test mode when it could be a logic 1. Subsequent data bytes contain the commands for control of the device. Upon the successful reception of a complete data byte by the shift register, an Acknowledge bit is sent. A STOP condition terminates the data transfer operation.
The I2C-bus interface is reset to its initial state (waiting for a slave address call) by the following conditions:
∙After a master reset
∙After a bus error has been detected on the I2C-bus interface.
Under both these conditions the data held in the shift register is abandoned.
6.1.1MAXIMUM SPEED OF THE I2C-BUS
The maximum I2C-bus transmission rate that the PCA8514 can receive is 400 kHz. However, if the data byte being transmitted is for display RAM then internal synchronization of the write operation from the shift register to the display RAM location is necessary. This will reduce the maximum transmission speed.
The synchronization process is carried out by on-chip hardware and takes place during the HSYNC retrace period when VSYNC is inactive. The I2C-bus clock is pulled LOW if a complete display RAM data byte is received before HSYNC becomes active. The I2C-bus clock will be released when HSYNC becomes active and then the contents of the shift register will be written into the display RAM location.
6.2High-speed serial interface (HIO)
The High-speed serial interface is selected when pin 15
(HIO/I2C) is pulled LOW. The High-speed serial interface has a 3-wire communication protocol; the maximum transmission rate being 1 MHz. The interface protocol is illustrated in Fig.4 and described below.
1.Pin 14 (E) the chip enable pin is driven HIGH. This LOW-to-HIGH transition clears the shift register and resets the serial input circuit.
2.On the first HIGH-to-LOW transition of SCLK after the interface has been enabled, the first data bit (D0) must be present at the SIN pin.
3.On the following LOW-to-HIGH transition of SCLK, the first data bit (D0) will be latched into the shift register.
4.On the next HIGH-to-LOW transition of SCLK the second data bit (D1) must be present at the SIN pin. Data bit (D1) will be latched into the shift register on the following LOW-to-HIGH transition of SCLK.
5.The operation specified in step 4 above is repeated another 6 times, thus loading the shift register with a complete data byte. This data byte is then transferred to the command interpreter which takes the appropriate action.
6.Providing the chip enable signal remains HIGH, a 2nd data byte can be transferred. The 1st data bit of the next data transfer takes place on the falling edge of the SCLK signal.
The following points should be noted:
∙If the chip enable signal is pulled LOW at any time the shift operation in progress is stopped and the HIO slave receiver is disabled
∙The rising edge of the chip enable signal resets the HIO slave receiver.
1995 Nov 27 |
7 |
Philips Semiconductors |
Product specification |
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Stand-alone OSD |
PCA8514 |
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I2C-bus |
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bit stream |
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MSB |
LSB |
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0 |
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7 |
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8 |
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0 |
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7 |
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8 |
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7 |
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0 |
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8 |
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S |
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Slave address |
W |
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Ack |
0 1 1 1 1 0 0 BS |
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Ack |
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Ack |
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Ack |
P |
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1st data byte |
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2nd data byte |
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nth data byte |
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Command |
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MRA818 |
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bit 7 |
bit 0 |
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Register data |
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Fig.3 I2C-bus write timing diagram - data stream.
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falling edge of SCLK |
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DOUT |
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SCLK |
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D OUT |
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D3 |
D4 |
D5 |
D6 |
D7 |
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
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connected to SIN pin of |
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HIO slave) |
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Ts rising edge of SCLK |
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Th |
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SCLK |
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SIN |
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
MLB395 - 1
(1) Ts ³ 1 ms; Th ³ 1 ms.
Fig.4 High-speed I/O format.
1995 Nov 27 |
8 |
Philips Semiconductors |
Product specification |
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Stand-alone OSD |
PCA8514 |
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7 CHARACTER FONTS
128 character fonts may be held in ROM; 125 customer selected fonts and three reserved character font codes. Customer selected fonts are mask programmable. Each character font is stored in a 12 × 19 dot matrix, as shown in Fig.5. Elements in Rows 1 to 18 can be selected as visible dots on the screen; Row 0 is used only for the combination of two characters in a vertical direction, when the North-West shadowing mode is selected (see Sections 9.9 and 10.2). Extremely high resolution can be achieved by having no spacing between characters on the same line and by programming the inter-line spacing to zero. The 12 × 18 dot matrix is suitable for the display of semigraphic patterns, Kanji, Hiragana, Katagana or even Chinese characters.
7.1Character font address map
Figure 6 shows the character font address map in ROM and RAM. Addresses 7FH and 7EH hold the reserved codes for space and carriage return functions respectively; address 7DH is reserved for testing purposes and addresses (00H to 7CH) contain the character font codes.
7.2Character font ROM
ROM is divided into two parts: ROM1 and ROM2. The organization of the bit patterns stored in ROM1 and ROM2 is shown in Fig.7.
11 10 |
9 |
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0 |
0
1
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18
MLC350
The file format to submit to Philips for customized character sets is also shown in Fig.7. The following points should be noted:
1.Row 0 of each font is reserved for vertical combination of two fonts.
2.When two font cells are combined in a vertical direction Row 0 of the lower font must contain the same bit pattern as held in Row 18 of the character above it.
3.Binary 1 denotes visual dots; binary 0 denotes a blank space.
4.ROM1 and ROM2 data files are in INTEL hex format on a byte basis. Each byte is structured High nibble followed by Low nibble.
5.The remaining unused 16 bytes (one character font) in ROM1/ROM2 must be filled with FFH.
6.CS denotes Checksum.
A software package (OSDGEM) that assists in the design of character fonts on-screen and that also automatically generates the bit pattern HEX files, is available on request. The package is run under the MS-DOS environment for IBM compatible PCs.
0
Mask Programmable Font
reserved code
124 (7CH) |
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125 (7DH) |
Test code |
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126 |
(7EH) |
Carriage return code |
127 |
(7FH) |
Space code |
MGC948
Fig.5 Character dot matrix organization. |
Fig.6 ROM address map. |
1995 Nov 27 |
9 |
Philips Semiconductors |
Product specification |
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Stand-alone OSD |
PCA8514 |
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MSB |
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11 10 9 |
8 7 |
6 5 |
4 3 2 1 |
0 |
ROM1 ROM2
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0 0 0 |
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3 F C |
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2 2 0 |
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2 2 0 |
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3 F C |
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2 2 0 |
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2 2 0 |
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2 2 0 |
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2 2 0 |
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0 0 1 |
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0 0 1 |
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5 5 3 |
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5 5 2 |
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0 0 6 |
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0 0 C |
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C |
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0 5 8 |
ROM2 |
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0 3 0 |
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3 |
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ROM1 |
byte # |
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0 1 2 3 4 5 6 7 8 9 A B C D E F |
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__ __ |
__ __ __ __ __ __ __ __ __ __ |
__ __ __ |
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: 1 0 0 0 0 0 0 0 |
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00 00 22 FC 03 22 20 F2 3F 01 20 55 0C 00 03 |
F F |
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< - - - |
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DATA FOR FONT 2 |
- - - > |
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F F |
C S |
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: 1 0 0 0 2 0 0 0 |
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< - - - |
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DATA FOR FONT 3 |
- - - > |
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F F |
C S |
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: 1 0 0 0 0 0 0 0 |
FC |
03 |
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20 C2 3F 20 12 00 53 65 00 58 |
F 0 |
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FF FF |
C S |
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: 1 0 0 0 1 0 0 0 < - - - |
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DATA FOR FONT 2 |
- - - > |
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F X |
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FF FF |
C S |
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: 1 0 0 0 2 0 0 0 < - - - |
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DATA FOR FONT 3 |
- - - > |
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F X |
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FF FF |
C S |
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MLB345
Fig.7 Character font pattern stored in ROM1 and ROM2.
1995 Nov 27 |
10 |
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