Philips PCA84C640, PCA84C641, PCA84C644, PCA84C440, PCA84C441 Datasheet

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INTEGRATED CIRCUITS

DATA SH EET

84C44X; 84C64X; 84C84X

8-bit microcontrollers with OSD and VST

Product speciﬁcation Supersedes data of October 1994 File under Integrated Circuits, IC14

1996 Nov 29

Philips Semiconductors Product speciﬁcation

8-bit microcontrollers with OSD and VST 84C44X; 84C64X; 84C84X

CONTENTS

1 FEATURES

1.1 PCF84CXXXA kernel

1.2 Derivative features PCA84C640 2 GENERAL DESCRIPTION

2.1 Important note 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING INFORMATION 6 DIFFERENCES BETWEEN THE TYPES 7 RESET

7.1 Power-on-reset 8 ANALOG CONTROL

8.1 6-bit PWM DACs 9 VST CONTROL

9.1 14-bit PWM DAC

9.2 Coarse adjustment

9.3 Fine adjustment 10 AFC INPUT 11 INPUT/OUTPUT (I/O) 12 ON SCREEN DISPLAY

12.1 Features

12.2 Horizontal display position control

12.3 Vertical display position control

12.4 Clock generator

12.5 Display data registers

12.6 Display control registers

12.7 OSD display position

12.8 OSD character size and colour selection

12.9 Character ROM

13 EMULATION MODE 14 REGISTER MAP 15 LIMITING VALUES 16 DC CHARACTERISTICS 17 AC CHARACTERISTICS

17.1 Characteristic curves 18 PACKAGE OUTLINE 19 SOLDERING

19.1 Introduction

19.2 Soldering by dipping or by wave

19.3 Repairing soldered joints 20 DEFINITIONS 21 LIFE SUPPORT APPLICATIONS 22 PURCHASE OF PHILIPS I2C COMPONENTS

1996 Nov 29 2

Philips Semiconductors Product speciﬁcation

8-bit microcontrollers with OSD and VST 84C44X; 84C64X; 84C84X

1 FEATURES

1.1 PCF84CXXXA kernel

• 8-bit CPU, ROM, RAM, I/O in a single 42 leads shrink DIL package

• Over 80 instructions all of 1 or 2 cycles

• 29 quasi-bidirectional standard I/O port lines

• Configuration of I/O lines individually selected by mask

• External interrupt

• 2 direct testable inputs T0 and T1

• 8-bit programmable timer/event counter

• 3 single level vectored interrupts (external,

timer/counter, I2C-bus)

• Power-on-reset and low voltage detector

• Single power supply

• 2 power reduction modes: Idle and Stop

• Operating temperature range: −20 to +70 °C

• Silicon gate CMOS fabrication process (SAC2).

1.2 Derivative features PCA84C640

Although the PCA84C640 is specifically referred to throughout this data sheet, the information applies to all the devices. The small differences between the 84C640 and the other devices are specified in the text and also highlighted in Chapter 6.

The PCA84C640 comprises:

• The PCF84CXXXA processor core

• 6 kbytes mask-programmable program ROM

• 128 bytes RAM

• Multi-master I

• AFC input for Voltage Synthesized Tuning

(VST; with 3-bit DAC and comparator)

• On Screen Display (OSD) facility for two rows of 16-characters

• On Screen Display character set of 64 types

INT/T0

C-bus interface

• Four programmable display dot sizes

• Half dot character rounding

• Seven colours for each character

• One 14-bit PWM output for VST

• Five 6-bit PWM outputs for analog controls

• Eight port lines with 10 mA LED drive capability

• 18 general purpose bidirectional I/O lines

plus 11 function-combined I/O lines

• 2 direct testable lines

• Programmable VSYNCN and HSYNCN input polarity

• RC oscillator for OSD function.

2 GENERAL DESCRIPTION

The 84C44X; 84C64X; 84C84X denotes the types:

• PCA84C440; 84C441; 84C443; 84C444

• PCA84C640; 84C641; 84C643; 84C644

• PCA84C840; 84C841; 84C843; 84C844.

which are 8-bit microcontrollers with On Screen Display (OSD) and Voltage Synthesized Tuning (VST) functions. All are members of the 84CXXX microcontroller family.

There are two oscillator types for the OSD function in the various types, i.e.,

• RC oscillator: PCA84C440; 84C443; 84C640; 84C643; 84C840; 84C843

• LC oscillator: PCA84C441; 84C444; 84C641; 84C644; 84C841; 84C844.

2.1 Important note

This data sheet details the specific properties of the PCA84C44X, PCA84C64X and PCA84C84X. The shared characteristics of the PCA84CXXX family of microcontrollers are described in the PCF84CXXXA Family single-chip 8-bit Microcontroller of

IC14”

, which should be read in conjunction with this data

sheet.

“Data Handbook

3 ORDERING INFORMATION

TYPE NUMBER

PCA84C440; 84C443; 84C640; 84C643; 84C840; 84C843

PCA84C441; 84C444; 84C641; 84C644; 84C841; 84C844

1996 Nov 29 3

NAME DESCRIPTION VERSION

SDIP42

PACKAGE

plastic shrink dual in-line package; 42 leads (600 mil)

TEMPERATURE

RANGE (°C)

SOT270-1 −20 to +70

Philips Semiconductors Product speciﬁcation

8-bit microcontrollers with OSD and VST 84C44X; 84C64X; 84C84X

4 BLOCK DIAGRAM

handbook, full pagewidth

XTAL1 (IN)

XTAL2 (OUT)

RESET

TEST/EMU

(6)

8-BIT

TIMER /

EVENT

COUNTER

PARALLEL

I/O

PORTS

INT/T0

CPU

84CXXX core excluding ROM/RAM

ROM

8-BIT

I/O

PORTS

888

(1)

6-BIT

DAC

RAM

(2)

14-BIT

DAC

VOB

VOW2

VOW1

ON SCREEN DISPLAY

3-BIT DAC +

COMPARATOR

VOW3

DOSC1

DOSC2

8-bit internal bus

VSYNCN

HSYNCN

(3)

I C

INTERFACE

MCD170

P0 P1

(1) 4 kbytes for the PCA84C440; 84C441; 84C443; 84C444.

6 kbytes for the PCA84C640; 84C641; 84C643; 84C644. 8 kbytes for the PCA84C840; 84C841; 84C843; 84C844.

(2) 128 bytes for the PCA84C440; 84C441; 84C443; 84C444; 84C640; 84C641; 84C643; 84C644.

192 bytes for the PCA84C840; 84C841; 84C843; 84C844.

(3) For use with an LC oscillator, only available with the:

PCA84C441; 84C444; 84C641; 84C644; 84C841; 84C844.

C-bus interface not available with the:

(4) I

PCA84C443; 84C444; 84C643; 84C644; 84C843; 84C844. (5) DP1.4 only available for PCA84C440; 84C443; 84C640; 84C643; 84C840; 84C843. (6) T1 = pin 29 for PCA84C440; 84C443; 84C640; 84C643; 84C840; 84C843.

T1 = pin 34 for PCA84C441; 84C444; 84C641; 84C644; 84C841; 84C844.

DP0 DP1 1 2 3 4 5

(5)

PWM

Fig.1 Block diagram.

1996 Nov 29 4

TDAC AFC SDA SCL

(4)

Philips Semiconductors Product speciﬁcation

8-bit microcontrollers with OSD and VST 84C44X; 84C64X; 84C84X

5 PINNING INFORMATION

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DP0.0/TDAC DP0.1/PWM1 DP0.2/PWM2 DP0.3/PWM3 DP0.4/PWM4 DP0.5/PWM5

DP1.7/AFC

P1.0 P1.1

P1.2 P1.3 P1.4 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20 21

PCA84C440 PCA84C443 PCA84C640 PCA84C643 PCA84C840 PCA84C843

MCD172

DP1.0

DP0.6/SDA

DP0.7/SCL

DP1.1

DP1.2

DP1.3

INT/T0

DP1.4

RESET

XTAL2

XTAL1

TEST/EMU

DOSC1

VSYNCN

HSYNCN

VOB

VOW3

VOW2/DP1.5

VOW1/DP1.6

handbook, halfpage

DP0.0/TDAC DP0.1/PWM1 DP0.2/PWM2 DP0.3/PWM3 DP0.4/PWM4 DP0.5/PWM5

DP1.7/AFC

P1.0 P1.1

P1.2 P1.3 P1.4 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21

PCA84C441 PCA84C444 PCA84C641 PCA84C644 PCA84C841 PCA84C844

MCD171

DP1.0

DP0.6/SDA

DP0.7/SCL

DP1.1

DP1.2

DP1.3

36 35

INT/T0 T1

34 33

RESET

XTAL2

XTAL1

31 30

TEST/EMU DOSC2

29 28

DOSC1

VSYNCN

HSYNCN VOB

VOW3

24 23

VOW2/DP1.5 VOW1/DP1.6

Fig.2 Pinning diagram for PCA84CX40; 84CX43.

1996 Nov 29 5

Fig.3 Pinning diagram for PCA84CX41; 84CX44.

1996 Nov 29 6

Table 1 Pin description

SYMBOL

(1)

DESCRIPTION

84CX40; 84CX43 84CX41; 84CX44 84CX40; 84CX43 84CX41; 84CX44 Deviating pinning

DP1.0 to DP1.4 DP1.0 to DP1.3 41, 38, 37, 36, 34 41, 38, 37, 36 Derivative Port 1: quasi-bidirectional I/O lines. T1 T1 29 34 Direct testable pin and event counter input. DOSC1 − 28 − Connection to RC oscillator of OSD clock.

− DOSC1/DOSC2 − 28, 29 Connections to LC oscillator of OSD clock.

Mutual pinning

DP0.0/TDAC 1 Derivative Port 0: quasi-bidirectional I/O line or 14-bit DAC PWM. DP0.1 to DP0.5/PWM1 to PWM5 2 to 6 Derivative Port 1: quasi-bidirectional I/O lines or 6-bit DAC PWM. P1.0 to P1.4 7, 8, 10, 11 and 12 Port 1: quasi-bidirectional I/O lines. P0.0 to P0.7 13 to 20 Port 0: quasi-bidirectional I/O port. DP1.7/AFC 9 Derivative Port 1:

quasi-bidirectional I/O line or comparator input with 3-bit DAC.

DP0.6/SDA 40 Derivative open drain I/O port or I2C-bus data line.

DP0.7/SCL 39 Derivative open drain I/O port or I

C- bus clock line. INT/T0 35 External interrupt or direct testable line. DP1.5 and DP1.6/VOW2 and VOW1 23, 22 Derivative Port 1:

quasi-bidirectional I/O lines or character video output. RESET 33 Initialize input, active LOW. XTAL2, XTAL1 32, 31 Oscillator output or input terminal for system clock. TEST/EMU 30 Control input for testing and emulation mode. Ground for normal

operation. VSYNCN 27 Vertical synchronous signal input. HSYNCN 26 Horizontal synchronous signal input. VOB 25 Blanking output. VOW3 24 Character video output of OSD. V

21 Ground. 42 Power supply.

Philips Semiconductors Product speciﬁcation

8-bit microcontrollers with OSD and VST 84C44X; 84C64X; 84C84X

Note

1. 84CX40; 84CX43 denotes the types: PCA84C440, PCA84C443, PCA84C640, PCA84C643, PCA84C840 and PCA84C843. 84CX41; 84CX44 denotes the types: PCA84C441, PCA84C444, PCA84C641, PCA84C644, PCA84C841 and PCA84C844.

1996 Nov 29 7

Table 2 Differences between the types PCA84C44X, PCA84C64X and PCA84C84X In this table: yes = available; no = not available.

6 DIFFERENCES BETWEEN THE TYPES

Philips Semiconductors Product speciﬁcation

8-bit microcontrollers with OSD and VST 84C44X; 84C64X; 84C84X

FEATURE

OSD oscillator RC LC RC LC RC LC RC LC RC LC RC LC General purpose I/O lines 18 17 18 17 18 17 18 17 18 17 18 17

C-bus interface yes yes no no yes yes no no yes yes no no

I ROM 4 kbytes 6 kbytes 8 kbytes RAM 128 bytes 128 bytes 192 bytes

Pin assignment

Pin 29 T1 DOSC2 T1 DOSC2 T1 DOSC2 T1 DOSC2 T1 DOSC2 T1 DOSC2 Pin 34 DP1.4 T1 DP1.4 T1 DP1.4 T1 DP1.4 T1 DP1.4 T1 DP1.4 T1

Pin yes no yes no yes no yes no yes no yes no Latch yes no yes no yes no yes no yes no yes no

84C440 84C441 84C443 84C444 84C640 84C641 84C643 84C644 84C840 84C841 84C843 84C844

PCA...

Philips Semiconductors Product speciﬁcation

8-bit microcontrollers with OSD and VST 84C44X; 84C64X; 84C84X

7 RESET

The RESET pin (active LOW input) is used to initialize the microcontroller to a defined state. The Reset configuration is shown in Fig.5.

ndbook, halfpage

R ≤ 100 kΩ

RESET

MCD174

Fig.4 External components for RESET pin.

7.1 Power-on-reset

The Power-on-reset circuit monitors the voltage level of VDD. If VDD remains below the internal reference voltage level V When VDD rises above V

(typically 1.3 V), the oscillator is inhibited.

ref

, the oscillator is released and

ref

the internal reset is active for a period of td (typically 50 µs).

Considering the VDD rise time, the following measures for a correct Power-on-reset can be taken:

• If the VDD rises above the minimum operation voltage before time period t

is exceeded, no external

components are necessary (see Fig.6).

• If V

has a slow rise time, such that after the time

period (t

Vref+td

) has elapsed the supply voltage is still

below the minimum operation voltage (V

min

external components are required (see Figs 4 and 7). To guarantee a correct reset operation, ensure that the time constant RC ≥ 8 × t

VDD

A definite Power-on-reset can be realized by applying an (external)

RESET signal during power-on.

handbook, full pagewidth

ref

internal

reset

oscillator

inhibit

POWER-ON-RESET

Fig.5 Reset configuration.

MLA651

RESET

1996 Nov 29 8

Philips Semiconductors Product speciﬁcation

8-bit microcontrollers with OSD and VST 84C44X; 84C64X; 84C84X

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RESET

OSCILLATOR

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RESET

without external component

RESET

with external component

ref

oscillator start up time

MCD240

Fig.6 Reset with fast rising VDD.

min

ref

VDD

Vref

RC ≥ 8 × t

VDD

OSCILLATOR

Fig.7 Reset with slow VDD.

1996 Nov 29 9

oscillator start up time

MCD241

Philips Semiconductors Product speciﬁcation

8-bit microcontrollers with OSD and VST 84C44X; 84C64X; 84C84X

8 ANALOG CONTROL

8.1 6-bit PWM DACs

Five PWM outputs are available for analog control purposes e.g. volume, balance, brightness, saturation, etc. The block diagram of a typical 6-bit PWM DAC is shown in Fig.8. Each PWM output can generate pulses of programmable length that have a repetition frequency of

⁄64× f

8.1.1 P

, where f

PWM

IN SELECTION FOR PWM OUTPUTS

PWM

=1⁄3× f

XTAL

The PWM outputs PWM1 to PWM5, share the same pins as the Derivative Port lines DP0.1 to DP0.5.

Setting the (relevant PWM enable) bit PWMnE to:

• Logic 1, selects the relevant PWMx output function

• Logic 0, selects the relevant DP0.x Port function.

8.1.2 P

OLARITY OF THE PWM OUTPUTS

The polarity of all five PWM outputs is selected by the state of the polarity control bit P6LVL.

Setting the control bit P6LVL to:

• Logic 0, sets the PWMx outputs to the default polarity

• Logic 1, inverts all the PWMx outputs.

8.1.3 A

NALOG OUTPUT VOLTAGE

A DC voltage proportional to the PWM control setting may be obtained by connecting an integrating network to each of the PWM outputs (see Fig.9).

The analog value is calculated as follows:

HIGH

------------- -

×=

Where:

•

HIGHt0

•

------------- -

PWMDL× HIGH time of the PWM pulse==

64× repetition time of the PWM pulse==

XTAL

• PWMDL is the decimal value of the contents of the PWM data latch.

Therefore, the analog output voltage is:

PWMDL

----------------------- 64

×=

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PWM

6-BIT PWM DATA LATCH

6-BIT DAC PWM

CONTROLLER

Fig.8 Block diagram of the 6-bit PWM DAC.

1996 Nov 29 10

P6LVL

DP0.x data

I/O

PWMnE

polarity control bit

DP0.x/PWMx

MCD176

Philips Semiconductors Product speciﬁcation

8-bit microcontrollers with OSD and VST 84C44X; 84C64X; 84C84X

handbook, full pagewidth

PWM

64 1 3 m m + 1m + 263641

decimal value PWM data latch

Fig.9 PWM output patterns (P6LVL = 0).

MCD175

1996 Nov 29 11

Philips Semiconductors Product speciﬁcation

8-bit microcontrollers with OSD and VST 84C44X; 84C64X; 84C84X

9 VST CONTROL

9.1 14-bit PWM DAC

The PCA84C640 has one 14-bit PWM DAC output (TDAC) with a resolution of 16384 levels for Voltage Synthesized Tuning. The PWM DAC (see Fig.10) consists of:

• 14-bit counter

• Two 7-bit DAC interface data latches (VSTH and VSTL)

• One 14-bit DAC data latch (VSTREG)

• Pulse control.

The polarity of output TDAC is selected with bit P14LVL. Setting the bit P14LVL to:

• Logic 1, sets the TDAC output to the default polarity

• Logic 0, inverts the TDAC output.

9.1.1 14-

BIT COUNTER

The counter is continuously running and is clocked by f0. The period of the clock,

------------- -

XTAL

The repetition time for one complete cycle of the counter:

rt0

16384×=

The repetition time for one cycle of the lower 7-bits of the counter is:

subt0

Therefore, the number of t

128×=

periods in a complete

sub

cycle tr is:

16384×

--------------------------t

9.1.2 D

128×

ATA AND INTERFACE LATCHES

128==

In order to ensure correct operation, interface data latch VSTH is loaded first and then interface data latch VSTL. The contents of:

• VSTH are used for coarse adjustment

• VSTL are used for fine adjustment.

9.2 Coarse adjustment

The coarse adjustment output (OUT1) is reset to LOW (inactive) at the start of each t It will remain LOW until the time has

period.

sub

t0VSTH 1+()×[] elapsed and then will go HIGH and remain so until the next t

period starts.

sub

9.3 Fine adjustment

Fine adjustment is achieved by generating additional pulses at the start of particular sub-periods (t

subn

). These additional pulses have a width of t0. The sub-period in which a pulse is added is determined by the contents of VSTL interface latch. Table 3 gives the numbers of the t

, at the start of which

subn

an additional pulse is generated, depending on the bit in VSTL being a logic 0. When more than one bit is a logic 0 a combination of additional pulses are generated. For example, if VSTL = 1111010, which is a combination of

• VSTL = 1111110: sub-period 64, and

• VSTL = 1111011: sub-periods 16, 48, 80 and 112,

then additional pulses will be given in sub-periods 16, 48, 64, 80 and 112; this is illustrated in Fig.12.

If VSTH = 0011101, VSTL = 1111010 and P14LVL = 0, then the TDAC output is as shown in Fig.13.

Table 3 Additional pulse distribution

LOWER

7 BITS (VSTL)

ADDITIONAL PULSE IN

SUB-PERIODS t

subn

1111110 64 1111101 32, 96 1111011 16, 48, 80, 112

1110111 8, 24, 40, 56, 72, 88, 104, 120

1101111 4, 12, 20, 28, 36, 44, 52, 60 .... 116, 124

1011111 2, 6, 10, 14, 18, 22, 26, 30, .... 122, 126

0111111 1, 3, 5, 7, 9, 11, 13, 15, 17, .... 125, 127

At the beginning of the first t

period following the loading

sub

of VSTL, both data latches are loaded into data latch VSTREG. After the contents of VSTH and VSTL are latched into VSTREG, one t

period is needed to

sub

generate the appropriate pulse pattern. To ensure correct DAC conversion, two (2) t

periods

sub

should be allowed before beginning the next sequence.

1996 Nov 29 12

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