Philips P89LPC933, P89LPC934, P89LPC935, P89LPC936 Technical data

UM10116

P89LPC933/934/935/936 User manual

Rev. 01 — 4 March 2005 User manual

Document information

Info Content

Keywords P89LPC933/934/935/936

Abstract Technical information for the P89LPC933/934/935/936 devices.

Philips Semiconductors

Revision history

Rev Date Description

01 20050304 Initial version

UM10116

P89LPC933/934/935/936 User manual

User manual Rev. 01 — 4 March 2005 2 of 147

Philips Semiconductors

1. Introduction

The P89LPC933/934/935/936 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC933/934/935/936 are based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC933/934/935/936 in order to reduce component count, board space, and system cost.

1.1 Product comparison overview

Ta bl e 1 highlights the differences between the four devices.

Table 1: Product comparison overview

Device Flash memory Sector size ADC1 ADC0 CCU Data EEPROM

P89LPC933 4 kB 1 kB X - - -

P89LPC934 8 kB 1 kB X - - -

P89LPC935 8 kB 1 kB X X X X

P89LPC936 16 kB 2 kB X X X X

UM10116

P89LPC933/934/935/936 User manual

1.2 Pin configuration

P2.0/DAC0

P0.0/CMP2/KBI0

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.3/INT0/SDA

P1.2/T0/SCL

Fig 1. P89LPC933/934 TSSOP28 pin configuration.

P2.1

P1.7

P1.6

P1.5/RST

V

SS

P1.4/INT1

P2.2/MOSI

P2.3/MISO

1

2

3

4

5

6

7

P89LPC933FDH

8

P89LPC934FDH

9

10

11

12

13

14

002aab071

28

P2.7

27

P2.6

26

P0.1/CIN2B/KBI1/AD10

25

P0.2/CIN2A/KBI2/AD11

24

P0.3/CIN1B/KBI3/AD12

23

P0.4/CIN1A/KBI4/DAC1/AD13

22

P0.5/CMPREF/KBI5

21

V

DD

20

P0.6/CMP1/KBI6

19

P0.7/T1/KBI7

18

P1.0/TXD

17

P1.1/RXD

16

P2.5/SPICLK

15

P2.4/SS

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P89LPC933/934/935/936 User manual

P2.0/ICB/DAC0/AD03

P2.1/OCD/AD02

P0.0/CMP2/KBI0/AD01

P1.7/OCC/AD00

P1.6/OCB

P1.5/RST

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

1

2

3

4

5

6

7

V

SS

P89LPC935FDH

8

P89LPC936FDH

9

10

11

12

13

14

002aab072

Fig 2. P89LPC935/936 TSSOP28 pin configuration.

28

P2.7/ICA

27

P2.6/OCA

26

P0.1/CIN2B/KBI1/AD10

25

P0.2/CIN2A/KBI2/AD11

24

P0.3/CIN1B/KBI3/AD12

23

P0.4/CIN1A/KBI4/DAC1/AD13

22

P0.5/CMPREF/KBI5

21

V

DD

20

P0.6/CMP1/KBI6

19

P0.7/T1/KBI7

18

P1.0/TXD

17

P1.1/RXD

16

P2.5/SPICLK

15

P2.4/SS

P1.7/OCC/AD00

P0.0/CMP2/KBI0/AD01

P2.1/OCD/AD02

P2.0/ICB/DAC0/AD03

1

2

4

3

P1.6/OCB

P1.5/RST

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

5

6

7

V

SS

8

9

10

11

P89LPC935FA

121314

P1.2/T0/SCL

15

P2.4/SS

P2.2/MOSI

P2.3/MISO

Fig 3. P89LPC935 PLCC28 pin configuration.

P2.7/ICA

P2.6/OCA

P0.1/CIN2B/KBI1/AD10

26

27

28

25

24

23

22

21

20

19

161718

P2.5/SPICLK

P1.0/TXD

P1.1/RXD

002aab074

P0.2/CIN2A/KBI2/AD11

P0.3/CIN1B/KBI3/AD12

P0.4/CIN1A/KBI4/DAC1/AD13

P0.5/CMPREF/KBI5

V

DD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

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P89LPC933/934/935/936 User manual

terminal 1

index area

P1.6/OCB

P1.5/RST

V

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

SS

P1.7/OCC/AD00

P0.0/CMP2/KBI0/AD01

28272625242322

1 21

2 20

3

4 18

P89LPC935FHN

5 17

6 16

7 15

8

9

P2.2/MOSI

P1.2/T0/SCL

Transparent top view

P2.7/ICA

P2.1/OCD/AD02

P2.0/ICB/DAC0/AD03

P2.6/OCA

P0.1/CIN2B/KBI1/AD10

1011121314

P2.4/SS

P2.3/MISO

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P0.2/CIN2A/KBI2/AD11

P0.3/CIN1B/KBI3/AD12

19

P0.4/CIN1A/KBI4/DAC1/AD13

P0.5/CMPREF/KBI5

V

DD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

002aab076

Fig 4. P89LPC935/936 HVQFN28 pin configuration.

1.2.1

Table 2: Pin description

Symbol Pin Typ e Description

TSSOP28,

HVQFN28

PLCC28

P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type.

During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1

for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt trigger inputs.

Port 0 also provides various special functions as described below:

P0.0/CMP2/ KBI0/AD01

327I/OP0.0 — Port 0 bit 0.

O CMP2 — Comparator 2 output.

I KBI0 — Keyboard input 0.

I AD01 — ADC0 channel 1 analog input. (P89LPC935/936)

P0.1/CIN2B/ KBI1/AD10

26 22 I/O P0.1 — Port 0 bit 1.

I CIN2B — Comparator 2 positive input B.

I KBI1 — Keyboard input 1.

I AD10 — ADC1 channel 0 analog input.

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P89LPC933/934/935/936 User manual

Table 2: Pin description

Symbol Pin Typ e Description

TSSOP28, PLCC28

P0.2/CIN2A/ KBI2/AD11

P0.3/CIN1B/ KBI3/AD12

P0.4/CIN1A/ KBI4/DAC1

P0.5/ CMPREF/ KBI5

P0.6/CMP1/ KBI6

P0.7/T1/ KBI7

P1.0 to P1.7 I/O, I

P1.0/TXD 18 14 I/O P1.0 — Port 1 bit 0.

P1.1/RXD 17 13 I/O P1.1 — Port 1 bit 1.

P1.2/T0/SCL 12 8 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).

25 21 I/O P0.2 — Port 0 bit 2.

24 20 I/O P0.3 — Port 0 bit 3.

23 19 I/O P0.4 — Port 0 bit 4.

22 18 I/O P0.5 — Port 0 bit 5.

20 16 I/O P0.6 — Port 0 bit 6.

19 15 I/O P0.7 — Port 0 bit 7.

…continued

HVQFN28

I CIN2A — Comparator 2 positive input A.

I KBI2 — Keyboard input 2.

I AD11 — ADC1 channel 1 analog input.

I CIN1B — Comparator 1 positive input B.

I KBI3 — Keyboard input 3.

I AD12 — ADC1 channel 2 analog input.

I CIN1A — Comparator 1 positive input A.

I KBI4 — Keyboard input 4.

O DAC1 — Digital-to-analog converter output 1.

I AD13 — ADC1 channel 3 analog input.

I CMPREF — Comparator reference (negative) input.

I KBI5 — Keyboard input 5.

O CMP1 — Comparator 1 output.

I KBI6 — Keyboard input 6.

I/O T1 — Timer/counter 1 external count input or overflow output.

I KBI7 — Keyboard input 7.

[1]

Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 5.1 P1.3 are open drain when used as outputs. P1.5 is input only.

All pins have Schmitt trigger inputs.

Port 1 also provides various special functions as described below:

O TXD — Transmitter output for the serial port.

I RXD — Receiver input for the serial port.

I/O T0 — Timer/counter 0 external count input or overflow output (open-drain

when used as output).

I/O SCL — I

2

C serial clock input/output.

for details. P1.2 and

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UM10116

P89LPC933/934/935/936 User manual

Table 2: Pin description

Symbol Pin Typ e Description

TSSOP28, PLCC28

P1.3/INT0/ SDA

P1.4/INT1

P1.5/RST

P1.6/OCB 5 1 I/O P1.6 — Port 1 bit 6.

P1.7/OCC/ AD00

11 7 I/O P1.3 — Port 1 bit 3 (open-drain when used as output).

10 6 I P1.4 — Port 1 bit 4.

62IP1.5 — Port 1 bit 5 (input only).

428I/OP1.7 — Port 1 bit 7.

…continued

HVQFN28

I INT0

I/O SDA — I

I INT1

I RST

O OCB — Output Compare B. (P89LPC935/936)

O OCC — Output Compare C. (P89LPC935/936)

I AD00 — ADC0 channel 0 analog input. (P89LPC935/936)

— External interrupt 0 input.

2

C serial data input/output.

— External interrupt 1 input.t

— External Reset input during power-on or if selected via UCFG1.

When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode. When using an oscillator

frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V minimum specified operating voltage.

has reached its specified level. When system

DD

falls below the

DD

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Philips Semiconductors

UM10116

P89LPC933/934/935/936 User manual

Table 2: Pin description

Symbol Pin Typ e Description

TSSOP28, PLCC28

P2.0 to P2.7 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.

P2.0/ICB/ DAC0/AD03

P2.1/OCD/ AD02

P2.2/MOSI 13 9 I/O P2.2 — Port 2 bit 2.

P2.3/MISO 14 10 I/O P2.3 — Port 2 bit 3.

P2.4/SS

P2.5/SPICLK 16 12 I/O P2.5 — Port 2 bit 5.

P2.6/OCA 27 23 I/O P2.6 — Port 2 bit 6.

P2.7/ICA 28 24 I/O P2.7 — Port 2 bit 7.

125I/OP2.0 — Port 2 bit 0.

226I/OP2.1 — Port 2 bit 1.

15 11 I/O P2.4 — Port 2 bit 4.

…continued

HVQFN28

During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1

All pins have Schmitt trigger inputs.

Port 2 also provides various special functions as described below:

I ICB — Input Capture B. (P89LPC935/936)

I DAC0 — Digital-to-analog converter output.

I AD03 — ADC0 channel 3 analog input. (P89LPC935/936)

O OCD — Output Compare D. (P89LPC935/936)

I AD02 — ADC0 channel 2 analog input. (P89LPC935/936)

I/O MOSI — SPI master out slave in. When configured as master, this pin is

output; when configured as slave, this pin is input.

I/O MISO — When configured as master, this pin is input, when configured as

slave, this pin is output.

I SS

I/O SPICLK — SPI clock. When configured as master, this pin is output; when

configured as slave, this pin is input.

O OCA — Output Compare A. (P89LPC935/936)

I ICA — Input Capture A. (P89LPC935/936)

— SPI Slave select.

for details.

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P89LPC933/934/935/936 User manual

Table 2: Pin description

Symbol Pin Typ e Description

TSSOP28, PLCC28

P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type.

P3.0/XTAL2/ CLKOUT

P3.1/XTAL 8 4 I/O P3.1 — Port 3 bit 1.

V

SS

V

DD

95I/OP3.0 — Port 3 bit 0.

73IGround: 0 V reference.

21 17 I Power Supply: This is the power supply voltage for normal operation as

…continued

HVQFN28

During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1

All pins have Schmitt trigger inputs.

Port 3 also provides various special functions as described below:

O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator

option is selected via the FLASH configuration.

O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -

TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer.

I XTAL1 — Input to the oscillator circuit and internal clock generator circuits

(when selected via the FLASH configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer.

for details.

well as Idle and Power-down modes.

[1] Input/Output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

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Philips Semiconductors

1.2.2 Logic symbols

UM10116

P89LPC933/934/935/936 User manual

V

DD

SS

KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7

CLKOUT

DAC1

AD10 AD11 AD12 AD13

Fig 5. P89LPC933/934 logic symbol.

CMP2 CIN2B CIN2A CIN1B CIN1A

CMPREF

CMP1

XTAL2

XTAL1

DAC1

AD01 AD10 AD11 AD12 AD13

KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7

CLKOUT

CMP2 CIN2B CIN2A CIN1B CIN1A

CMPREF

CMP1

T1

XTAL2

XTAL1

T1

PORT 0

PORT 3

PORT 0

PORT 3

V

DD

P89LPC935 P89LPC936

P89LPC933 P89LPC934

002aab077

V

SS

002aab078

PORT 1

PORT 2

PORT 1

PORT 2

TXD RXD T0 INT0 INT1 RST

OCB OCC

ICB OCD MOSI MISO SS SPICLK OCA ICA

TXD RXD T0 INT0 INT1 RST

DAC0 MOSI MISO SS SPICLK

SCL SDA

AD00

AD03 AD02

SCL SDA

DAC0

Fig 6. P89LPC935/936 logic symbol.

User manual Rev. 01 — 4 March 2005 10 of 147

Philips Semiconductors

1.2.3 Block diagram

P89LPC933/934/935/936

UM10116

P89LPC933/934/935/936 User manual

ACCELERATED 2-CLOCK 80C51 CPU

P3[1:0]

P2[7:0]

P1[7:0]

P0[7:0]

4 kb/8 kB/16 kB

CODE FLASH

256-BYTE

DATA RAM

512-BYTE

AUXILIARY RAM

512-BYTE

DATA EEPROM

(P89LPC935/936)

PORT 3

CONFIGURABLE I/Os

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

internal bus

CPU clock

UART

I2C-BUS

SPI

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0 TIMER 1

ANALOG

COMPARATORS

CCU (CAPTURE/ COMPARE UNIT) (P89LPC935/936)

ADC1/DAC1

ADC0/DAC0

(P89LPC935/936)

TXD RXD

SCL SDA

SPICLK MOSI MISO SS

T0 T1

CMP2 CIN2B CIN2A CMP1 CIN1A CIN1B

OCA OCB OCC OCD ICA ICB

AD10 AD11 AD12 AD13 DAC1

AD00 AD01 AD02 AD03 DAC1

CRYSTAL

OR

RESONATOR

X1

X2

CONFIGURABLE

OSCILLATOR

ON-CHIP

RC

OSCILLATOR

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

002aab070

Fig 7. Block diagram.

User manual Rev. 01 — 4 March 2005 11 of 147

Philips Semiconductors

1.3 Special function registers

Remark: SFR accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not defined.

• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

• SFR bits labeled ‘-’, logic 0 or logic 1 can only be written and read as follows:

– ‘-’ Unless otherwise specified, must be written with logic 0, but can return any

– Logic 0 must be written with logic 0, and will return a logic 0 when read.

– Logic 1 must be written with logic 1, and will return a logic 1 when read.

UM10116

P89LPC933/934/935/936 User manual

value when read (even if it was written with logic 0). It is a reserved bit and may be used in future derivatives.

User manual Rev. 01 — 4 March 2005 12 of 147

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User manual Rev. 01 — 4 March 2005 13 of 147

Table 3: Special function registers - P89LPC933/934

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000

ADCON0A/D control register0 8EH-----ENADC0--0000000000

ADCON1 A/D control register 1 97H ENBI1 ENADCI1TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000

ADINSA/D input select A3HADI13ADI12ADI11ADI10----0000000000

ADMODA A/D mode register A C0H BNDI1 BURST1 SCC1 SCAN1 ----0000000000

ADMODB A/D mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 ENDAC0 BSA1 - 00 000x0000

AD0DAT3 A/D_0 data register 3 F4H 00 00000000

AD1BH A/D_1 boundary high register C4H FF 11111111

AD1BL A/D_1 boundary low register BCH 00 00000000

AD1DAT0 A/D_1 data register 0 D5H 00 00000000

AD1DAT1 A/D_1 data register 1 D6H 00 00000000

AD1DAT2 A/D_1 data register 2 D7H 00 00000000

AD1DAT3 A/D_1 data register 3 F5H 00 00000000

AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 000000x0

B* B register F0H 00 00000000

BRGR0

BRGR1

BRGCONBaud rate generator controlBDH------SBRGSBRGEN00

CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00

CMP2 Comparator 2 control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00

DIVM CPU clock divide-by-M control 95H 00 00000000

DPTR Data pointer (2 bytes)

DPH Data pointer high 83H 00 00000000

DPL Data pointer low 82H 00 00000000

FMADRH Program Flash address high E7H 00 00000000

FMADRL Program Flash address low E6H 00 00000000

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

Bit address E7 E6 E5 E4 E3 E2 E1 E0

MSB LSB Hex Binary

Bit address F7 F6 F5 F4 F3 F2 F1 F0

[2]

Baud rate generator rate low BEH 00 00000000

[2]

Baud rate generator rate high BFH 00 00000000

[2]

[1]

xxxxxx00

xx000000

Philips Semiconductors

P89LPC933/934/935/936 User manual

UM10116

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 4 March 2005 14 of 147

Table 3: Special function registers - P89LPC933/934

* indicates SFRs that are bit addressable.

Name Description SFR

FMCON Program Flash control (Read) E4H BUSY - - - HVA HVE SV OI 70 01110000

FMDATA Program Flash data E5H 00 00000000

I2ADR I

I2CON* I

I2DAT I

I2SCLH Serial clock generator/SCL

I2SCLL Serial clock generator/SCL

I2STAT I

ICRAH Input capture A register high ABH 00 00000000

ICRAL Input capture A register low AAH 00 00000000

ICRBH Input capture B register high AFH 00 00000000

ICRBL Input capture B register low AEH 00 00000000

IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 00000000

IEN1* Interrupt enable 1 E8H EAD EST - - ESPI EC EKBI EI2C 00

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00

IP0H Interrupt priority 0 high B7H - PWDRTHPBOH PSH/

IP1* Interrupt priority 1 F8H PAD PST - - PSPI PC PKBI PI2C 00

IP1H Interrupt priority 1 high F7H PADH PSTH - - PSPIH PCH PKBIH PI2CH 00

KBCON Keypad control register 94H ------PATN

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

Program Flash control (Write) E4H FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

2

C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 00000000

Bit address DF DE DD DC DB DA D9 D8

2

C control register D8H - I2EN STA STO SI AA - CRSEL 00 x00000x0

2

C data register DAH

DDH 00 00000000

duty cycle register high

DCH 00 00000000

duty cycle register low

2

C status register D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 11111000

Bit address AF AE AD AC AB AA A9 A8

Bit address EF EE ED EC EB EA E9 E8

Bit address BF BE BD BC BB BA B9 B8

Bit address FF FE FD FC FB FA F9 F8

MSB LSB Hex Binary

0

[1]

PT1H PX1H PT0H PX0H 00

PSRH

KBIF 00

_SEL

[1]

Philips Semiconductors

P89LPC933/934/935/936 User manual

00x00000

x0000000

UM10116

00x00000

xxxxxx00

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User manual Rev. 01 — 4 March 2005 15 of 147

Table 3: Special function registers - P89LPC933/934 …continued

* indicates SFRs that are bit addressable.

Name Description SFR

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

P0* Port 0 80H T1/KB7 CMP1

P1* Port 1 90H - - RST

P2* Port 2 A0H - - SPICLK SS

P3*Port3 B0H------XTAL1XTAL2

P0M1 Port 0 output mode 1 84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF

P0M2 Port 0 output mode 2 85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00

P1M1 Port 1 output mode 1 91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3

P1M2 Port 1 output mode 2 92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00

P2M1 Port 2 output mode 1 A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF

P2M2 Port 2 output mode 2 A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00

P3M1Port3 output mode1 B1H------(P3M1.1)(P3M1.0)03

P3M2Port3 output mode2 B2H------(P3M2.1)(P3M2.0)00

PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000

PCONA Power control register A B5H RTCPD - VCPD ADPD I2PD SPPD SPD - 00

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000

PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00000x

RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX

RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60

RTCH Real-time clock register high D2H 00

RTCL Real-time clock register low D3H 00

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

86H 00 00000000

register

Bit address 87 86 85 84 83 82 81 80

Bit address 97 96 95 94 93 92 91 90

Bit address A7 A6 A5 A4 A3 A2 A1 A0

Bit address B7 B6 B5 B4 B3 B2 B1 B0

Bit address D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB Hex Binary

/KB6

CMPREF

/KB5

CIN1A

/KB4

INT1 INT0/

CIN1B

/KB3

SDA

MISO MOSI - -

CIN2A

/KB2

T0/SCL RXD TXD

CIN2B

/KB1

CMP2

/KB0

[1]

[1][6]

[6]

[1]

11111111

00000000

11x1xx11

00x0xx00

11111111

00000000

xxxxxx11

xxxxxx00

00000000

[3]

011xxx00

00000000

Philips Semiconductors

P89LPC933/934/935/936 User manual

UM10116

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User manual Rev. 01 — 4 March 2005 16 of 147

Table 3: Special function registers - P89LPC933/934 …continued

* indicates SFRs that are bit addressable.

Name Description SFR

SADDR Serial port address register A9H 00 00000000

SADEN Serial port address enable B9H 00 00000000

SBUF Serial Port data buffer register 99H xx xxxxxxxx

SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000

SSTAT Serial port extended status

SP Stack pointer 81H 07 00000111

SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 00000100

SPSTAT SPI status register E1H SPIF WCOL ------0000xxxxxx

SPDAT SPI data register E3H 00 00000000

TAMOD Timer 0 and 1 auxiliary mode 8FH - - - T1M2 - - - T0M2 00 xxx0xxx0

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 00000000

TH0 Timer 0 high 8CH 00 00000000

TH1 Timer 1 high 8DH 00 00000000

TL0 Timer 0 low 8AH 00 00000000

TL1 Timer 1 low 8BH 00 00000000

TMOD Timer 0 and 1 mode 89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 00000000

TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0

WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

Bit address 9F 9E 9D 9C 9B 9A 99 98

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000

register

Bit address 8F 8E 8D 8C 8B 8A 89 88

MSB LSB Hex Binary

Philips Semiconductors

P89LPC933/934/935/936 User manual

[5] [6]

[4] [6]

UM10116

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 4 March 2005 17 of 147

Table 3: Special function registers - P89LPC933/934

* indicates SFRs that are bit addressable.

Name Description SFR

WDL Watchdog load C1H FF 11111111

WFEED1 Watchdog feed 1 C2H

WFEED2 Watchdog feed 2 C3H

[1] All ports are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reflects the cause of the UM10116 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is

[4] After reset, the value is 111001x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

xx110000.

Other resets will not affect WDTOF.

MSB LSB Hex Binary

…continued

Philips Semiconductors

P89LPC933/934/935/936 User manual

UM10116

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

User manual Rev. 01 — 4 March 2005 18 of 147

Table 4: Special function registers - P89LPC935/936

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000

ADCON0 A/D control register 0 8EH ENBI0 ENADCI0TMM0 EDGE0 ADCI0 ENADC0 ADCS01 ADCS00 00 00000000

ADCON1 A/D control register 1 97H ENBI1 ENADCI1TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000

ADINS A/D input select A3H ADI13 ADI12 ADI11 ADI10 ADI03 ADI02 ADI01 ADI00 00 00000000

ADMODA A/D mode register A C0H BNDI1 BURST1 SCC1 SCAN1 BNDI0 BURST0 SCC0 SCAN0 00 00000000

ADMODB A/D mode register B A1H CLK2 CLK1 CLK0 - ENDAC1 ENDAC0 BSA1 BSA0 00 000x0000

AD0BH A/D_0 boundary high register BBH FF 11111111

AD0BL A/D_0 boundary low register A6H 00 00000000

AD0DAT0 A/D_0 data register 0 C5H 00 00000000

AD0DAT1 A/D_0 data register 1 C6H 00 00000000

AD0DAT2 A/D_0 data register 2 C7H 00 00000000

AD0DAT3 A/D_0 data register 3 F4H 00 00000000

AD1BH A/D_1 boundary high register C4H FF 11111111

AD1BL A/D_1 boundary low register BCH 00 00000000

AD1DAT0 A/D_1 data register 0 D5H 00 00000000

AD1DAT1 A/D_1 data register 1 D6H 00 00000000

AD1DAT2 A/D_1 data register 2 D7H 00 00000000

AD1DAT3 A/D_1 data register 3 F5H 00 00000000

AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 000000x0

B* B register F0H 00 00000000

BRGR0

BRGR1

BRGCONBaud rate generator controlBDH------SBRGSBRGEN00

CCCRA Capture compare A control

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

Bit address E7 E6 E5 E4 E3 E2 E1 E0

MSB LSB Hex Binary

Bit address F7 F6 F5 F4 F3 F2 F1 F0

[2]

Baud rate generator rate low BEH 00 00000000

[2]

Baud rate generator rate high BFH 00 00000000

[2]

EAH ICECA2 ICECA1 ICECA0 ICESA ICNFA FCOA OCMA1 OCMA0 00 00000000

register

Philips Semiconductors

P89LPC933/934/935/936 User manual

UM10116

xxxxxx00

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User manual Rev. 01 — 4 March 2005 19 of 147

Table 4: Special function registers - P89LPC935/936

* indicates SFRs that are bit addressable.

Name Description SFR

CCCRB Capture compare B control

CCCRC Capture compare C control

CCCRD Capture compare D control

CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00

CMP2 Comparator 2 control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00

DEECON Data EEPROM control

DEEDAT Data EEPROM data register F2H 00 00000000

DEEADR Data EEPROM address

DIVM CPU clock divide-by-M control 95H 00 00000000

DPTR Data pointer (2 bytes)

DPH Data pointer high 83H 00 00000000

DPL Data pointer low 82H 00 00000000

FMADRH Program Flash address high E7H 00 00000000

FMADRL Program Flash address low E6H 00 00000000

FMCON Program Flash control (Read) E4H BUSY - - - HVA HVE SV OI 70 01110000

FMDATA Program Flash data E5H 00 00000000

I2ADR I

I2CON* I

I2DAT I

I2SCLH Serial clock generator/SCL

I2SCLL Serial clock generator/SCL

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

EBH ICECB2 ICECB1 ICECB0 ICESB ICNFB FCOB OCMB1 OCMB0 00 00000000

register

ECH-----FCOCOCMC1OCMC000xxxxx000

register

EDH-----FCODOCMD1OCMD000xxxxx000

register

F1H EEIF HVERR ECTL1 ECTL0 - - - EADR8 0E 00001110

register

F3H 00 00000000

register

MSB LSB Hex Binary

[1]

Program Flash control (Write) E4H FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

0

2

C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 00000000

Bit address DF DE DD DC DB DA D9 D8

2

C control register D8H - I2EN STA STO SI AA - CRSEL 00 x00000x0

2

C data register DAH

DDH 00 00000000

duty cycle register high

DCH 00 00000000

duty cycle register low

Philips Semiconductors

xx000000

P89LPC933/934/935/936 User manual

UM10116

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User manual Rev. 01 — 4 March 2005 20 of 147

Table 4: Special function registers - P89LPC935/936

* indicates SFRs that are bit addressable.

Name Description SFR

I2STAT I2C status register D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 11111000

ICRAH Input capture A register high ABH 00 00000000

ICRAL Input capture A register low AAH 00 00000000

ICRBH Input capture B register high AFH 00 00000000

ICRBL Input capture B register low AEH 00 00000000

IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 00000000

IEN1* Interrupt enable 1 E8H EADEE EST - ECCU ESPI EC EKBI EI2C 00

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00

IP0H Interrupt priority 0 high B7H - PWDRTHPBOH PSH/

IP1* Interrupt priority 1 F8H PADEE PST - PCCU PSPI PC PKBI PI2C 00

IP1H Interrupt priority 1 high F7H PAEEH PSTH - PCCUH PSPIH PCH PKBIH PI2CH 00

KBCON Keypad control register 94H ------PATN

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

OCRAH Output compare A register

OCRAL Output compare A register

OCRBH Output compare B register

OCRBL Output compare B register

OCRCH Output compare C register

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

Bit address AF AE AD AC AB AA A9 A8

Bit address EF EE ED EC EB EA E9 E8

Bit address BF BE BD BC BB BA B9 B8

Bit address FF FE FD FC FB FA F9 F8

86H 00 00000000

register

EFH 00 00000000

high

EEH 00 00000000

low

FBH 00 00000000

high

FAH 00 00000000

low

FDH 00 00000000

high

MSB LSB Hex Binary

PSRH

PT1H PX1H PT0H PX0H 00

KBIF 00

_SEL

[1]

Philips Semiconductors

00x00000

x0000000

00x00000

xxxxxx00

P89LPC933/934/935/936 User manual

UM10116

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User manual Rev. 01 — 4 March 2005 21 of 147

Table 4: Special function registers - P89LPC935/936 …continued

* indicates SFRs that are bit addressable.

Name Description SFR

OCRCL Output compare C register

OCRDH Output compare D register

OCRDL Output compare D register

P0* Port 0 80H T1/KB7 CMP1

P1* Port 1 90H OCC OCB RST

P2* Port 2 A0H ICA OCA SPICLK SS

P3*Port3 B0H------XTAL1XTAL2

P0M1 Port 0 output mode 1 84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF

P0M2 Port 0 output mode 2 85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00

P1M1 Port 1 output mode 1 91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3

P1M2 Port 1 output mode 2 92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00

P2M1 Port 2 output mode 1 A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF

P2M2 Port 2 output mode 2 A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00

P3M1Port3 output mode1 B1H------(P3M1.1)(P3M1.0)03

P3M2Port3 output mode2 B2H------(P3M2.1)(P3M2.0)00

PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000

PCONA Power control register A B5H RTCPD DEEPD VCPD ADPD I2PD SPPD SPD CCUPD 00

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000

PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00000x

RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Bit functions and addresses Reset value

addr.

FCH 00 00000000

low

FFH 00 00000000

high

FEH 00 00000000

low

Bit address 87 86 85 84 83 82 81 80

Bit address 97 96 95 94 93 92 91 90

Bit address A7 A6 A5 A4 A3 A2 A1 A0

Bit address B7 B6 B5 B4 B3 B2 B1 B0

Bit address D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB Hex Binary

/KB6

CMPREF

/KB5

CIN1A

/KB4

INT1 INT0/

CIN1B

/KB3

SDA

MISO MOSI OCD ICB

CIN2A

/KB2

T0/SCL RXD TXD

CIN2B

/KB1

CMP2

/KB0

[1]

11111111

00000000

11x1xx11

00x0xx00

11111111

00000000

xxxxxx11

xxxxxx00

00000000

[3]

Philips Semiconductors

P89LPC933/934/935/936 User manual

UM10116

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User manual Rev. 01 — 4 March 2005 22 of 147

Table 4: Special function registers - P89LPC935/936

* indicates SFRs that are bit addressable.

Name Description SFR

RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60

RTCH Real-time clock register high D2H 00

RTCL Real-time clock register low D3H 00

SADDR Serial port address register A9H 00 00000000

SADEN Serial port address enable B9H 00 00000000

SBUF Serial Port data buffer register 99H xx xxxxxxxx

SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000

SSTAT Serial port extended status

SP Stack pointer 81H 07 00000111

SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 00000100

SPSTAT SPI status register E1H SPIF WCOL ------0000xxxxxx

SPDAT SPI data register E3H 00 00000000

TAMOD Timer 0 and 1 auxiliary mode 8FH - - - T1M2 - - - T0M2 00 xxx0xxx0

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 00000000

TCR20* CCU control register 0 C8H PLEEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20 00 00000000

TCR21 CCU control register 1 F9H TCOU2 - - - PLLDV.3 PLLDV.2 PLLDV.1 PLLDV.0 00 0xxx0000

TH0 Timer 0 high 8CH 00 00000000

TH1 Timer 1 high 8DH 00 00000000

TH2 CCU timer high CDH 00 00000000

TICR2 CCU interrupt control register C9H TOIE2 TOCIE2DTOCIE2CTOCIE2B TOCIE2A - TICIE2B TICIE2A 00 00000x00

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

Bit address 9F 9E 9D 9C 9B 9A 99 98

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000

register

Bit address 8F 8E 8D 8C 8B 8A 89 88

MSB LSB Hex Binary

[1][6]

[6]

Philips Semiconductors

011xxx00

00000000

P89LPC933/934/935/936 User manual

TIFR2 CCU interrupt flag register E9H TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A - TICF2B TICF2A 00 00000x00

TISE2 CCU interrupt status encode

register

TL0 Timer 0 low 8AH 00 00000000

TL1 Timer 1 low 8BH 00 00000000

TL2 CCU timer low CCH 00 00000000

DEH-----ENCINT.

ENCINT.1ENCINT.000 xxxxx000

2

UM10116

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User manual Rev. 01 — 4 March 2005 23 of 147

Table 4: Special function registers - P89LPC935/936

* indicates SFRs that are bit addressable.

Name Description SFR

TMOD Timer 0 and 1 mode 89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 00000000

TOR2H CCU reload register high CFH 00 00000000

TOR2L CCU reload register low CEH 00 00000000

TPCR2HPrescaler control register highCBH------TPCR2H.

TPCR2L Prescaler control register low CAH TPCR2L.7TPCR2L.6TPCR2L.5TPCR2L.4TPCR2L.3TPCR2L.2TPCR2L.1TPCR2L.000 00000000

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

addr.

…continued

Bit functions and addresses Reset value

MSB LSB Hex Binary

TPCR2H.000 xxxxxx00

1

Philips Semiconductors

TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0

WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK

WDL Watchdog load C1H FF 11111111

WFEED1 Watchdog feed 1 C2H

WFEED2 Watchdog feed 2 C3H

[1] All ports are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reflects the cause of the UM10116 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is

xx110000.

[4] After reset, the value is 111001x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

[5] [6]

[4] [6]

P89LPC933/934/935/936 User manual

UM10116

Philips Semiconductors

1.4 Memory organization

FF00h

FFEFh

1FFFh

1E00h

1C00h 1BFFh

1800h 17FFh

1400h 13FFh

1000h

0FFFh

0C00h 0BFFh

0800h 07FFh

0400h 03FFh

0000h

IAP entry-

points

ISP CODE

(1)

(512B)

SECTOR 7

SECTOR 6

SECTOR 5

SECTOR 4

SECTOR 3

SECTOR 2

SECTOR 1

SECTOR 0

read-protected

IAP calls only

IDATA routines

entry points for:

-51 ASM. code

-C code

ISP serial loader

entry points for:

-UART (auto-baud)

-I2C, SPI, etc.

UM10116

P89LPC933/934/935/936 User manual

FFEFh

FF1Fh

FF00h

1FFFh

(1)

1E00h

entry points

SPECIAL FUNCTION

REGISTERS

(DIRECTLY ADDRESSABLE)

IDATA (incl. DATA)

128 BYTES ON-CHIP

DATA MEMORY (STACK

AND INDIR. ADDR.)

DATA

128 BYTES ON-CHIP

DATA MEMORY (STACK,

DIRECT AND INDIR. ADDR.)

4 REG. BANKS R[7:0]

data memory

(DATA, IDATA)

002aab228

(1) ISP code located in Sector 3 for the P89LPC933 device.

Fig 8. P89LPC933/934/935/936 memory map.

1.5 Memory organization

The various P89LPC933/934/935/936 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

• SFR

Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

• XDATA (P89LPC935/936)

‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC935/936 has 512 bytes of on-chip XDATA memory.

User manual Rev. 01 — 4 March 2005 24 of 147

Philips Semiconductors

• CODE

64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The UM10116 have 4 KB/8 kB/16 kB of on-chip Code memory.

The P89LPC935/936 also has 512 bytes of on-chip Data EEPROM that is accessed via SFRs (see Section 18 “

2. Clocks

2.1 Enhanced CPU

The P89LPC933/934/935/936 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

2.2 Clock definitions

The P89LPC933/934/935/936 device has several internal clocks as defined below:

UM10116

P89LPC933/934/935/936 User manual

Data EEPROM (P89LPC935/936)”).

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources and can also be optionally divided to a slower frequency (see Figure 10

Section 2.8 “

OSCCLK frequency.

CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is

2.2.1 Oscillator Clock (OSCCLK)

The P89LPC933/934/935/936 provides several user-selectable oscillator options. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.

2.2.2 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.

CPU Clock (CCLK) modification: DIVM register”). Note: f

CCLK

⁄2.

and

is defined as the

osc

2.2.3 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.

2.2.4 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration. When using an oscillator frequency

above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit

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is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed V specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V

2.3 Clock output

The P89LPC933/934/935/936 supports a user-selectable clock output function on the XTAL2 / CLKOUT pin when the crystal oscillator is not being used. This condition occurs if a different clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-time Clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC933/934/935/936. This output is enabled by the ENCLK bit in the TRIM register

UM10116

P89LPC933/934/935/936 User manual

will fall below the minimum

DD

falls below the minimum specified operating voltage.

DD

The frequency of this clock output is in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of other bits of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.

1

⁄2 that of the CCLK. If the clock output is not needed

2.4 On-chip RC oscillator option

The P89LPC933/934/935/936 has a TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ± 1 %. (Note: the initial value is better than 1 %; please refer to the P89LPC933/934/935/936 data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency.

Table 5: On-chip RC oscillator trim register (TRIM - address 96h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0

Reset 0 0 Bits 5:0 loaded with factory stored value during reset.

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9

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P89LPC933/934/935/936 User manual

Table 6: On-chip RC oscillator trim register (TRIM - address 96h) bit description

Bit Symbol Description

0 TRIM.0 Trim value. Determines the frequency of the internal RC oscillator. During reset,

1TRIM.1

2TRIM.2

3TRIM.3

4TRIM.4

5TRIM.5

6 ENCLK when = 1,

7 RCCLK when = 1, selects the RC Oscillator output as the CPU clock (CCLK). This allows for

these bits are loaded with a stored factory calibration value. When writing to either bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value by reading this register, modifying bits 6 or 7 as required, and writing the result to this register.

CCLK

⁄2 is output on the XTAL2 pin provided the crystal oscillator is not

being used.

fast switching between any clock source and the internal RC oscillator without needing to go through a reset cycle.

2.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

2.6 External clock input option

In this configuration, the processor clock is derived from an external source driving the XTAL1 / P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output. When using an oscillator frequency

above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V specified level. When system power is removed V specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V

has reached its

DD

will fall below the minimum

DD

falls below the minimum specified operating voltage.

DD

quartz crystal or

ceramic resonator

P89LPC93x

XTAL1

(1)

XTAL2

002aab22

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

(1) A series resistor may be required to limit crystal drive levels. This is especially important for low

frequency crystals.

Fig 9. Using the crystal oscillator.

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UM10116

P89LPC933/934/935/936 User manual

XTAL1

XTAL2

(7.3728 MHz ±1 %)

(400 kHz +30 % −20 %)

Fig 10. Block diagram of oscillator control.

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

RC

OSCILLATOR

WATCHDOG

OSCILLATOR

RCCLK

TIMER 0 AND

TIMER 1

OSCCLK

I2C-BUS

PCLK

DIVM

SPI

CCLK

PCLK

÷2

UART

ADC1

ADC0

(P89LPC935/936)

2.7 Oscillator Clock (OSCCLK) wake-up delay

The P89LPC933/934/935/936 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections, the delay is 992 OSCCLK cycles plus 60 µs to 100 µs. If the clock source is either the internal RC oscillator or the Watchdog oscillator, the delay is 224 OSCCLK cycles plus 60 µs to 100 µs.

RTC

CPU

WDT

32 × PLL

CCU

002aab079

2.8 CPU Clock (CCLK) modification: DIVM register

The OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK frequency using the following formula:

CCLK frequency = f

Where: f

is the frequency of OSCCLK, N is the value of DIVM.

osc

Since N ranges from 0 to 255, the CCLK frequency can be in the range of f (for N = 0, CCLK = f

This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. This can allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

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osc

).

/ (2N)

osc

to f

osc

/510.

Philips Semiconductors

2.9 Low power select

The P89LPC933/934/935/936 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.

3. A/D converter

3.1

The P89LPC935/936 have two 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter modules sharing common control logic. The P89LPC933/934 have a single 8-bit, 4-channel multiplexed analog-to-digital converter (ADC1) and an additional DAC module (DAC0). A block diagram of the A/D converter is shown in

Figure 11

circuit providing an input signal to one of two comparator inputs. The control logic in combination with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.

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P89LPC933/934/935/936 User manual

. Each A/D consists of a 4-input multiplexer which feeds a sample-and-hold

3.2 A/D features

• Two (P89LPC935/936) 8-bit, 4-channel multiplexed input, successive approximation

A/D converters with common control logic (one A/D on the P89LPC933/934).

• Four result registers for each A/D.

• Six operating modes

– Fixed channel, single conversion mode

– Fixed channel, continuous conversion mode

– Auto scan, single conversion mode

– Auto scan, continuous conversion mode

– Dual channel, continuous conversion mode

– Single step mode

• Four conversion start modes

– Timer triggered start

– Start immediately

– Edge triggered

– Dual start immediately (P89LPC935/936)

• 8-bit conversion time of ≥3.9 µs at an A/D clock of 3.3 MHz

• Interrupt or polled operation

• Boundary limits interrupt

• DAC output to a port pin with high output impedance

• Clock divider

• Power down mode

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0

3.2.1 A/D operating modes

3.2.1.1 Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel (see Ta bl e 7 completes. The input channel is selected in the ADINS register. This mode is selected by setting the SCANx bit in the ADMODA register.

INPUT

MUX

UM10116

P89LPC933/934/935/936 User manual

). An interrupt, if enabled, will be generated after the conversion

comp

+

–

SAR

INPUT

MUX

DAC1

comp

+

–

SAR

8

CONTROL

LOGIC

DAC0

CCLK

Fig 11. ADC block diagram.

Table 7: Input channels and result registers for fixed channel single, auto scan single, and

auto scan continuous conversion modes

Result register Input channel Result register Input channel

AD0DAT0 AD00 AD1DAT0 AD10

AD0DAT1 AD01 AD1DAT1 AD11

AD0DAT2 AD02 AD1DAT2 AD12

AD0DAT3 AD03 AD1DAT3 AD13

8

002aab08

3.2.1.2 Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result registers (see Tab le 8

). An interrupt, if enabled, will be generated after every four conversions. Additional conversion results will again cycle through the four result registers, overwriting the previous results. Continuous conversions continue until terminated by the user. This mode is selected by setting the SCCx bit in the ADMODA register.

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