UM10116
P89LPC933/934/935/936 User manual
Rev. 01 — 4 March 2005 User manual 
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P89LPC933/934/935/936 |
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Abstract |
Technical information for the P89LPC933/934/935/936 devices. |
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Philips Semiconductors |
UM10116 |
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P89LPC933/934/935/936 User manual |
Revision history |
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20050304 |
Initial version |
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
2 of 147 |
Philips Semiconductors |
UM10116 |
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P89LPC933/934/935/936 User manual |
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1. Introduction
The P89LPC933/934/935/936 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC933/934/935/936 are based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC933/934/935/936 in order to reduce component count, board space, and system cost.
1.1 Product comparison overview
Table 1 highlights the differences between the four devices.
Table 1: Product comparison overview
Device |
Flash memory |
Sector size |
ADC1 |
ADC0 |
CCU |
Data EEPROM |
P89LPC933 |
4 kB |
1 kB |
X |
- |
- |
- |
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P89LPC934 |
8 kB |
1 kB |
X |
- |
- |
- |
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P89LPC935 |
8 kB |
1 kB |
X |
X |
X |
X |
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P89LPC936 |
16 kB |
2 kB |
X |
X |
X |
X |
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1.2 Pin configuration
P2.0/DAC0 |
1 |
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28 |
P2.7 |
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P2.1 |
2 |
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27 |
P2.6 |
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P0.0/CMP2/KBI0 |
3 |
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26 |
P0.1/CIN2B/KBI1/AD10 |
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P1.7 |
4 |
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25 |
P0.2/CIN2A/KBI2/AD11 |
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P1.6 |
5 |
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24 |
P0.3/CIN1B/KBI3/AD12 |
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P1.5/RST |
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6 |
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23 |
P0.4/CIN1A/KBI4/DAC1/AD13 |
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VSS |
7 |
P89LPC933FDH |
22 |
P0.5/CMPREF/KBI5 |
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P3.1/XTAL1 |
8 |
P89LPC934FDH |
21 |
VDD |
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P3.0/XTAL2/CLKOUT |
9 |
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20 |
P0.6/CMP1/KBI6 |
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P1.4/INT1 |
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10 |
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19 |
P0.7/T1/KBI7 |
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P1.3/INT0/SDA |
11 |
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18 |
P1.0/TXD |
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P1.2/T0/SCL |
12 |
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17 |
P1.1/RXD |
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P2.2/MOSI |
13 |
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16 |
P2.5/SPICLK |
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P2.3/MISO |
14 |
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15 |
P2.4/SS |
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002aab071
Fig 1. P89LPC933/934 TSSOP28 pin configuration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
3 of 147 |
Philips Semiconductors |
UM10116 |
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P89LPC933/934/935/936 User manual |
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P2.0/ICB/DAC0/AD03 |
1 |
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28 |
P2.7/ICA |
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P2.1/OCD/AD02 |
2 |
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27 |
P2.6/OCA |
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P0.0/CMP2/KBI0/AD01 |
3 |
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26 |
P0.1/CIN2B/KBI1/AD10 |
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P1.7/OCC/AD00 |
4 |
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25 |
P0.2/CIN2A/KBI2/AD11 |
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P1.6/OCB |
5 |
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24 |
P0.3/CIN1B/KBI3/AD12 |
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P1.5/RST |
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6 |
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23 |
P0.4/CIN1A/KBI4/DAC1/AD13 |
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VSS |
7 |
P89LPC935FDH |
22 |
P0.5/CMPREF/KBI5 |
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P3.1/XTAL1 |
8 |
P89LPC936FDH |
21 |
VDD |
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P3.0/XTAL2/CLKOUT |
9 |
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20 |
P0.6/CMP1/KBI6 |
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P1.4/INT1 |
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10 |
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19 |
P0.7/T1/KBI7 |
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P1.3/INT0/SDA |
11 |
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18 |
P1.0/TXD |
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P1.2/T0/SCL |
12 |
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17 |
P1.1/RXD |
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P2.2/MOSI |
13 |
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16 |
P2.5/SPICLK |
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P2.3/MISO |
14 |
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15 |
P2.4/SS |
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002aab072
Fig 2. P89LPC935/936 TSSOP28 pin configuration.
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P1.7/OCC/AD00 |
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P0.0/CMP2/KBI0/AD01 |
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P2.1/OCD/AD02 |
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P2.0/ICB/DAC0/AD03 |
P2.7/ICA |
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P2.6/OCA |
P0.1/CIN2B/KBI1/AD10 |
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26 |
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4 |
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3 |
2 |
1 |
28 |
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27 |
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P1.6/OCB |
5 |
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P1.5/RST |
6 |
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VSS |
7 |
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P3.1/XTAL1 |
8 |
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P89LPC935FA |
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P3.0/XTAL2/CLKOUT |
9 |
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P1.4/INT1 |
10 |
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P1.3/INT0/SDA |
11 |
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16 |
17 |
18 |
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12 |
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14 |
15 |
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P2.5/SPICLK |
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P1.1/RXD |
P1.0/TXD |
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P1.2/T0/SCL |
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P2.2/MOSI |
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P2.3/MISO |
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P2.4/SS |
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25 |
P0.2/CIN2A/KBI2/AD11 |
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24 |
P0.3/CIN1B/KBI3/AD12 |
23 |
P0.4/CIN1A/KBI4/DAC1/AD13 |
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22 |
P0.5/CMPREF/KBI5 |
21 |
VDD |
20 |
P0.6/CMP1/KBI6 |
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P0.7/T1/KBI7 |
19 |
002aab074
Fig 3. P89LPC935 PLCC28 pin configuration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
4 of 147 |
Philips Semiconductors |
UM10116 |
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P89LPC933/934/935/936 User manual |
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terminal 1 index area 
P1.6/OCB 1
P1.5/RST 2
VSS 3
P3.1/XTAL1 4
P3.0/XTAL2/CLKOUT 5
P1.4/INT1 6
P1.3/INT0/SDA 7
P1.7/OCC/AD00 |
P0.0/CMP2/KBI0/AD01 |
P2.1/OCD/AD02 |
P2.0/ICB/DAC0/AD03 |
P2.7/ICA |
P2.6/OCA |
P0.1/CIN2B/KBI1/AD10 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
P89LPC935FHN
8 |
9 |
10 |
11 |
12 |
13 |
14 |
P1.2/T0/SCL |
P2.2/MOSI |
P2.3/MISO |
P2.4/SS |
P2.5/SPICLK |
P1.1/RXD |
P1.0/TXD |
Transparent top view
21 P0.2/CIN2A/KBI2/AD11
20 P0.3/CIN1B/KBI3/AD12
19 P0.4/CIN1A/KBI4/DAC1/AD13
18 P0.5/CMPREF/KBI5
17 VDD
16 P0.6/CMP1/KBI6
15 P0.7/T1/KBI7
002aab076
Fig 4. P89LPC935/936 HVQFN28 pin configuration.
1.2.1
Table 2: Pin description
Symbol |
Pin |
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Type |
Description |
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TSSOP28, |
HVQFN28 |
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PLCC28 |
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P0.0 to P0.7 |
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I/O |
Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. |
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During reset Port 0 latches are configured in the input only mode with the |
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internal pull-up disabled. The operation of Port 0 pins as inputs and |
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outputs depends upon the port configuration selected. Each port pin is |
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configured independently. Refer to Section 5.1 for details. |
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The Keypad Interrupt feature operates with Port 0 pins. |
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All pins have Schmitt trigger inputs. |
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Port 0 also provides various special functions as described below: |
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P0.0/CMP2/ |
3 |
27 |
I/O |
P0.0 — Port 0 bit 0. |
KBI0/AD01 |
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O |
CMP2 — Comparator 2 output. |
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I |
KBI0 — Keyboard input 0. |
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I |
AD01 — ADC0 channel 1 analog input. (P89LPC935/936) |
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P0.1/CIN2B/ |
26 |
22 |
I/O |
P0.1 — Port 0 bit 1. |
KBI1/AD10 |
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I |
CIN2B — Comparator 2 positive input B. |
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I |
KBI1 — Keyboard input 1. |
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I |
AD10 — ADC1 channel 0 analog input. |
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
5 of 147 |
Philips Semiconductors |
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UM10116 |
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P89LPC933/934/935/936 User manual |
Table 2: Pin description …continued |
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Symbol |
Pin |
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Type |
Description |
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TSSOP28, |
HVQFN28 |
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PLCC28 |
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P0.2/CIN2A/ |
25 |
21 |
I/O |
P0.2 — Port 0 bit 2. |
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KBI2/AD11 |
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CIN2A — Comparator 2 positive input A. |
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I |
KBI2 — Keyboard input 2. |
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I |
AD11 — ADC1 channel 1 analog input. |
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P0.3/CIN1B/ |
24 |
20 |
I/O |
P0.3 — Port 0 bit 3. |
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KBI3/AD12 |
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CIN1B — Comparator 1 positive input B. |
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I |
KBI3 — Keyboard input 3. |
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I |
AD12 — ADC1 channel 2 analog input. |
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P0.4/CIN1A/ |
23 |
19 |
I/O |
P0.4 — Port 0 bit 4. |
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KBI4/DAC1 |
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CIN1A — Comparator 1 positive input A. |
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I |
KBI4 — Keyboard input 4. |
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O |
DAC1 — Digital-to-analog converter output 1. |
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I |
AD13 — ADC1 channel 3 analog input. |
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P0.5/ |
22 |
18 |
I/O |
P0.5 — Port 0 bit 5. |
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CMPREF/ |
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I |
CMPREF — Comparator reference (negative) input. |
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KBI5 |
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KBI5 — Keyboard input 5. |
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P0.6/CMP1/ |
20 |
16 |
I/O |
P0.6 — Port 0 bit 6. |
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KBI6 |
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O |
CMP1 — Comparator 1 output. |
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I |
KBI6 — Keyboard input 6. |
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P0.7/T1/ |
19 |
15 |
I/O |
P0.7 — Port 0 bit 7. |
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KBI7 |
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I/O |
T1 — Timer/counter 1 external count input or overflow output. |
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I |
KBI7 — Keyboard input 7. |
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P1.0 to P1.7 |
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I/O, I [1] |
Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, |
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except for three pins as noted below. During reset Port 1 latches are |
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configured in the input only mode with the internal pull-up disabled. The |
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operation of the configurable Port 1 pins as inputs and outputs depends |
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upon the port configuration selected. Each of the configurable port pins |
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are programmed independently. Refer to Section 5.1 for details. P1.2 and |
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P1.3 are open drain when used as outputs. P1.5 is input only. |
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All pins have Schmitt trigger inputs. |
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Port 1 also provides various special functions as described below: |
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P1.0/TXD |
18 |
14 |
I/O |
P1.0 — Port 1 bit 0. |
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O |
TXD — Transmitter output for the serial port. |
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P1.1/RXD |
17 |
13 |
I/O |
P1.1 — Port 1 bit 1. |
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I |
RXD — Receiver input for the serial port. |
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P1.2/T0/SCL |
12 |
8 |
I/O |
P1.2 — Port 1 bit 2 (open-drain when used as output). |
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I/O |
T0 — Timer/counter 0 external count input or overflow output (open-drain |
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when used as output). |
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I/O |
SCL — I2C serial clock input/output. |
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
6 of 147 |
Philips Semiconductors |
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UM10116 |
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P89LPC933/934/935/936 User manual |
Table 2: |
Pin description …continued |
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Symbol |
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Pin |
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Description |
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TSSOP28, |
HVQFN28 |
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PLCC28 |
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11 |
7 |
I/O |
P1.3 — Port 1 bit 3 (open-drain when used as output). |
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P1.3/INT0/ |
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SDA |
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I |
INT0 — External interrupt 0 input. |
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I/O |
SDA — I2C serial data input/output. |
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10 |
6 |
I |
P1.4 — Port 1 bit 4. |
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P1.4/INT1 |
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I |
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— External interrupt 1 input.t |
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INT1 |
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6 |
2 |
I |
P1.5 — Port 1 bit 5 (input only). |
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P1.5/RST |
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I |
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— External Reset input during power-on or if selected via UCFG1. |
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RST |
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When functioning as a reset input, a LOW on this pin resets the |
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microcontroller, causing I/O ports and peripherals to take on their default |
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states, and the processor begins execution at address 0. Also used during |
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a power-on sequence to force ISP mode. When using an oscillator |
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frequency above 12 MHz, the reset input function of P1.5 must be |
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enabled. An external circuit is required to hold the device in reset at |
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power-up until VDD has reached its specified level. When system |
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power is removed VDD will fall below the minimum specified |
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operating voltage. When using an oscillator frequency above |
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12 MHz, in some applications, an external brownout detect circuit |
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may be required to hold the device in reset when VDD falls below the |
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minimum specified operating voltage. |
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P1.6/OCB |
5 |
1 |
I/O |
P1.6 — Port 1 bit 6. |
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O |
OCB — Output Compare B. (P89LPC935/936) |
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P1.7/OCC/ |
4 |
28 |
I/O |
P1.7 — Port 1 bit 7. |
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AD00 |
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O |
OCC — Output Compare C. (P89LPC935/936) |
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I |
AD00 — ADC0 channel 0 analog input. (P89LPC935/936) |
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
7 of 147 |
Philips Semiconductors |
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UM10116 |
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P89LPC933/934/935/936 User manual |
Table 2: Pin description …continued |
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Symbol |
Pin |
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Type |
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Description |
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TSSOP28, |
HVQFN28 |
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PLCC28 |
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P2.0 to P2.7 |
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I/O |
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. |
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During reset Port 2 latches are configured in the input only mode with the |
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internal pull-up disabled. The operation of Port 2 pins as inputs and |
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outputs depends upon the port configuration selected. Each port pin is |
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configured independently. Refer to Section 5.1 for details. |
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All pins have Schmitt trigger inputs. |
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Port 2 also provides various special functions as described below: |
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P2.0/ICB/ |
1 |
25 |
I/O |
P2.0 — Port 2 bit 0. |
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DAC0/AD03 |
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I |
ICB — Input Capture B. (P89LPC935/936) |
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I |
DAC0 — Digital-to-analog converter output. |
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I |
AD03 — ADC0 channel 3 analog input. (P89LPC935/936) |
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P2.1/OCD/ |
2 |
26 |
I/O |
P2.1 — Port 2 bit 1. |
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AD02 |
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O |
OCD — Output Compare D. (P89LPC935/936) |
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I |
AD02 — ADC0 channel 2 analog input. (P89LPC935/936) |
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P2.2/MOSI |
13 |
9 |
I/O |
P2.2 — Port 2 bit 2. |
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I/O |
MOSI — SPI master out slave in. When configured as master, this pin is |
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output; when configured as slave, this pin is input. |
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P2.3/MISO |
14 |
10 |
I/O |
P2.3 — Port 2 bit 3. |
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I/O |
MISO — When configured as master, this pin is input, when configured as |
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slave, this pin is output. |
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15 |
11 |
I/O |
P2.4 — Port 2 bit 4. |
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P2.4/SS |
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I |
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— SPI Slave select. |
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SS |
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P2.5/SPICLK |
16 |
12 |
I/O |
P2.5 — Port 2 bit 5. |
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I/O |
SPICLK — SPI clock. When configured as master, this pin is output; when |
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configured as slave, this pin is input. |
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P2.6/OCA |
27 |
23 |
I/O |
P2.6 — Port 2 bit 6. |
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O |
OCA — Output Compare A. (P89LPC935/936) |
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P2.7/ICA |
28 |
24 |
I/O |
P2.7 — Port 2 bit 7. |
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I |
ICA — Input Capture A. (P89LPC935/936) |
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
8 of 147 |
Philips Semiconductors |
|
UM10116 |
||||
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P89LPC933/934/935/936 User manual |
Table 2: Pin description …continued |
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Symbol |
Pin |
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Type |
Description |
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TSSOP28, |
HVQFN28 |
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PLCC28 |
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P3.0 to P3.1 |
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I/O |
Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. |
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During reset Port 3 latches are configured in the input only mode with the |
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internal pull-up disabled. The operation of Port 3 pins as inputs and |
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outputs depends upon the port configuration selected. Each port pin is |
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configured independently. Refer to Section 5.1 for details. |
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All pins have Schmitt trigger inputs. |
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Port 3 also provides various special functions as described below: |
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P3.0/XTAL2/ |
9 |
5 |
I/O |
P3.0 — Port 3 bit 0. |
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CLKOUT |
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O |
XTAL2 — Output from the oscillator amplifier (when a crystal oscillator |
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option is selected via the FLASH configuration. |
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O |
CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - |
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TRIM.6). It can be used if the CPU clock is the internal RC oscillator, |
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watchdog oscillator or external clock input, except when XTAL1/XTAL2 are |
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used to generate clock source for the RTC/system timer. |
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P3.1/XTAL |
8 |
4 |
I/O |
P3.1 — Port 3 bit 1. |
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I |
XTAL1 — Input to the oscillator circuit and internal clock generator circuits |
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(when selected via the FLASH configuration). It can be a port pin if |
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internal RC oscillator or watchdog oscillator is used as the CPU clock |
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source, and if XTAL1/XTAL2 are not used to generate the clock for the |
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RTC/system timer. |
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VSS |
7 |
3 |
I |
Ground: 0 V reference. |
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VDD |
21 |
17 |
I |
Power Supply: This is the power supply voltage for normal operation as |
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well as Idle and Power-down modes. |
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[1] Input/Output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
9 of 147 |
Philips Semiconductors |
UM10116 |
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P89LPC933/934/935/936 User manual |
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1.2.2 Logic symbols
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VDD |
VSS |
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KBI0 |
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CMP2 |
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TXD |
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AD10 |
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KBI1 |
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CIN2B |
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RXD |
SCL |
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AD11 |
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KBI2 |
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CIN2A |
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T0 |
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AD12 |
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KBI3 |
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CIN1B |
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INT0 |
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SDA |
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PORT 0 |
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PORT 1 |
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DAC1 |
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AD13 |
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KBI4 |
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CIN1A |
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INT1 |
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KBI5 |
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CMPREF |
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RST |
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KBI6 |
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CMP1 |
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KBI7 |
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T1 |
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P89LPC933 |
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CLKOUT |
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P89LPC934 |
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XTAL2 |
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PORT 3 |
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DAC0 |
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XTAL1 |
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MOSI |
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MISO |
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PORT 2 |
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SS |
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SPICLK |
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002aab077
Fig 5. P89LPC933/934 logic symbol.
VDD VSS
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AD01 |
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KBI0 |
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CMP2 |
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AD10 |
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KBI1 |
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CIN2B |
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AD11 |
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KBI2 |
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CIN2A |
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AD12 |
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KBI3 |
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CIN1B |
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PORT 0 |
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DAC1 |
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AD13 |
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KBI4 |
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CIN1A |
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KBI5 |
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CMPREF |
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KBI6 |
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CMP1 |
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KBI7 |
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T1 |
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CLKOUT |
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XTAL2 |
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PORT 3 |
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XTAL1
Fig 6. P89LPC935/936 logic symbol.
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TXD |
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RXD |
SCL |
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T0 |
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INT0 |
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SDA |
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PORT 1 |
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INT1 |
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RST |
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OCB |
AD00 |
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P89LPC935 |
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OCC |
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P89LPC936 |
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ICB |
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AD03 |
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DAC0 |
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OCD |
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AD02 |
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MOSI |
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MISO |
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PORT 2 |
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SS |
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SPICLK |
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OCA |
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ICA |
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002aab078 |
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
10 of 147 |
Philips Semiconductors |
UM10116 |
||
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P89LPC933/934/935/936 User manual |
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1.2.3 Block diagram
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P89LPC933/934/935/936 |
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ACCELERATED 2-CLOCK 80C51 CPU |
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4 kb/8 kB/16 kB |
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UART |
TXD |
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RXD |
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CODE FLASH |
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internal bus |
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256-BYTE |
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I2C-BUS |
SCL |
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DATA RAM |
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SDA |
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SPICLK |
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512-BYTE |
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SPI |
MOSI |
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AUXILIARY RAM |
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MISO |
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SS |
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512-BYTE |
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REAL-TIME CLOCK/ |
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DATA EEPROM |
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SYSTEM TIMER |
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(P89LPC935/936) |
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TIMER 0 |
T0 |
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P3[1:0] |
PORT 3 |
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TIMER 1 |
T1 |
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CONFIGURABLE I/Os |
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CMP2 |
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PORT 2 |
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ANALOG |
CIN2B |
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P2[7:0] |
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CIN2A |
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CONFIGURABLE I/Os |
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COMPARATORS |
CMP1 |
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CIN1A |
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P1[7:0] |
PORT 1 |
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CIN1B |
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CONFIGURABLE I/Os |
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OCA |
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PORT 0 |
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CCU (CAPTURE/ |
OCB |
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P0[7:0] |
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COMPARE UNIT) |
OCC |
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CONFIGURABLE I/Os |
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OCD |
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(P89LPC935/936) |
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ICA |
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ICB |
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KEYPAD |
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AD10 |
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INTERRUPT |
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ADC1/DAC1 |
AD11 |
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AD12 |
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WATCHDOG TIMER |
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AD13 |
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DAC1 |
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AND OSCILLATOR |
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AD00 |
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ADC0/DAC0 |
AD01 |
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PROGRAMMABLE |
CPU |
AD02 |
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(P89LPC935/936) |
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OSCILLATOR DIVIDER |
clock |
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AD03 |
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DAC1 |
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CRYSTAL |
X1 |
ON-CHIP |
POWER MONITOR |
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CONFIGURABLE |
(POWER-ON RESET, |
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OR |
RC |
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OSCILLATOR |
BROWNOUT RESET) |
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RESONATOR |
OSCILLATOR |
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X2 |
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002aab070 |
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Fig 7. |
Block diagram. |
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|
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
11 of 147 |
Philips Semiconductors |
UM10116 |
||
|
|
|
P89LPC933/934/935/936 User manual |
|
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|
|
1.3 Special function registers
Remark: SFR accesses are restricted in the following ways:
•User must not attempt to access any SFR locations not defined.
•Accesses to any defined SFR locations must be strictly for the functions for the SFRs.
•SFR bits labeled ‘-’, logic 0 or logic 1 can only be written and read as follows:
–‘-’ Unless otherwise specified, must be written with logic 0, but can return any value when read (even if it was written with logic 0). It is a reserved bit and may be used in future derivatives.
–Logic 0 must be written with logic 0, and will return a logic 0 when read.
–Logic 1 must be written with logic 1, and will return a logic 1 when read.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
12 of 147 |
manual User
2005 March 4 — 01 .Rev
147 of 13
.reserved rights All .2004 .V.N Electronics Philips Koninklijke ©
Table 3: |
Special function registers - P89LPC933/934 |
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|
||
* indicates SFRs that are bit addressable. |
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Name |
Description |
SFR |
Bit functions and addresses |
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Reset value |
|||
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addr. |
MSB |
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LSB |
Hex |
Binary |
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Bit address |
E7 |
E6 |
E5 |
E4 |
E3 |
E2 |
E1 |
E0 |
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ACC* |
Accumulator |
E0H |
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00 |
00000000 |
ADCON0 |
A/D control register 0 |
8EH |
- |
- |
- |
- |
- |
ENADC0 |
- |
- |
00 |
00000000 |
ADCON1 |
A/D control register 1 |
97H |
ENBI1 |
ENADCI |
TMM1 |
EDGE1 |
ADCI1 |
ENADC1 |
ADCS11 |
ADCS10 |
00 |
00000000 |
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1 |
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ADINS |
A/D input select |
A3H |
ADI13 |
ADI12 |
ADI11 |
ADI10 |
- |
- |
- |
- |
00 |
00000000 |
ADMODA |
A/D mode register A |
C0H |
BNDI1 |
BURST1 |
SCC1 |
SCAN1 |
- |
- |
- |
- |
00 |
00000000 |
ADMODB |
A/D mode register B |
A1H |
CLK2 |
CLK1 |
CLK0 |
- |
ENDAC1 |
ENDAC0 |
BSA1 |
- |
00 |
000x0000 |
AD0DAT3 |
A/D_0 data register 3 |
F4H |
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00 |
00000000 |
AD1BH |
A/D_1 boundary high register |
C4H |
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FF |
11111111 |
AD1BL |
A/D_1 boundary low register |
BCH |
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00 |
00000000 |
AD1DAT0 |
A/D_1 data register 0 |
D5H |
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00 |
00000000 |
AD1DAT1 |
A/D_1 data register 1 |
D6H |
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00 |
00000000 |
AD1DAT2 |
A/D_1 data register 2 |
D7H |
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00 |
00000000 |
AD1DAT3 |
A/D_1 data register 3 |
F5H |
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00 |
00000000 |
AUXR1 |
Auxiliary function register |
A2H |
CLKLP |
EBRR |
ENT1 |
ENT0 |
SRST |
0 |
- |
DPS |
00 |
000000x0 |
|
Bit address |
F7 |
F6 |
F5 |
F4 |
F3 |
F2 |
F1 |
F0 |
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B* |
B register |
F0H |
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00 |
00000000 |
BRGR0[2] |
Baud rate generator rate low |
BEH |
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00 |
00000000 |
BRGR1[2] |
Baud rate generator rate high |
BFH |
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|
00 |
00000000 |
BRGCON |
Baud rate generator control |
BDH |
- |
- |
- |
- |
- |
- |
SBRGS |
BRGEN |
00[2] |
xxxxxx00 |
CMP1 |
Comparator 1 control register |
ACH |
- |
- |
CE1 |
CP1 |
CN1 |
OE1 |
CO1 |
CMF1 |
00[1] |
xx000000 |
CMP2 |
Comparator 2 control register |
ADH |
- |
- |
CE2 |
CP2 |
CN2 |
OE2 |
CO2 |
CMF2 |
00[1] |
xx000000 |
DIVM |
CPU clock divide-by-M control |
95H |
|
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|
|
00 |
00000000 |
DPTR |
Data pointer (2 bytes) |
|
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|
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DPH |
Data pointer high |
83H |
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|
00 |
00000000 |
DPL |
Data pointer low |
82H |
|
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|
00 |
00000000 |
FMADRH |
Program Flash address high |
E7H |
|
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|
|
|
|
00 |
00000000 |
FMADRL |
Program Flash address low |
E6H |
|
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|
00 |
00000000 |
|
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|
|
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|
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|
|
|
|
|
Semiconductors Philips
manual User P89LPC933/934/935/936 |
UM10116 |
manual User
2005 March 4 — 01 .Rev
147 of 14
.reserved rights All .2004 .V.N Electronics Philips Koninklijke ©
Table 3: |
Special function registers - P89LPC933/934 …continued |
|
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|
|||
* indicates SFRs that are bit addressable. |
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||
Name |
Description |
SFR |
Bit functions and addresses |
|
|
|
|
|
Reset value |
|||
|
|
addr. |
MSB |
|
|
|
|
|
|
LSB |
Hex |
Binary |
|
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||||
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FMCON |
Program Flash control (Read) |
E4H |
BUSY |
- |
- |
- |
HVA |
HVE |
SV |
OI |
70 |
01110000 |
|
Program Flash control (Write) |
E4H |
FMCMD. |
FMCMD. |
FMCMD. |
FMCMD. FMCMD. FMCMD. FMCMD. FMCMD. |
|
|
||||
|
|
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
FMDATA |
Program Flash data |
E5H |
|
|
|
|
|
|
|
|
00 |
00000000 |
I2ADR |
I2C slave address register |
DBH |
I2ADR.6 |
I2ADR.5 |
I2ADR.4 |
I2ADR.3 |
I2ADR.2 |
I2ADR.1 |
I2ADR.0 |
GC |
00 |
00000000 |
|
Bit address |
DF |
DE |
DD |
DC |
DB |
DA |
D9 |
D8 |
|
|
|
I2CON* |
I2C control register |
D8H |
- |
I2EN |
STA |
STO |
SI |
AA |
- |
CRSEL |
00 |
x00000x0 |
I2DAT |
I2C data register |
DAH |
|
|
|
|
|
|
|
|
|
|
I2SCLH |
Serial clock generator/SCL |
DDH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
duty cycle register high |
|
|
|
|
|
|
|
|
|
|
|
I2SCLL |
Serial clock generator/SCL |
DCH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
duty cycle register low |
|
|
|
|
|
|
|
|
|
|
|
I2STAT |
I2C status register |
D9H |
STA.4 |
STA.3 |
STA.2 |
STA.1 |
STA.0 |
0 |
0 |
0 |
F8 |
11111000 |
ICRAH |
Input capture A register high |
ABH |
|
|
|
|
|
|
|
|
00 |
00000000 |
ICRAL |
Input capture A register low |
AAH |
|
|
|
|
|
|
|
|
00 |
00000000 |
ICRBH |
Input capture B register high |
AFH |
|
|
|
|
|
|
|
|
00 |
00000000 |
ICRBL |
Input capture B register low |
AEH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
Bit address |
AF |
AE |
AD |
AC |
AB |
AA |
A9 |
A8 |
|
|
|
IEN0* |
Interrupt enable 0 |
A8H |
EA |
EWDRT |
EBO |
ES/ESR |
ET1 |
EX1 |
ET0 |
EX0 |
00 |
00000000 |
|
Bit address |
EF |
EE |
ED |
EC |
EB |
EA |
E9 |
E8 |
|
|
|
IEN1* |
Interrupt enable 1 |
E8H |
EAD |
EST |
- |
- |
ESPI |
EC |
EKBI |
EI2C |
00[1] |
00x00000 |
|
Bit address |
BF |
BE |
BD |
BC |
BB |
BA |
B9 |
B8 |
|
|
|
IP0* |
Interrupt priority 0 |
B8H |
- |
PWDRT |
PBO |
PS/PSR |
PT1 |
PX1 |
PT0 |
PX0 |
00[1] |
x0000000 |
IP0H |
Interrupt priority 0 high |
B7H |
- |
PWDRT |
PBOH |
PSH/ |
PT1H |
PX1H |
PT0H |
PX0H |
00[1] |
x0000000 |
|
|
|
|
H |
|
PSRH |
|
|
|
|
|
|
|
Bit address |
FF |
FE |
FD |
FC |
FB |
FA |
F9 |
F8 |
|
|
|
IP1* |
Interrupt priority 1 |
F8H |
PAD |
PST |
- |
- |
PSPI |
PC |
PKBI |
PI2C |
00[1] |
00x00000 |
IP1H |
Interrupt priority 1 high |
F7H |
PADH |
PSTH |
- |
- |
PSPIH |
PCH |
PKBIH |
PI2CH |
00[1] |
00x00000 |
KBCON |
Keypad control register |
94H |
- |
- |
- |
- |
- |
- |
PATN |
KBIF |
00[1] |
xxxxxx00 |
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|
_SEL |
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|
Semiconductors Philips
manual User P89LPC933/934/935/936 |
UM10116 |
manual User
2005 March 4 — 01 .Rev
147 of 15
.reserved rights All .2004 .V.N Electronics Philips Koninklijke ©
Table 3: |
Special function registers - P89LPC933/934 …continued |
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* indicates SFRs that are bit addressable. |
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||||
Name |
Description |
SFR |
Bit functions and addresses |
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Reset value |
|||||
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|
addr. |
MSB |
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LSB |
Hex |
Binary |
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||||
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KBMASK |
Keypad interrupt mask |
86H |
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00 |
00000000 |
|
register |
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KBPATN |
Keypad pattern register |
93H |
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FF |
11111111 |
|
Bit address |
87 |
86 |
85 |
|
84 |
|
|
83 |
|
82 |
81 |
80 |
|
|
|||||
P0* |
Port 0 |
80H |
T1/KB7 |
CMP1 |
CMPREF |
CIN1A |
CIN1B |
CIN2A |
CIN2B |
CMP2 |
|
[1] |
||||||||
|
|
|
|
/KB6 |
/KB5 |
|
/KB4 |
|
/KB3 |
/KB2 |
/KB1 |
/KB0 |
|
|
||||||
|
Bit address |
97 |
96 |
95 |
|
94 |
|
|
93 |
|
92 |
91 |
90 |
|
|
|||||
P1* |
Port 1 |
90H |
- |
- |
|
|
|
|
|
|
|
|
|
|
|
T0/SCL |
RXD |
TXD |
|
[1] |
|
RST |
INT1 |
INT0/ |
|
||||||||||||||||
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SDA |
|
|
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|
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|
Bit address |
A7 |
A6 |
|
A5 |
|
|
A4 |
|
A3 |
A2 |
A1 |
A0 |
|
|
|||||
P2* |
Port 2 |
A0H |
- |
- |
SPICLK |
|
|
|
|
MISO |
MOSI |
- |
- |
|
[1] |
|||||
|
SS |
|
||||||||||||||||||
|
Bit address |
B7 |
B6 |
|
B5 |
|
|
B4 |
|
B3 |
B2 |
B1 |
B0 |
|
|
|||||
P3* |
Port 3 |
B0H |
- |
- |
- |
|
- |
|
|
- |
|
- |
XTAL1 |
XTAL2 |
|
[1] |
||||
P0M1 |
Port 0 output mode 1 |
84H |
(P0M1.7) |
(P0M1.6) |
(P0M1.5) |
(P0M1.4) |
(P0M1.3) |
(P0M1.2) |
(P0M1.1) |
(P0M1.0) |
FF[1] |
11111111 |
||||||||
P0M2 |
Port 0 output mode 2 |
85H |
(P0M2.7) |
(P0M2.6) |
(P0M2.5) |
(P0M2.4) |
(P0M2.3) |
(P0M2.2) |
(P0M2.1) |
(P0M2.0) |
00[1] |
00000000 |
||||||||
P1M1 |
Port 1 output mode 1 |
91H |
(P1M1.7) |
(P1M1.6) |
- |
|
(P1M1.4) |
(P1M1.3) |
(P1M1.2) |
(P1M1.1) |
(P1M1.0) |
D3[1] |
11x1xx11 |
|||||||
P1M2 |
Port 1 output mode 2 |
92H |
(P1M2.7) |
(P1M2.6) |
- |
|
(P1M2.4) |
(P1M2.3) |
(P1M2.2) |
(P1M2.1) |
(P1M2.0) |
00[1] |
00x0xx00 |
|||||||
P2M1 |
Port 2 output mode 1 |
A4H |
(P2M1.7) |
(P2M1.6) |
(P2M1.5) |
(P2M1.4) |
(P2M1.3) |
(P2M1.2) |
(P2M1.1) |
(P2M1.0) |
FF[1] |
11111111 |
||||||||
P2M2 |
Port 2 output mode 2 |
A5H |
(P2M2.7) |
(P2M2.6) |
(P2M2.5) |
(P2M2.4) |
(P2M2.3) |
(P2M2.2) |
(P2M2.1) |
(P2M2.0) |
00[1] |
00000000 |
||||||||
P3M1 |
Port 3 output mode 1 |
B1H |
- |
- |
- |
|
- |
|
|
- |
|
- |
(P3M1.1) |
(P3M1.0) |
03[1] |
xxxxxx11 |
||||
P3M2 |
Port 3 output mode 2 |
B2H |
- |
- |
- |
|
- |
|
|
- |
|
- |
(P3M2.1) |
(P3M2.0) |
00[1] |
xxxxxx00 |
||||
PCON |
Power control register |
87H |
SMOD1 |
SMOD0 |
BOPD |
|
BOI |
|
GF1 |
GF0 |
PMOD1 |
PMOD0 |
00 |
00000000 |
||||||
PCONA |
Power control register A |
B5H |
RTCPD |
- |
VCPD |
ADPD |
|
I2PD |
SPPD |
SPD |
- |
00[1] |
00000000 |
|||||||
|
Bit address |
D7 |
D6 |
|
D5 |
|
|
D4 |
|
D3 |
D2 |
D1 |
D0 |
|
|
|||||
PSW* |
Program status word |
D0H |
CY |
AC |
|
F0 |
|
RS1 |
|
RS0 |
OV |
F1 |
P |
00 |
00000000 |
|||||
PT0AD |
Port 0 digital input disable |
F6H |
- |
- |
PT0AD.5 |
PT0AD.4 |
PT0AD.3 |
PT0AD.2 |
PT0AD.1 |
- |
00 |
xx00000x |
||||||||
RSTSRC |
Reset source register |
DFH |
- |
- |
BOF |
|
POF |
R_BK |
R_WD |
R_SF |
R_EX |
|
[3] |
|||||||
RTCCON |
Real-time clock control |
D1H |
RTCF |
RTCS1 |
RTCS0 |
- |
|
|
- |
|
- |
ERTC |
RTCEN |
60[1][6] |
011xxx00 |
|||||
RTCH |
Real-time clock register high |
D2H |
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
00[6] |
00000000 |
RTCL |
Real-time clock register low |
D3H |
|
|
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|
|
|
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|
|
|
|
|
|
|
|
00[6] |
00000000 |
Semiconductors Philips
manual User P89LPC933/934/935/936 |
UM10116 |
manual User
2005 March 4 — 01 .Rev
147 of 16
.reserved rights All .2004 .V.N Electronics Philips Koninklijke ©
Table 3: |
Special function registers - P89LPC933/934 …continued |
|
|
|
|
|
|
|
|
|
|||
* indicates SFRs that are bit addressable. |
|
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|||
Name |
Description |
SFR |
Bit functions and addresses |
|
|
|
|
|
Reset value |
||||
|
|
addr. |
MSB |
|
|
|
|
|
|
LSB |
Hex |
|
Binary |
|
|
|
|
|
|
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|
||||
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|
|
|
|
SADDR |
Serial port address register |
A9H |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
SADEN |
Serial port address enable |
B9H |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
SBUF |
Serial Port data buffer register |
99H |
|
|
|
|
|
|
|
|
xx |
|
xxxxxxxx |
|
Bit address |
9F |
9E |
9D |
9C |
9B |
9A |
99 |
98 |
|
|
|
|
SCON* |
Serial port control |
98H |
SM0/FE |
SM1 |
SM2 |
REN |
TB8 |
RB8 |
TI |
RI |
00 |
00000000 |
|
SSTAT |
Serial port extended status |
BAH |
DBMOD |
INTLO |
CIDIS |
DBISEL |
FE |
BR |
OE |
STINT |
00 |
00000000 |
|
|
register |
|
|
|
|
|
|
|
|
|
|
|
|
SP |
Stack pointer |
81H |
|
|
|
|
|
|
|
|
07 |
00000111 |
|
SPCTL |
SPI control register |
E2H |
SSIG |
SPEN |
DORD |
MSTR |
CPOL |
CPHA |
SPR1 |
SPR0 |
04 |
00000100 |
|
SPSTAT |
SPI status register |
E1H |
SPIF |
WCOL |
- |
- |
- |
- |
- |
- |
00 |
|
00xxxxxx |
SPDAT |
SPI data register |
E3H |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
TAMOD |
Timer 0 and 1 auxiliary mode |
8FH |
- |
- |
- |
T1M2 |
- |
- |
- |
T0M2 |
00 |
|
xxx0xxx0 |
|
Bit address |
8F |
8E |
8D |
8C |
8B |
8A |
89 |
88 |
|
|
|
|
TCON* |
Timer 0 and 1 control |
88H |
TF1 |
TR1 |
TF0 |
TR0 |
IE1 |
IT1 |
IE0 |
IT0 |
00 |
00000000 |
|
TH0 |
Timer 0 high |
8CH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
TH1 |
Timer 1 high |
8DH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
TL0 |
Timer 0 low |
8AH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
TL1 |
Timer 1 low |
8BH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
TMOD |
Timer 0 and 1 mode |
89H |
T1GATE |
T1C/T |
T1M1 |
T1M0 |
T0GATE |
T0C/T |
T0M1 |
T0M0 |
00 |
00000000 |
|
TRIM |
Internal oscillator trim register |
96H |
RCCLK |
ENCLK |
TRIM.5 |
TRIM.4 |
TRIM.3 |
TRIM.2 |
TRIM.1 |
TRIM.0 |
|
[5] [6] |
|
WDCON |
Watchdog control register |
A7H |
PRE2 |
PRE1 |
PRE0 |
- |
- |
WDRUN |
WDTOF |
WDCLK |
|
[4] [6] |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Semiconductors Philips
manual User P89LPC933/934/935/936 |
UM10116 |
manual User
2005 March 4 — 01 .Rev
147 of 17
.reserved rights All .2004 .V.N Electronics Philips Koninklijke ©
Table 3: |
Special function registers - P89LPC933/934 …continued |
|
|
|
||
* indicates SFRs that are bit addressable. |
|
|
|
|
|
|
|
|
|
|
|
|
|
Name |
Description |
SFR |
Bit functions and addresses |
|
Reset value |
|
|
|
addr. |
MSB |
LSB |
Hex |
Binary |
|
|
|
||||
|
|
|
|
|
|
|
WDL |
Watchdog load |
C1H |
|
|
FF |
11111111 |
WFEED1 |
Watchdog feed 1 |
C2H |
|
|
|
|
WFEED2 |
Watchdog feed 2 |
C3H |
|
|
|
|
|
|
|
|
|
|
|
[1]All ports are in input only (high-impedance) state after power-up.
[2]BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[3]The RSTSRC register reflects the cause of the UM10116 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx110000.
[4]After reset, the value is 111001x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF.
[5]On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6]The only reset source that affects these SFRs is power-on reset.
Semiconductors Philips
manual User P89LPC933/934/935/936 |
UM10116 |
manual User
2005 March 4 — 01 .Rev
147 of 18
.reserved rights All .2004 .V.N Electronics Philips Koninklijke ©
Table 4: |
Special function registers - P89LPC935/936 |
|
|
|
|
|
|
|
|
|
||
* indicates SFRs that are bit addressable. |
|
|
|
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|
|
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|
|
|
|
|
|
|
|
|
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|
|
|
|
||
Name |
Description |
SFR |
Bit functions and addresses |
|
|
|
|
|
Reset value |
|||
|
|
addr. |
MSB |
|
|
|
|
|
|
LSB |
Hex |
Binary |
|
|
|
|
|
|
|
|
|
||||
|
Bit address |
E7 |
E6 |
E5 |
E4 |
E3 |
E2 |
E1 |
E0 |
|
|
|
ACC* |
Accumulator |
E0H |
|
|
|
|
|
|
|
|
00 |
00000000 |
ADCON0 |
A/D control register 0 |
8EH |
ENBI0 |
ENADCI |
TMM0 |
EDGE0 |
ADCI0 |
ENADC0 |
ADCS01 |
ADCS00 |
00 |
00000000 |
|
|
|
|
0 |
|
|
|
|
|
|
|
|
ADCON1 |
A/D control register 1 |
97H |
ENBI1 |
ENADCI |
TMM1 |
EDGE1 |
ADCI1 |
ENADC1 |
ADCS11 |
ADCS10 |
00 |
00000000 |
|
|
|
|
1 |
|
|
|
|
|
|
|
|
ADINS |
A/D input select |
A3H |
ADI13 |
ADI12 |
ADI11 |
ADI10 |
ADI03 |
ADI02 |
ADI01 |
ADI00 |
00 |
00000000 |
ADMODA |
A/D mode register A |
C0H |
BNDI1 |
BURST1 |
SCC1 |
SCAN1 |
BNDI0 |
BURST0 |
SCC0 |
SCAN0 |
00 |
00000000 |
ADMODB |
A/D mode register B |
A1H |
CLK2 |
CLK1 |
CLK0 |
- |
ENDAC1 |
ENDAC0 |
BSA1 |
BSA0 |
00 |
000x0000 |
AD0BH |
A/D_0 boundary high register |
BBH |
|
|
|
|
|
|
|
|
FF |
11111111 |
AD0BL |
A/D_0 boundary low register |
A6H |
|
|
|
|
|
|
|
|
00 |
00000000 |
AD0DAT0 |
A/D_0 data register 0 |
C5H |
|
|
|
|
|
|
|
|
00 |
00000000 |
AD0DAT1 |
A/D_0 data register 1 |
C6H |
|
|
|
|
|
|
|
|
00 |
00000000 |
AD0DAT2 |
A/D_0 data register 2 |
C7H |
|
|
|
|
|
|
|
|
00 |
00000000 |
AD0DAT3 |
A/D_0 data register 3 |
F4H |
|
|
|
|
|
|
|
|
00 |
00000000 |
AD1BH |
A/D_1 boundary high register |
C4H |
|
|
|
|
|
|
|
|
FF |
11111111 |
AD1BL |
A/D_1 boundary low register |
BCH |
|
|
|
|
|
|
|
|
00 |
00000000 |
AD1DAT0 |
A/D_1 data register 0 |
D5H |
|
|
|
|
|
|
|
|
00 |
00000000 |
AD1DAT1 |
A/D_1 data register 1 |
D6H |
|
|
|
|
|
|
|
|
00 |
00000000 |
AD1DAT2 |
A/D_1 data register 2 |
D7H |
|
|
|
|
|
|
|
|
00 |
00000000 |
AD1DAT3 |
A/D_1 data register 3 |
F5H |
|
|
|
|
|
|
|
|
00 |
00000000 |
AUXR1 |
Auxiliary function register |
A2H |
CLKLP |
EBRR |
ENT1 |
ENT0 |
SRST |
0 |
- |
DPS |
00 |
000000x0 |
|
Bit address |
F7 |
F6 |
F5 |
F4 |
F3 |
F2 |
F1 |
F0 |
|
|
|
B* |
B register |
F0H |
|
|
|
|
|
|
|
|
00 |
00000000 |
BRGR0[2] |
Baud rate generator rate low |
BEH |
|
|
|
|
|
|
|
|
00 |
00000000 |
BRGR1[2] |
Baud rate generator rate high |
BFH |
|
|
|
|
|
|
|
|
00 |
00000000 |
BRGCON |
Baud rate generator control |
BDH |
- |
- |
- |
- |
- |
- |
SBRGS |
BRGEN |
00[2] |
xxxxxx00 |
CCCRA |
Capture compare A control |
EAH |
ICECA2 |
ICECA1 |
ICECA0 |
ICESA |
ICNFA |
FCOA |
OCMA1 |
OCMA0 |
00 |
00000000 |
|
register |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Semiconductors Philips
manual User P89LPC933/934/935/936 |
UM10116 |
manual User
2005 March 4 — 01 .Rev
147 of 19
.reserved rights All .2004 .V.N Electronics Philips Koninklijke ©
Table 4: |
Special function registers - P89LPC935/936 …continued |
|
|
|
|
|
|
|
|
|||
* indicates SFRs that are bit addressable. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Name |
Description |
SFR |
Bit functions and addresses |
|
|
|
|
|
Reset value |
|||
|
|
addr. |
MSB |
|
|
|
|
|
|
LSB |
Hex |
Binary |
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
CCCRB |
Capture compare B control |
EBH |
ICECB2 |
ICECB1 |
ICECB0 |
ICESB |
ICNFB |
FCOB |
OCMB1 |
OCMB0 |
00 |
00000000 |
|
register |
|
|
|
|
|
|
|
|
|
|
|
CCCRC |
Capture compare C control |
ECH |
- |
- |
- |
- |
- |
FCOC |
OCMC1 |
OCMC0 |
00 |
xxxxx000 |
|
register |
|
|
|
|
|
|
|
|
|
|
|
CCCRD |
Capture compare D control |
EDH |
- |
- |
- |
- |
- |
FCOD |
OCMD1 |
OCMD0 |
00 |
xxxxx000 |
|
register |
|
|
|
|
|
|
|
|
|
|
|
CMP1 |
Comparator 1 control register |
ACH |
- |
- |
CE1 |
CP1 |
CN1 |
OE1 |
CO1 |
CMF1 |
00[1] |
xx000000 |
CMP2 |
Comparator 2 control register |
ADH |
- |
- |
CE2 |
CP2 |
CN2 |
OE2 |
CO2 |
CMF2 |
00[1] |
xx000000 |
DEECON |
Data EEPROM control |
F1H |
EEIF |
HVERR |
ECTL1 |
ECTL0 |
- |
- |
- |
EADR8 |
0E |
00001110 |
|
register |
|
|
|
|
|
|
|
|
|
|
|
DEEDAT |
Data EEPROM data register |
F2H |
|
|
|
|
|
|
|
|
00 |
00000000 |
DEEADR |
Data EEPROM address |
F3H |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
register |
|
|
|
|
|
|
|
|
|
|
|
DIVM |
CPU clock divide-by-M control |
95H |
|
|
|
|
|
|
|
|
00 |
00000000 |
DPTR |
Data pointer (2 bytes) |
|
|
|
|
|
|
|
|
|
|
|
DPH |
Data pointer high |
83H |
|
|
|
|
|
|
|
|
00 |
00000000 |
DPL |
Data pointer low |
82H |
|
|
|
|
|
|
|
|
00 |
00000000 |
FMADRH |
Program Flash address high |
E7H |
|
|
|
|
|
|
|
|
00 |
00000000 |
FMADRL |
Program Flash address low |
E6H |
|
|
|
|
|
|
|
|
00 |
00000000 |
FMCON |
Program Flash control (Read) |
E4H |
BUSY |
- |
- |
- |
HVA |
HVE |
SV |
OI |
70 |
01110000 |
|
Program Flash control (Write) |
E4H |
FMCMD. |
FMCMD. FMCMD. FMCMD. |
FMCMD. |
FMCMD. |
FMCMD. |
FMCMD. |
|
|
||
|
|
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
FMDATA |
Program Flash data |
E5H |
|
|
|
|
|
|
|
|
00 |
00000000 |
I2ADR |
I2C slave address register |
DBH |
I2ADR.6 |
I2ADR.5 |
I2ADR.4 |
I2ADR.3 |
I2ADR.2 |
I2ADR.1 |
I2ADR.0 |
GC |
00 |
00000000 |
|
Bit address |
DF |
DE |
DD |
DC |
DB |
DA |
D9 |
D8 |
|
|
|
I2CON* |
I2C control register |
D8H |
- |
I2EN |
STA |
STO |
SI |
AA |
- |
CRSEL |
00 |
x00000x0 |
I2DAT |
I2C data register |
DAH |
|
|
|
|
|
|
|
|
|
|
I2SCLH |
Serial clock generator/SCL |
DDH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
duty cycle register high |
|
|
|
|
|
|
|
|
|
|
|
I2SCLL |
Serial clock generator/SCL |
DCH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
duty cycle register low |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Semiconductors Philips
manual User P89LPC933/934/935/936 |
UM10116 |
manual User
2005 March 4 — 01 .Rev
147 of 20
.reserved rights All .2004 .V.N Electronics Philips Koninklijke ©
Table 4: |
Special function registers - P89LPC935/936 …continued |
|
|
|
|
|
|
|
|
|||
* indicates SFRs that are bit addressable. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Name |
Description |
SFR |
Bit functions and addresses |
|
|
|
|
|
Reset value |
|||
|
|
addr. |
MSB |
|
|
|
|
|
|
LSB |
Hex |
Binary |
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
I2STAT |
I2C status register |
D9H |
STA.4 |
STA.3 |
STA.2 |
STA.1 |
STA.0 |
0 |
0 |
0 |
F8 |
11111000 |
ICRAH |
Input capture A register high |
ABH |
|
|
|
|
|
|
|
|
00 |
00000000 |
ICRAL |
Input capture A register low |
AAH |
|
|
|
|
|
|
|
|
00 |
00000000 |
ICRBH |
Input capture B register high |
AFH |
|
|
|
|
|
|
|
|
00 |
00000000 |
ICRBL |
Input capture B register low |
AEH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
Bit address |
AF |
AE |
AD |
AC |
AB |
AA |
A9 |
A8 |
|
|
|
IEN0* |
Interrupt enable 0 |
A8H |
EA |
EWDRT |
EBO |
ES/ESR |
ET1 |
EX1 |
ET0 |
EX0 |
00 |
00000000 |
|
Bit address |
EF |
EE |
ED |
EC |
EB |
EA |
E9 |
E8 |
|
|
|
IEN1* |
Interrupt enable 1 |
E8H |
EADEE |
EST |
- |
ECCU |
ESPI |
EC |
EKBI |
EI2C |
00[1] |
00x00000 |
|
Bit address |
BF |
BE |
BD |
BC |
BB |
BA |
B9 |
B8 |
|
|
|
IP0* |
Interrupt priority 0 |
B8H |
- |
PWDRT |
PBO |
PS/PSR |
PT1 |
PX1 |
PT0 |
PX0 |
00[1] |
x0000000 |
IP0H |
Interrupt priority 0 high |
B7H |
- |
PWDRT |
PBOH |
PSH/ |
PT1H |
PX1H |
PT0H |
PX0H |
00[1] |
x0000000 |
|
|
|
|
H |
|
PSRH |
|
|
|
|
|
|
|
Bit address |
FF |
FE |
FD |
FC |
FB |
FA |
F9 |
F8 |
|
|
|
IP1* |
Interrupt priority 1 |
F8H |
PADEE |
PST |
- |
PCCU |
PSPI |
PC |
PKBI |
PI2C |
00[1] |
00x00000 |
IP1H |
Interrupt priority 1 high |
F7H |
PAEEH |
PSTH |
- |
PCCUH |
PSPIH |
PCH |
PKBIH |
PI2CH |
00[1] |
00x00000 |
KBCON |
Keypad control register |
94H |
- |
- |
- |
- |
- |
- |
PATN |
KBIF |
00[1] |
xxxxxx00 |
|
|
|
|
|
|
|
|
|
_SEL |
|
|
|
KBMASK |
Keypad interrupt mask |
86H |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
register |
|
|
|
|
|
|
|
|
|
|
|
KBPATN |
Keypad pattern register |
93H |
|
|
|
|
|
|
|
|
FF |
11111111 |
OCRAH |
Output compare A register |
EFH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
high |
|
|
|
|
|
|
|
|
|
|
|
OCRAL |
Output compare A register |
EEH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
low |
|
|
|
|
|
|
|
|
|
|
|
OCRBH |
Output compare B register |
FBH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
high |
|
|
|
|
|
|
|
|
|
|
|
OCRBL |
Output compare B register |
FAH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
low |
|
|
|
|
|
|
|
|
|
|
|
OCRCH |
Output compare C register |
FDH |
|
|
|
|
|
|
|
|
00 |
00000000 |
|
high |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Semiconductors Philips
manual User P89LPC933/934/935/936 |
UM10116 |
manual User
2005 March 4 — 01 .Rev
147 of 21
.reserved rights All .2004 .V.N Electronics Philips Koninklijke ©
Table 4: |
Special function registers - P89LPC935/936 …continued |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
* indicates SFRs that are bit addressable. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
Name |
Description |
SFR |
Bit functions and addresses |
|
|
|
|
|
|
|
|
|
|
|
Reset value |
|||||
|
|
addr. |
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
Hex |
Binary |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OCRCL |
Output compare C register |
FCH |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
00 |
00000000 |
|
low |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OCRDH |
Output compare D register |
FFH |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
00 |
00000000 |
|
high |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OCRDL |
Output compare D register |
FEH |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
00 |
00000000 |
|
low |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Bit address |
87 |
86 |
85 |
|
84 |
|
|
83 |
|
82 |
81 |
80 |
|
|
|||||
P0* |
Port 0 |
80H |
T1/KB7 |
CMP1 |
CMPREF |
CIN1A |
CIN1B |
CIN2A |
CIN2B |
CMP2 |
|
[1] |
||||||||
|
|
|
|
/KB6 |
/KB5 |
|
/KB4 |
|
/KB3 |
/KB2 |
/KB1 |
/KB0 |
|
|
||||||
|
Bit address |
97 |
96 |
95 |
|
94 |
|
|
93 |
|
92 |
91 |
90 |
|
|
|||||
P1* |
Port 1 |
90H |
OCC |
OCB |
|
|
|
|
|
|
|
|
|
|
|
T0/SCL |
RXD |
TXD |
|
[1] |
|
RST |
INT1 |
INT0/ |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SDA |
|
|
|
|
|
|
|
Bit address |
A7 |
A6 |
|
A5 |
|
|
A4 |
|
A3 |
A2 |
A1 |
A0 |
|
|
|||||
P2* |
Port 2 |
A0H |
ICA |
OCA |
SPICLK |
|
|
|
|
MISO |
MOSI |
OCD |
ICB |
|
[1] |
|||||
|
SS |
|
||||||||||||||||||
|
Bit address |
B7 |
B6 |
|
B5 |
|
|
B4 |
|
B3 |
B2 |
B1 |
B0 |
|
|
|||||
P3* |
Port 3 |
B0H |
- |
- |
- |
|
- |
|
|
- |
|
- |
XTAL1 |
XTAL2 |
|
[1] |
||||
P0M1 |
Port 0 output mode 1 |
84H |
(P0M1.7) |
(P0M1.6) |
(P0M1.5) |
(P0M1.4) |
(P0M1.3) |
(P0M1.2) |
(P0M1.1) |
(P0M1.0) |
FF[1] |
11111111 |
||||||||
P0M2 |
Port 0 output mode 2 |
85H |
(P0M2.7) |
(P0M2.6) |
(P0M2.5) |
(P0M2.4) |
(P0M2.3) |
(P0M2.2) |
(P0M2.1) |
(P0M2.0) |
00[1] |
00000000 |
||||||||
P1M1 |
Port 1 output mode 1 |
91H |
(P1M1.7) |
(P1M1.6) |
- |
|
(P1M1.4) |
(P1M1.3) |
(P1M1.2) |
(P1M1.1) |
(P1M1.0) |
D3[1] |
11x1xx11 |
|||||||
P1M2 |
Port 1 output mode 2 |
92H |
(P1M2.7) |
(P1M2.6) |
- |
|
(P1M2.4) |
(P1M2.3) |
(P1M2.2) |
(P1M2.1) |
(P1M2.0) |
00[1] |
00x0xx00 |
|||||||
P2M1 |
Port 2 output mode 1 |
A4H |
(P2M1.7) |
(P2M1.6) |
(P2M1.5) |
(P2M1.4) |
(P2M1.3) |
(P2M1.2) |
(P2M1.1) |
(P2M1.0) |
FF[1] |
11111111 |
||||||||
P2M2 |
Port 2 output mode 2 |
A5H |
(P2M2.7) |
(P2M2.6) |
(P2M2.5) |
(P2M2.4) |
(P2M2.3) |
(P2M2.2) |
(P2M2.1) |
(P2M2.0) |
00[1] |
00000000 |
||||||||
P3M1 |
Port 3 output mode 1 |
B1H |
- |
- |
- |
|
- |
|
|
- |
|
- |
(P3M1.1) |
(P3M1.0) |
03[1] |
xxxxxx11 |
||||
P3M2 |
Port 3 output mode 2 |
B2H |
- |
- |
- |
|
- |
|
|
- |
|
- |
(P3M2.1) |
(P3M2.0) |
00[1] |
xxxxxx00 |
||||
PCON |
Power control register |
87H |
SMOD1 |
SMOD0 |
BOPD |
|
BOI |
|
GF1 |
GF0 |
PMOD1 |
PMOD0 |
00 |
00000000 |
||||||
PCONA |
Power control register A |
B5H |
RTCPD |
DEEPD |
VCPD |
ADPD |
|
I2PD |
SPPD |
SPD |
CCUPD |
00[1] |
00000000 |
|||||||
|
Bit address |
D7 |
D6 |
|
D5 |
|
|
D4 |
|
D3 |
D2 |
D1 |
D0 |
|
|
|||||
PSW* |
Program status word |
D0H |
CY |
AC |
|
F0 |
|
RS1 |
|
RS0 |
OV |
F1 |
P |
00 |
00000000 |
|||||
PT0AD |
Port 0 digital input disable |
F6H |
- |
- |
PT0AD.5 |
PT0AD.4 |
PT0AD.3 |
PT0AD.2 |
PT0AD.1 |
- |
00 |
xx00000x |
||||||||
RSTSRC |
Reset source register |
DFH |
- |
- |
BOF |
|
POF |
R_BK |
R_WD |
R_SF |
R_EX |
|
[3] |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Semiconductors Philips
manual User P89LPC933/934/935/936 |
UM10116 |
manual User
2005 March 4 — 01 .Rev
147 of 22
.reserved rights All .2004 .V.N Electronics Philips Koninklijke ©
Table 4: |
Special function registers - P89LPC935/936 …continued |
|
|
|
|
|
|
|
|
|||
* indicates SFRs that are bit addressable. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Name |
Description |
SFR |
Bit functions and addresses |
|
|
|
|
|
Reset value |
|||
|
|
addr. |
MSB |
|
|
|
|
|
|
LSB |
Hex |
Binary |
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
RTCCON |
Real-time clock control |
D1H |
RTCF |
RTCS1 |
RTCS0 |
- |
- |
- |
ERTC |
RTCEN |
60[1][6] |
011xxx00 |
RTCH |
Real-time clock register high |
D2H |
|
|
|
|
|
|
|
|
00[6] |
00000000 |
RTCL |
Real-time clock register low |
D3H |
|
|
|
|
|
|
|
|
00[6] |
00000000 |
SADDR |
Serial port address register |
A9H |
|
|
|
|
|
|
|
|
00 |
00000000 |
SADEN |
Serial port address enable |
B9H |
|
|
|
|
|
|
|
|
00 |
00000000 |
SBUF |
Serial Port data buffer register |
99H |
|
|
|
|
|
|
|
|
xx |
xxxxxxxx |
|
Bit address |
9F |
9E |
9D |
9C |
9B |
9A |
99 |
98 |
|
|
|
SCON* |
Serial port control |
98H |
SM0/FE |
SM1 |
SM2 |
REN |
TB8 |
RB8 |
TI |
RI |
00 |
00000000 |
SSTAT |
Serial port extended status |
BAH |
DBMOD |
INTLO |
CIDIS |
DBISEL |
FE |
BR |
OE |
STINT |
00 |
00000000 |
|
register |
|
|
|
|
|
|
|
|
|
|
|
SP |
Stack pointer |
81H |
|
|
|
|
|
|
|
|
07 |
00000111 |
SPCTL |
SPI control register |
E2H |
SSIG |
SPEN |
DORD |
MSTR |
CPOL |
CPHA |
SPR1 |
SPR0 |
04 |
00000100 |
SPSTAT |
SPI status register |
E1H |
SPIF |
WCOL |
- |
- |
- |
- |
- |
- |
00 |
00xxxxxx |
SPDAT |
SPI data register |
E3H |
|
|
|
|
|
|
|
|
00 |
00000000 |
TAMOD |
Timer 0 and 1 auxiliary mode |
8FH |
- |
- |
- |
T1M2 |
- |
- |
- |
T0M2 |
00 |
xxx0xxx0 |
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Bit address |
8F |
8E |
8D |
8C |
8B |
8A |
89 |
88 |
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TCON* |
Timer 0 and 1 control |
88H |
TF1 |
TR1 |
TF0 |
TR0 |
IE1 |
IT1 |
IE0 |
IT0 |
00 |
00000000 |
TCR20* |
CCU control register 0 |
C8H |
PLEEN |
HLTRN |
HLTEN |
ALTCD |
ALTAB |
TDIR2 |
TMOD21 |
TMOD20 |
00 |
00000000 |
TCR21 |
CCU control register 1 |
F9H |
TCOU2 |
- |
- |
- |
PLLDV.3 |
PLLDV.2 |
PLLDV.1 |
PLLDV.0 |
00 |
0xxx0000 |
TH0 |
Timer 0 high |
8CH |
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00 |
00000000 |
TH1 |
Timer 1 high |
8DH |
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00 |
00000000 |
TH2 |
CCU timer high |
CDH |
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00 |
00000000 |
TICR2 |
CCU interrupt control register |
C9H |
TOIE2 |
TOCIE2 |
TOCIE2 |
TOCIE2B |
TOCIE2A |
- |
TICIE2B |
TICIE2A |
00 |
00000x00 |
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D |
C |
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TIFR2 |
CCU interrupt flag register |
E9H |
TOIF2 |
TOCF2D |
TOCF2C |
TOCF2B |
TOCF2A |
- |
TICF2B |
TICF2A |
00 |
00000x00 |
TISE2 |
CCU interrupt status encode |
DEH |
- |
- |
- |
- |
- |
ENCINT. |
ENCINT. |
ENCINT. |
00 |
xxxxx000 |
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2 |
1 |
0 |
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TL0 |
Timer 0 low |
8AH |
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00 |
00000000 |
TL1 |
Timer 1 low |
8BH |
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00 |
00000000 |
TL2 |
CCU timer low |
CCH |
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00 |
00000000 |
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Semiconductors Philips
manual User P89LPC933/934/935/936 |
UM10116 |
manual User
2005 March 4 — 01 .Rev
147 of 23
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Table 4: |
Special function registers - P89LPC935/936 …continued |
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* indicates SFRs that are bit addressable. |
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Name |
Description |
SFR |
Bit functions and addresses |
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Reset value |
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addr. |
MSB |
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LSB |
Hex |
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Binary |
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Semiconductors |
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TMOD |
Timer 0 and 1 mode |
89H |
T1GATE |
T1C/T |
T1M1 |
T1M0 |
T0GATE |
T0C/T |
T0M1 |
T0M0 |
00 |
00000000 |
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TOR2H |
CCU reload register high |
CFH |
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00 |
00000000 |
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TOR2L |
CCU reload register low |
CEH |
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00 |
00000000 |
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TPCR2H |
Prescaler control register high |
CBH |
- |
- |
- |
- |
- |
- |
TPCR2H. |
TPCR2H. |
00 |
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xxxxxx00 |
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1 |
0 |
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TPCR2L |
Prescaler control register low |
CAH |
TPCR2L. TPCR2L. TPCR2L. TPCR2L. |
TPCR2L. |
TPCR2L. |
TPCR2L. |
TPCR2L. |
00 |
00000000 |
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7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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TRIM |
Internal oscillator trim register |
96H |
RCCLK |
ENCLK |
TRIM.5 |
TRIM.4 |
TRIM.3 |
TRIM.2 |
TRIM.1 |
TRIM.0 |
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[5] [6] |
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WDCON |
Watchdog control register |
A7H |
PRE2 |
PRE1 |
PRE0 |
- |
- |
WDRUN |
WDTOF |
WDCLK |
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[4] [6] |
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WDL |
Watchdog load |
C1H |
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FF |
11111111 |
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WFEED1 |
Watchdog feed 1 |
C2H |
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WFEED2 |
Watchdog feed 2 |
C3H |
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[1] All ports are in input only (high-impedance) state after power-up. |
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[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. |
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[3] The RSTSRC register reflects the cause of the UM10116 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is |
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xx110000. |
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[4] After reset, the value is 111001x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. |
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Other resets will not affect WDTOF. |
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[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. |
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manualUserP89LPC933/934/935/936 |
UM10116 |
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.reservedrightsAll.2004.V.NElectronicsPhilips Koninklijke © |
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[6] The only reset source that affects these SFRs is power-on reset. |
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Philips Semiconductors |
UM10116 |
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P89LPC933/934/935/936 User manual |
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1.4 Memory organization |
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FF00h |
IAP entry- |
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FFEFh |
points |
ISP CODE 1FFFh (512B)(1)
1E00h
SECTOR 7
1C00h
1BFFh
SECTOR 6
1800h
17FFh
SECTOR 5
1400h
13FFh
SECTOR 4
1000h
0FFFh
SECTOR 3
0C00h
0BFFh
SECTOR 2
0800h
07FFh
SECTOR 1
0400h
03FFh
SECTOR 0
0000h
read-protected IAP calls only
IDATA routines entry points for:
-51 ASM. code -C code
ISP serial loader entry points for:
-UART (auto-baud) -I2C, SPI, etc.(1)
FFEFh |
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SPECIAL FUNCTION |
IDATA (incl. DATA) |
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FF1Fh |
entry |
128 BYTES ON-CHIP |
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REGISTERS |
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DATA MEMORY (STACK |
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points |
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(DIRECTLY ADDRESSABLE) |
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FF00h |
AND INDIR. ADDR.) |
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DATA |
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1FFFh |
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128 BYTES ON-CHIP |
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DATA MEMORY (STACK, |
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DIRECT AND INDIR. ADDR.) |
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4 REG. BANKS R[7:0] |
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1E00h |
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data memory |
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(DATA, IDATA) |
002aab228
(1) ISP code located in Sector 3 for the P89LPC933 device.
Fig 8. P89LPC933/934/935/936 memory map.
1.5 Memory organization
The various P89LPC933/934/935/936 memory spaces are as follows:
•DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.
•IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.
•SFR
Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
•XDATA (P89LPC935/936)
‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC935/936 has 512 bytes of on-chip XDATA memory.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
24 of 147 |
Philips Semiconductors |
UM10116 |
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P89LPC933/934/935/936 User manual |
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•CODE
64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The UM10116 have 4 KB/8 kB/16 kB of on-chip Code memory.
The P89LPC935/936 also has 512 bytes of on-chip Data EEPROM that is accessed via SFRs (see Section 18 “Data EEPROM (P89LPC935/936)”).
2. Clocks
2.1 Enhanced CPU
The P89LPC933/934/935/936 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.
2.2 Clock definitions
The P89LPC933/934/935/936 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources and can also be optionally divided to a slower frequency (see Figure 10 and Section 2.8 “CPU Clock (CCLK) modification: DIVM register”). Note: fosc is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).
RCCLK — The internal 7.373 MHz RC oscillator output.
PCLK — Clock for the various peripheral devices and is CCLK⁄2.
2.2.1Oscillator Clock (OSCCLK)
The P89LPC933/934/935/936 provides several user-selectable oscillator options. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.
2.2.2Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.
2.2.3Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.
2.2.4High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
25 of 147 |
Philips Semiconductors |
UM10116 |
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P89LPC933/934/935/936 User manual |
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is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.
2.3 Clock output
The P89LPC933/934/935/936 supports a user-selectable clock output function on the XTAL2 / CLKOUT pin when the crystal oscillator is not being used. This condition occurs if a different clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-time Clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC933/934/935/936. This output is enabled by the ENCLK bit in the TRIM register
The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of other bits of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.
2.4 On-chip RC oscillator option
The P89LPC933/934/935/936 has a TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ± 1 %. (Note: the initial value is better than 1 %; please refer to the P89LPC933/934/935/936 data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency.
Table 5: |
On-chip RC oscillator trim register (TRIM - address 96h) bit allocation |
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Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Symbol |
RCCLK |
ENCLK |
TRIM.5 |
TRIM.4 |
TRIM.3 |
TRIM.2 |
TRIM.1 |
TRIM.0 |
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Reset |
0 |
0 |
Bits 5:0 loaded with factory stored value during reset. |
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
26 of 147 |
Philips Semiconductors |
UM10116 |
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P89LPC933/934/935/936 User manual |
Table 6: |
On-chip RC oscillator trim register (TRIM - address 96h) bit description |
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Bit |
Symbol |
Description |
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0 |
TRIM.0 |
1 |
TRIM.1 |
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2 |
TRIM.2 |
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3 |
TRIM.3 |
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4 |
TRIM.4 |
Trim value. Determines the frequency of the internal RC oscillator. During reset, these bits are loaded with a stored factory calibration value. When writing to either bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value by reading this register, modifying bits 6 or 7 as required, and writing the result to this register.
5 |
TRIM.5 |
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6 |
ENCLK |
when = 1, CCLK⁄2 is output on the XTAL2 pin provided the crystal oscillator is not |
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being used. |
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7 |
RCCLK |
when = 1, selects the RC Oscillator output as the CPU clock (CCLK). This allows for |
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fast switching between any clock source and the internal RC oscillator without |
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needing to go through a reset cycle. |
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2.5 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.
2.6 External clock input option
In this configuration, the processor clock is derived from an external source driving the XTAL1 / P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.
quartz crystal or ceramic resonator
P89LPC93x
XTAL1
(1)
XTAL2
002aab229
Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.
(1)A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals.
Fig 9. Using the crystal oscillator.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
27 of 147 |
Philips Semiconductors |
UM10116 |
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P89LPC933/934/935/936 User manual |
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XTAL1 |
HIGH FREQUENCY |
RTC |
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MEDIUM FREQUENCY |
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XTAL2 |
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LOW FREQUENCY |
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ADC1 |
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ADC0 |
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(P89LPC935/936) |
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OSCCLK |
CCLK |
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DIVM |
CPU |
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RC |
RCCLK |
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OSCILLATOR |
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÷2 |
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(7.3728 MHz ±1 %) |
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PCLK |
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WATCHDOG |
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WDT |
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OSCILLATOR |
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(400 kHz +30 % −20 %) |
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PCLK |
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32 × PLL |
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SPI |
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(P89LPC935/936) |
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TIMER 1 |
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002aab079 |
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Fig 10. Block diagram of oscillator control.
2.7 Oscillator Clock (OSCCLK) wake-up delay
The P89LPC933/934/935/936 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections, the delay is 992 OSCCLK cycles plus 60 µs to 100 µs. If the clock source is either the internal RC oscillator or the Watchdog oscillator, the delay is 224 OSCCLK cycles plus 60 µs to 100 µs.
2.8 CPU Clock (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK frequency using the following formula:
CCLK frequency = fosc / (2N)
Where: fosc is the frequency of OSCCLK, N is the value of DIVM.
Since N ranges from 0 to 255, the CCLK frequency can be in the range of fosc to fosc/510. (for N = 0, CCLK = fosc).
This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. This can allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
28 of 147 |
Philips Semiconductors |
UM10116 |
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P89LPC933/934/935/936 User manual |
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2.9 Low power select
The P89LPC933/934/935/936 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.
3. A/D converter
3.1
The P89LPC935/936 have two 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter modules sharing common control logic. The P89LPC933/934 have a single 8-bit, 4-channel multiplexed analog-to-digital converter (ADC1) and an additional DAC module (DAC0). A block diagram of the A/D converter is shown in Figure 11. Each A/D consists of a 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.
3.2A/D features
•Two (P89LPC935/936) 8-bit, 4-channel multiplexed input, successive approximation A/D converters with common control logic (one A/D on the P89LPC933/934).
•Four result registers for each A/D.
•Six operating modes
–Fixed channel, single conversion mode
–Fixed channel, continuous conversion mode
–Auto scan, single conversion mode
–Auto scan, continuous conversion mode
–Dual channel, continuous conversion mode
–Single step mode
•Four conversion start modes
–Timer triggered start
–Start immediately
–Edge triggered
–Dual start immediately (P89LPC935/936)
•8-bit conversion time of ≥3.9 µs at an A/D clock of 3.3 MHz
•Interrupt or polled operation
•Boundary limits interrupt
•DAC output to a port pin with high output impedance
•Clock divider
•Power down mode
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
29 of 147 |
Philips Semiconductors |
UM10116 |
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P89LPC933/934/935/936 User manual |
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3.2.1A/D operating modes
3.2.1.1Fixed channel, single conversion mode
A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel (see Table 7). An interrupt, if enabled, will be generated after the conversion completes. The input channel is selected in the ADINS register. This mode is selected by setting the SCANx bit in the ADMODA register.
comp
INPUT |
+ |
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SAR |
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MUX |
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– |
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8 |
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DAC1 |
CONTROL
LOGIC
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comp |
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INPUT |
+ |
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SAR |
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MUX |
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– |
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8
DAC0
CCLK
002aab080
Fig 11. ADC block diagram.
Table 7: Input channels and result registers for fixed channel single, auto scan single, and auto scan continuous conversion modes
Result register |
Input channel |
Result register |
Input channel |
AD0DAT0 |
AD00 |
AD1DAT0 |
AD10 |
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AD0DAT1 |
AD01 |
AD1DAT1 |
AD11 |
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AD0DAT2 |
AD02 |
AD1DAT2 |
AD12 |
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AD0DAT3 |
AD03 |
AD1DAT3 |
AD13 |
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3.2.1.2Fixed channel, continuous conversion mode
A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result registers (see Table 8). An interrupt, if enabled, will be generated after every four conversions. Additional conversion results will again cycle through the four result registers, overwriting the previous results. Continuous conversions continue until terminated by the user. This mode is selected by setting the SCCx bit in the ADMODA register.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
User manual |
Rev. 01 — 4 March 2005 |
30 of 147 |
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