Philips P89LPC930, P89LPC931 Technical data

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAM

Rev. 05 — 15 December 2004 Product data

1. General description

The P89LPC930/931 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC930/931 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC930/931 in order to reduce component count, board space, and system cost.

2. Features

■ A high performance 80C51 CPU provides instruction cycle times of 111 ns to

222 ns for all instructions except multiply and divide when executing at 18 MHz. This is 6 times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.

■ 2.4 V to 3.6 V VDDoperating range. I/O pins are 5 V tolerant (may be pulled up or

driven to 5.5 V).

■ 4 kB/8 kB Flash code memory with 1 kB sectors, and 64-byte page size.

■ Byte-erase allowing code memory to be used for data storage.

■ Flash program operation completes in 2 ms.

■ Flash erase operation completes in 2 ms.

■ 256-byte RAM data memory.

■ Two 16-bit counter/timers. Each timer may be conﬁgured to toggle a port output

upon timer overﬂow or to become a PWM output.

■ Real-Time clock that can also be used as a system timer.

■ Two analog comparators with selectable inputs and reference source.

■ Enhanced UART with fractional baud rate generator, break detect, framing error

detection, automatic address detection and versatile interrupt capabilities.

■ 400 kHz byte-wide I2C-bus communication port.

■ SPI communication port.

■ Eight keypad interrupt inputs, plus two additional external interrupt inputs.

■ Four interrupt priority levels.

■ Watchdog timer with separate on-chip oscillator, requiring no external

components. The Watchdog time-out time is selectable from 8 values.

■ Active-LOWreset. On-chip power-on reset allows operation without external reset

components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.

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■ Low voltage reset (Brownout detect) allows a graceful system shutdown when

■ Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator

■ Conﬁgurable on-chip oscillator with frequency range and RC oscillator options

■ Programmable port output conﬁguration options:

■ Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value

■ Second data pointer.

■ Schmitt trigger port inputs.

■ LED drive capability (20 mA) on all port pins. Maximum combined I/O current of

■ Controlled slew rate port outputs to reduce EMI. Outputs have approximately

■ 23 I/O pins minimum (28-pin package). Up to 26 I/O pins while using on-chip

■ Only power and ground connections are required to operate the P89LPC930/931

■ Serial Flash programming allows in-circuit production coding. Flash security bits

■ In-Application Programming of the Flash code memory. This allows changing the

■ Idle and two different Power-down reduced power modes. Improvedwake-upfrom

■ 28-pin TSSOP package.

■ Emulation support.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

power fails. May optionally be conﬁgured as an interrupt.

allowing it to perform an oscillator fail detect function.

(selected by user programmed Flash conﬁguration bits). The RC oscillator (factory calibrated to ±1 %) option allows operation without external oscillator components. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. The RC oscillator option is selectable and ﬁne tunable.

◆ Quasi-bidirectional

◆ Open drain

◆ Push-pull

◆ Input-only

of the pins match or do not match a programmable pattern.

100 mA.

10 ns minimum ramp times.

oscillator and reset options.

using on-chip oscillator and on-chip reset options.

prevent reading of sensitive programs.

code in a running application.

Power-down mode (a low interrupt input starts execution). Typical Power-down current is 1 µA (total Power-down with voltage comparators disabled).

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3. Ordering information

Table 1: Ordering information

Type number Package

P89LPC930FDH TSSOP28 plastic thin shrink small outline package;

P89LPC931FDH TSSOP28 plastic thin shrink small outline package;

3.1 Ordering options

Table 2: Part options

Type number Program memory Temperature range Frequency

P89LPC930FDH 4 kB −45 °Cto+85°C 0 MHz to 18 MHz P89LPC931FDH 8 kB −45 °Cto+85°C 0 MHz to 18 MHz

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Name Description Version

SOT361-1

28 leads; body width 4.4 mm

SOT361-1

28 leads; body width 4.4 mm

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4. Block diagram

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

CRYSTAL

RESONATOR

4 kB/8 kB

CODE FLASH

256-BYTE

DATA RAM

PORT 3

CONFIGURABLE I/Os

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

PROGRAMMABLE

OSCILLATOR DIVIDER

CONFIGURABLE

OSCILLATOR

INTERNAL BUS

CPU CLOCK

ON-CHIP

OSCILLATOR

UART

I2C

SPI

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0 TIMER 1

WATCHDOG TIMER

AND OSCILLATOR

ANALOG

COMPARATORS

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

002aaa428

Fig 1. Block diagram.

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Philips Semiconductors

5. Pinning information

5.1 Pinning

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

handbook, halfpage

KBIO/CMP2/P0.0

RST/P1.5

XTAL1/P3.1

CLKOUT/XTAL2/P3.0

INT1/P1.4

SDA/INT0/P1.3

SCL/T0/P1.2

MOSI/P2.2 MISO/P2.3

Fig 2. DIP28 pin conﬁguration.

P2.0 P2.1

P1.7 P1.6

1 2 3 4 5 6 7 8

9 10 11 12 13 14

P89LPC930FDH

P89LPC931FDH

002aaa429

P2.7

28 27

P2.6 P0.1/CIN2B/KBI1

P0.2/CIN2A/KBI2

P0.3/CIN1B/KBI3

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.4/SS

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5.2 Pin description

Table 3: Pin description

Symbol Pin Type Description

P0.0 - P0.7 3, 26, 25,

24, 23, 22, 20, 19

3 I/O P0.0 — Port 0 bit 0.

26 I/O P0.1 — Port 0 bit 1.

25 I/O P0.2 — Port 0 bit 2.

24 I/O P0.3 — Port 0 bit 3.

23 I/O P0.4 — Port 0 bit 4.

22 I/O P0.5 — Port 0 bit 5.

20 I/O P0.6 — Port 0 bit 6.

19 I/O P0.7 — Port 0 bit 7.

I/O Port 0: Port 0 is an 8-bit I/O port with a user-conﬁgurable output type. During reset

Port 0 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section

8.11.1 “Port conﬁgurations” and Table 7 “DC electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

O CMP2 — Comparator 2 output. I KBI0 — Keyboard input 0.

I CIN2B — Comparator 2 positive input B. I KBI1 — Keyboard input 1.

I CIN2A — Comparator 2 positive input A. I KBI2 — Keyboard input 2.

I CIN1B — Comparator 1 positive input B. I KBI3 — Keyboard input 3.

I CIN1A — Comparator 1 positive input A. I KBI4 — Keyboard input 4.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5.

O CMP1 — Comparator 1 output. I KBI6 — Keyboard input 6.

I/O T1 — Timer/counter 1 external count input or overﬂow output. I KBI7 — Keyboard input 7.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

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Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Table 3: Pin description

…continued

Symbol Pin Type Description

P1.0 - P1.7 18, 17, 12,

11, 10, 6, 5, 4

I/O, I

[1]

Port 1: Port 1 is an 8-bit I/O port with a user-conﬁgurable output type, except for three pins as noted below. During reset Port 1 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the port conﬁguration selected. Each of the conﬁgurable port pins are programmed independently. Refer to Section 8.11.1 “Port

conﬁgurations” and Table 7 “DC electrical characteristics” for details. P1.2 - P1.3 are

open drain when used as outputs. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

18 I/O P1.0 — Port 1 bit 0.

O TxD — Transmitter output for the serial port.

17 I/O P1.1 — Port 1 bit 1.

I RXD — Receiver input for the serial port.

12 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).

I/O T0 — Timer/counter 0 external count input or overﬂowoutput(open-drain when used

as output).

I/O SCL — I

11 I P1.3 — Port 1 bit 3 (open-drain when used as output).

I I/O SDA — I

INT0 — External interrupt 0 input.

10 I P1.4 — Port 1 bit 4.

INT1 — External interrupt 1 input.

6IP1.5 — Port 1 bit 5 (input only).

RST — External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode. When using an oscillator frequency above 12 MHz, the

reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until V When system power is removed V operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when V

5 I/O P1.6 — Port 1 bit 6. 4 I/O P1.7 — Port 1 bit 7.

C serial clock input/output.

C serial data input/output.

falls below the minimum speciﬁed operating voltage.

has reached its speciﬁed level.

will fall below the minimum speciﬁed

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Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Table 3: Pin description

Symbol Pin Type Description

P2.0 - P2.7 1, 2, 13,

14, 15, 16, 27, 28

1 I/O P2.0 — Port 2 bit 0. 2 I/O P2.1 — Port 2 bit 1. 13 I/O P2.2 — Port 2 bit 2.

14 I/O P2.3 — Port 2 bit 3.

15 I/O P2.4 — Port 2 bit 4.

16 I/O P2.5 — Port 2 bit 5.

27 I/O P2.6 — Port 2 bit 6. 28 I/O P2.7 — Port 2 bit 7.

…continued

I/O Port 2: Port 2 is a 8-bit I/O port with a user-conﬁgurable output type. During reset

Port 2 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of port 2 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to the section on I/O port conﬁguration and the DC Electrical Characteristics for details. This port is not available in 20-pin package and is conﬁgured automatically as outputs to conserve power. The alternate functions for these pins must not be enabled.

All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below.

I/O MOSI — SPI master out slave in. When conﬁgured as master, this pin is output,

when conﬁgured as slave, this pin is input.

I/O MISO — SPI master in slave out. When conﬁgured as master, this pin is input, when

conﬁgured as slave, this pin is output.

I/O SPICLK — SPI clock. When conﬁgured as master, this pin is output, when

SS — SPI Slave select.

conﬁgured as slave, this pin is input.

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Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Table 3: Pin description

…continued

Symbol Pin Type Description

P3.0 - P3.1 9, 8 I/O Port 3: Port 3 is an 2-bit I/O port with a user-conﬁgurable output type. During reset

Port 3 latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section

8.11.1 “Port conﬁgurations” and Table 7 “DC electrical characteristics” for details.

All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below:

9 I/O P3.0 — Port 3 bit 0.

O XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is

selected via the FLASH conﬁguration).

O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It

can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the real time clock/system timer.

8 I/O P3.1 — Port 3 bit 1.

I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

selected via the FLASH conﬁguration). It can be a port pin if internal RC oscillator or Watchdog oscillator is used as the CPU clock source,and if XTAL1/XTAL2 are not used to generate the clock for the real time clock/system timer.

7IGround: 0 V reference. 21 I Power Supply: This is the power supply voltage for normal operation as well as Idle

and Power Down modes.

[1] Input/Output for P1.0-P1.4, P1.6, P1.7. Input for P1.5.

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Philips Semiconductors

6. Logic symbol

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

DDVSS

KBI0 KBI1 KBI2 KBI3 KBI4 KBI5 KBI6 KBI7

CLKOUT

Fig 3. Logic symbol.

CMP2 CIN2B CIN2A CIN1B CIN1A

CMPREF

CMP1

XTAL2 XTAL1

TxD RxD T0 INT0

PORT 0

PORT 3

PORT 1

P89LPC930/931

PORT 2

002aaa427

INT1 RST

MOSI MISO SS SPICLK

SCL SDA

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7. Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following

ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the

SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read. – ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

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Product data Rev. 05 — 15 December 2004 11 of 55

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Product data Rev. 05 — 15 December 2004 12 of 55

Table 4: Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000

AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00

B* B register F0H 00 00000000 BRGR0

BRGR1

BRGCON Baud rate generator control BDH ------SBRGS BRGEN 00 CMP1 Comparator 1 control register ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00 CMP2 Comparator 2 control register ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00 DIVM CPU clock divide-by-M

DPTR Data pointer (2 bytes)

DPH Data pointer HIGH 83H 00 00000000

DPL Data pointer LOW 82H 00 00000000 FMADRH Program Flash address HIGH E7H ------ 0000000000 FMADRL Program Flash address LOW E6H 00 00000000 FMCON Program Flash Control

FMDATA Program Flash data E5H 00 00000000 I2ADR I

I2CON* I I2DAT I

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Bit functions and addresses Reset value

addr.

Bit address E7 E6 E5 E4 E3 E2 E1 E0

Bit address F7 F6 F5 F4 F3 F2 F1 F0

[2]

Baud rate generator rate

BEH 00 00000000

LOW

[2]

Baud rate generator rate

BFH 00 00000000

HIGH

95H 00 00000000

control

E4H BUSY - - - HVA HVE SV OI 70 01110000

(Read) Program Flash Control

(Write)

C slave address register DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0 GC 00 00000000

Bit address DF DE DD DC DB DA D9 D8

C control register D8H - I2EN STA STO SI AA - CRSEL 00 x00000x0

C data register DAH

MSB LSB Hex Binary

[1]

[6] [1] [1]

FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

Philips Semiconductors

000000x0

xxxxxx00 xx000000 xx000000

8-bit microcontrollers with two-clock 80C51 core

P89LPC930/931

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Product data Rev. 05 — 15 December 2004 13 of 55

Table 4: Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

I2SCLH Serial clock generator/SCL

I2SCLL Serial clock generator/SCL

I2STAT I

IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00 00000000

IEN1* Interrupt enable 1 E8H - EST - - ESPI EC EKBI EI2C 00

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00 IP0H Interrupt priority 0 HIGH B7H - PWDRTHPBOH PSH/

IP1* Interrupt priority 1 F8H - PST - - PSPI PC PKBI PI2C 00 IP1H Interrupt priority 1 HIGH F7H - PSTH - - PSPIH PCH PKBIH PI2CH 00 KBCON Keypad control register 94H ------PATN

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

P0* Port 0 80H T1/KB7 CMP1

P1* Port 1 90H - -

P2* Port 2 A0H - - SPICLK SS MISO MOSI - -

P3*Port3 B0H------XTAL1XTAL2

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…continued

Bit functions and addresses Reset value

addr.

DDH 00 00000000

duty cycle register HIGH

DCH 00 00000000

duty cycle register LOW

C status register D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0 0 F8 11111000

Bit address AF AE AD AC AB AA A9 A8

Bit address EF EE ED EC EB EA E9 E8

Bit address BF BE BD BC BB BA B9 B8

Bit address FF FE FD FC FB FA F9 F8

86H 00 00000000

Bit address 87 86 85 84 83 82 81 80

Bit address 97 96 95 94 93 92 91 90

Bit address A7 A6 A5 A4 A3 A2 A1 A0

Bit address B7 B6 B5 B4 B3 B2 B1 B0

MSB LSB Hex Binary

[1]

PT1H PX1H PT0H PX0H 00

[1]

PSRH

[1] [1]

KBIF 00

[1]

_SEL

/KB6

CMPREF

/KB5

RST INT1 INT0/

CIN1A

/KB4

CIN1B

/KB3

CIN2A

/KB2

CIN2B

/KB1

CMP2

/KB0

T0/SCL RXD TXD

SDA

00x00000

x0000000 x0000000

00x00000 00x00000 xxxxxx00

[1]

Philips Semiconductors

8-bit microcontrollers with two-clock 80C51 core

P89LPC930/931

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Product data Rev. 05 — 15 December 2004 14 of 55

Table 4: Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

P0M1 Port 0 output mode 1 84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF 11111111 P0M2 Port 0 output mode 2 85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00 00000000 P1M1 Port 1 output mode 1 91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3 P1M2 Port 1 output mode 2 92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00 P2M1 Port 2 output mode 1 A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0) FF P2M2 Port 2 output mode 2 A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00 00000000 P3M1 Port 3 output mode 1 B1H ------(P3M1.1) (P3M1.0) 03 P3M2 Port 3 output mode 2 B2H ------(P3M2.1) (P3M2.0) 00 PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD - VCPD - I2PD SPPD SPD - 00

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1 - 00 xx00000x RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60

RTCH Real-time clock register HIGH D2H 00 RTCL Real-time clock register LOW D3H 00 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000

SBUF Serial port data buffer register 99H xx xxxxxxxx

SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status

SP Stack pointer 81H 07 00000111 SPCTL SPI Control Register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 00000100 SPSTAT SPI Status Register E1H SPIF WCOL ------0000xxxxxx SPDAT SPI Data Register E3H 00 00000000

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…continued

Bit functions and addresses Reset value

addr.

Bit address D7 D6 D5 D4 D3 D2 D1 D0

Bit address 9F 9E 9D 9C 9B 9A 99 98

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000

MSB LSB Hex Binary

[1]

[1] [1]

[1]

[6]

[6] [6]

[1]

11x1xx11 00x0xx00 11111111

xxxxxx11 xxxxxx00

00000000

[3]

011xxx00

00000000 00000000

Philips Semiconductors

8-bit microcontrollers with two-clock 80C51 core

P89LPC930/931

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Product data Rev. 05 — 15 December 2004 15 of 55

Table 4: Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

TAMOD Timer 0 and 1 auxiliary mode 8FH - - - T1M2 - - - T0M2 00 xxx0xxx0

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 00000000 TH0 Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TL0 Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1 T0M0 00 00000000 TRIM Internal oscillator trim register 96H - ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H

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…continued

Bit functions and addresses Reset value

addr.

Bit address 8F 8E 8D 8C 8B 8A 89 88

MSB LSB Hex Binary

Philips Semiconductors

[5] [6] [4] [6]

[1] All ports are in input only (high impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.

Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise speciﬁed, ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are ’0’s although they are unknown when read.

[3] The RSTSRC register reﬂects the cause of the P89LPC930/931 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset value is

xx110000.

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOF bit is ‘1’ after Watchdogresetandis‘0’afterpower-onreset. Other resets will

not affect WDTOF.

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

8-bit microcontrollers with two-clock 80C51 core

P89LPC930/931

Philips Semiconductors

8. Functional description

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Remark: Please refer to the

functional description.

8.1 Enhanced CPU

The P89LPC930/931 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

8.2 Clocks

8.2.1 Clock deﬁnitions

The P89LPC930/931 device has several internal clocks as deﬁned below: OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four

clock sources (see Figure 4) and can also be optionally divided to a slower frequency (see Section 8.7 “CPU CLOCK (CCLK) modiﬁcation: DIVM register”).

Note: f CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per

machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output. PCLK — Clock for the various peripheral devices and is CCLK/2

is deﬁned as the OSCCLK frequency.

osc

P89LPC930/931 User’s Manual

for a more detailed

8.2.2 CPU clock (OSCCLK)

The P89LPC930/931 providesseveraluser-selectableoscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are conﬁgured when the FLASH is programmed and include an on-chip Watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.

8.2.3 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this conﬁguration.

8.2.4 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this conﬁguration.

8.2.5 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this conﬁguration. When using an oscillator

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the minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum speciﬁed operating voltage.

8.2.6 Clock output

The P89LPC930/931 supports a user-selectable clock output function on the XTAL2/CLKOUTpin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, Watchdog oscillator, external clock input on X1) and if the Real-Time clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC930/931. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is1⁄2that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.3 On-chip RC oscillator option

The P89LPC930/931 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±1% at room temperature. End-user applications can write to the Trim register to adjust the on-chip RC oscillator to other frequencies.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

8.4 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

8.5 External clock input option

In this conﬁguration, the processor clock is derived from an external source driving the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2/P3.0 pin may be used as a standard port pin or a clock output. When using an oscillator

frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDDhas reached its speciﬁed level. When system power is removed VDD will fall below the minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum speciﬁed operating voltage.

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

XTAL1 XTAL2

SPI

High freq. Med. freq.

Low freq.

OSCILLATOR (7.3728 MHz)

WATCHDOG

OSCILLATOR

(400 kHz)

TIMER 0 and

TIMER 1

OSCCLK

PCLK

I2C

Fig 4. Block diagram of oscillator control.

DIVM

BAUD RATE

GENERATOR

CCLK

UART

RTC

CPU

WDT

002aaa431

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8.6 CPU CLock (CCLK) wake-up delay

The P89LPC930/931 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus 60 to 100 µs. If the clock source is either the internal RC oscillator, Watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60 to 100 µs.

8.7 CPU CLOCK (CCLK) modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 256 times by conﬁguring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

8.8 Low power select

The P89LPC930/931 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower,the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

8.9 Memory organization

The various P89LPC930/931 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC930/931 has 4 kB/ 8 kB of on-chip Code memory.

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8.10 Interrupts

The P89LPC930/931 uses a four priority level interrupt structure. This allows great ﬂexibility in controlling the handling of the many interrupt sources. The P89LPC930/931 supports 13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect, watchdog/real-time clock, I2C, keyboard, and comparators 1 and 2, and SPI.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levelsare pending at the start of an instruction, the request of higher priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.

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8-bit microcontrollers with two-clock 80C51 core

8.10.1 External interrupt inputs

The P89LPC930/931 has two external interrupt inputs as well as the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set, causing an interrupt request.

If an external interrupt is enabled when the P89LPC930/931 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-upand resume operation. Refer to Section 8.13 “Power reduction modes” for details.

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RTCF ERTC

(RTCCON.1)

WDOVF

IE0

EX0

IE1

EX1

BOF EBO

KBIF

EKBI

EWDRT

CMF2 CMF1

EA (IE0.7)

TF0

ET0

TF1

ET1

TI & RI/RI

ES/ESR

EST

EI2C SPIF

ESPI

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

WAKE-UP (IF IN POWER-DOWN)

INTERRUPT TO CPU

002aaa432

Fig 5. Interrupt sources, interrupt enables, and power-down wake-up sources.

8.11 I/O ports

The P89LPC930/931 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0, 1 and 2 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available depend upon the clock and reset options chosen, as shown in Table 5.

Table 5: Number of I/O pins available

Clock source Reset option Number of I/O pins

On-chip oscillator or Watchdog oscillator

External clock input No external reset (except during power-up) 25

Low/medium/high speed oscillator (external crystal or resonator)

[1] Required for operation above 12 MHz.

No external reset (except during power-up) 26 External

External

RST pin supported

[1]

No external reset (except during power-up) 24 External

RST pin supported

[1]

(20-pin package)

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8.11.1 Port conﬁgurations

All but three I/O port pins on the P89LPC930/931 may be conﬁgured by software to one of four types on a bit-by-bitbasis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two conﬁguration registers for each port select the output type for each port pin.

P1.5 (RST) can only be an input and cannot be conﬁgured. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be conﬁgured to be either input-only or

open-drain.

8.11.2 Quasi-bidirectional output conﬁguration

Quasi-bidirectional outputs can be used as both an input and output without the need to reconﬁgure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW,it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes.

The P89LPC930/931 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current ﬂowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

8.11.3 Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be used as a logic output, a port conﬁgured in this manner must have an external pull-up, typically a resistor tied to VDD.

An open-drain port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

8.11.4 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt-triggered input that also has a glitch suppression circuit.

8.11.5 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic ‘1’. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

8.11.6 Port 0 analog functions

The P89LPC930/931 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled.

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Digital outputs are disabled by putting the port output into the Input-Only (high impedance) mode as described in Section 8.11.4.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register, bits 1:5. On any reset, PT0AD1:5 defaults to ‘0’s to enable digital functions.

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8.11.7 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.

• After power-up, all I/O pins except P1.5, may be conﬁgured by software.

• Pin P1.5 is input only.Pins P1.2 and P1.3 and are conﬁgurable for either input-only

Every output on the P89LPC930/931 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 7 “DC electrical characteristics” for detailed speciﬁcations.

All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

8.12 Power monitoring functions

The P89LPC930/931 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout detect.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

or open-drain.

8.12.1 Brownout detection

The Brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a Brownout detection to cause a processor reset, however it may alternatively be conﬁgured to generate an interrupt.

Brownout detection may be enabled or disabled in software. If Brownout detection is enabled, the brownout condition occurs when VDDfalls below

the brownout trip voltage, VBO (see Table 7 “DC electrical characteristics”), and is negated when VDD rises above VBO. If the P89LPC930/931 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating.

For correct activation of Brownout detect, the VDD rise and fall times must be observed. Please see Table 7 “DC electrical characteristics” for speciﬁcations.

8.12.2 Power-on detection

The Power-on Detect has a function similar to the Brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where Brownout detect can work. The POF ﬂag in the RSTSRC register is set to indicate an initial power-up condition. The POF ﬂag will remain set until cleared by software.

8.13 Power reduction modes

The P89LPC930/931 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode.

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8.13.1 Idle mode

Idle mode leavesperipherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.

8.13.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC930/931 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage V was entered. SFR contents are not guaranteed after VDD has been lowered to V therefore it is highly recommended to wake up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during Power-down.These include: Brownout detect, Watchdog Timer, Comparators (note that Comparators can be powered-down separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

. This retains the RAM contents at the point where Power-down mode

RAM

8.13.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during Power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the Real-Time Clock running during Power-down.

8.14 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin will always function as a reset input. An external circuit connected to this pin

should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this input will function either as an external reset

input or as a digital input as deﬁned by the RPE bit. Only a power-up reset will temporarily override the selection deﬁned by RPE bit. Other sources of reset will not override the RPE bit.

Remark: During a power cycle, VDDmust fall below V

(see Table 7 “DC electrical

POR

characteristics” on page 42) before power is reapplied, in order to ensure a power-on

reset. Reset can be triggered from the following sources:

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• External reset pin (during power-up or if user conﬁgured via UCFG1. This option

• Power-on detect

• Brownout detect

• Watchdog Timer

• Software reset

• UART break character detect reset

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These ﬂag bits can be cleared in software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

• For any other reset, previously set ﬂag bits that have not been cleared will remain

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

must be used for an oscillator frequency above 12 MHz.)

cleared.

set.

8.14.1 Reset vector

Followingreset, the P89LPC930/931 will fetch instructions from either address 0000h or the Boot address. The Boot address is formed by using the Boot Vectoras the high byte of the address and the low byte of the address = 00h.

The Boot address will be used if a UART break reset occurs, or the non-volatile Boot Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see

P89LPC930/931 User’s Manual

address 0000H.

8.15 Timers/counters 0 and 1

The P89LPC930/931 has two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. Both can be conﬁgured to operate either as timers or event counter. An option to automatically toggle the T0 and/or T1 pins upon timer overﬂow has been added.

In the ‘Timer’ function, the register is incremented every machine cycle. In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition

at its corresponding external input pin, T0 or T1. In this function, the external input is sampled once during every machine cycle.

Timer 0 and Timer 1 have ﬁve operating modes (modes 0, 1, 2, 3 and 6). Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is different.

). Otherwise, instructions will be fetched from

8.15.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is conﬁgured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

8.15.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

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8.15.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.

8.15.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

8.15.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.

8.15.6 Timer overﬂow toggle output

Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a timer overﬂow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic ‘1’ prior to the ﬁrst timer overﬂow when this mode is turned on.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

8.16 Real-Time clock/system timer

The P89LPC930/931 has a simple Real-Time clock that allows a user to continue running an accurate timer while the rest of the device is powered-down. The Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF ﬂag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL oscillator, provided that the XTALoscillator is not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as its clock source. Only power-on reset will reset the Real-Time clock and its associated SFRs to the default state.

8.17 UART

The P89LPC930/931 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source. The P89LPC930/931 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overﬂow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.

8.17.1 Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at1⁄16 of the CPU clock frequency.

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8.17.2 Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit (logic ‘0’), 8 data bits (LSB ﬁrst), and a stop bit (logic ‘1’). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in

Section 8.17.5 “Baud rate generator and selection”).

8.17.3 Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logic ‘0’), 8 data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic ‘1’). When data is transmitted, the 9thdata bit (TB8 in SCON) can be assigned the value of ‘0’ or ‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not saved. The baud rate is programmable to either1⁄16 or1⁄32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON.

8.17.4 Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit (logic ‘0’), 8 data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic ‘1’). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in section Section 8.17.5 “Baud rate generator and selection”).

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

8.17.5 Baud rate generator and selection

The P89LPC930/931 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing functions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 6). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent Baud Rate Generator uses OSCCLK.

SMOD1 = 1

SMOD1 = 0

Timer 1 Overflow

(PCLK-based)

Baud Rate Generator

(CCLK-based)

Fig 6. Baud rate sources for UART (Modes 1, 3).

8.17.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is ‘1’, framing errors can be made available in SCON.7 respectively. If SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is ‘0’.

SBRGS = 0

SBRGS = 1

Baud Rate Modes 1 and 3

002aaa419

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8.17.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device and force the device into ISP mode.

8.17.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the ﬁrst character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = ‘0’), the UART is compatible with the conventional80C51 UART. If enabled, the UARTallows writing to SnBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = ‘0’).

8.17.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventionalUART, in double buffering mode, the Tx interrupt is generated when the double buffer is ready to receive new data.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

8.17.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.

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8.18 I2C-bus serial interface

I2C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features:

• Bidirectional data transfer between masters and slaves.

• Multimaster bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of

• Serial clock synchronization allows devices with different bit rates to communicate

• Serial clock synchronization can be used as a handshake mechanism to suspend

• The I

A typical I2C-bus conﬁguration is shown in Figure 7. The P89LPC930/931 device provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.

8-bit microcontrollers with two-clock 80C51 core

serial data on the bus.

via one serial bus.

and resume serial transfer.

C-bus may be used for test and diagnostic purposes.

P89LPC930/931

C-BUS

P1.3/SDA P1.2/SCL

P89LPC930/931

Fig 7. I2C-bus conﬁguration.

OTHER DEVICE

WITH I

INTERFACE

C-BUS

OTHER DEVICE

WITH I

C-BUS

INTERFACE

002aaa433

SDA

SCL

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

P1.3/SDA

P1.2/SCL

P1.3

INPUT

FILTER

OUTPUT

STAGE

INPUT

FILTER

OUTPUT

STAGE

P1.2

TIMER 1

OVERFLOW

I2CON I2SCLH I2SCLL

ADDRESS REGISTER

COMPARATOR

SHIFT REGISTER

BIT COUNTER /

ARBITRATION &

SYNC LOGIC

SERIAL CLOCK

GENERATOR

CONTROL REGISTERS &

SCL DUTY CYCLE REGISTERS

TIMING

CONTROL

LOGIC

I2ADR

INTERNAL BUS

ACK

I2DAT

CCLK

INTERRUPT

STATUS BUS

I2STAT

Fig 8. I2C-bus serial interface block diagram.

8.19 Serial Peripheral Interface (SPI)

LPC930/931 provides another high-speed serial communication interface - the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in Master or 3.0 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection.

STATUS

DECODER

STATUS REGISTER

002aaa421

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CPU clock

DIVIDER

BY 4, 16, 64, 128

SELECT

SPR1

SPR0

SPI CONTROL

SPIF

WCOL

SPI STATUS REGISTER

interrupt

request

SPI clock (master)

MSTR

SPEN

SPI

8-BIT SHIFT REGISTER

READ DATA BUFFER

CLOCK LOGIC

SSIG

SPEN

DORD

MSTR

SPI CONTROL REGISTER

internal

data

bus

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

clock

CPHA

CPOL

SPR1

SPR0

M M

S M

MSTR

PIN CONTROL LOGIC

SPEN

MISO

P2.3

MOSI

P2.2

SPICLK

P2.5

P2.4

002aaa434

Fig 9. SPI block diagram.

The SPI interface has four pins: SPICLK, MOSI, MISO, and SS:

• SPICLK, MOSI and MISO are typically tied together between two or more SPI

devices. Data ﬂows from master to slave on MOSI (Master Out Slave In) pin and ﬂows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are conﬁgured for port functions.

• SS is the optional slave select pin. In a typical conﬁguration, an SPI master asserts

one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected.

Typical connections are shown in Figures 10, 11, and 12.

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8.19.1 Typical SPI conﬁgurations

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Master Slave

8-BIT SHIFT

MISO

MOSI

MISO

MOSI

8-BIT SHIFT

SPICLK

SPI CLOCK

GENERATOR

PORT

Fig 10. SPI single master single slave conﬁguration.

Master Slave

MISO

8-BIT SHIFT

SPI CLOCK

GENERATOR

MOSI

SPICLK

MISO

MOSI

SPICLK

002aaa435

8-BIT SHIFT

SPI CLOCK

GENERATOR

002aaa436

Fig 11. SPI dual device conﬁguration, where either can be a master or a slave.

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Master Slave

8-BIT SHIFT

MISO

MOSI

MISO

MOSI

8-BIT SHIFT

SPI CLOCK

GENERATOR

SPICLK port

port

SPICLK

Fig 12. SPI single master multiple slaves conﬁguration.

MISO MOSI

Slave

8-BIT SHIFT

002aaa437

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8.20 Analog comparators

Two analog comparators are provided on the P89LPC930/931. Input and output options allow use of the comparators in a number of different conﬁgurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a ‘0’. Each comparator may be conﬁgured to cause an interrupt when the output value changes.

The overall connections to both comparators are shown in Figure 13. The comparators function to VDD= 2.4 V.

When each comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt ﬂag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.

When a comparator is disabled the comparator’s output, COx, goes HIGH. If the comparator output was LOW and then is disabled, the resulting transition of the comparator output from a LOW to HIGH state will set the comparator ﬂag, CMFx. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator ﬂag, CMFx, after disabling the comparator.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

(P0.4) CIN1A (P0.3) CIN1B

(P0.5) CMPREF

(P0.2) CIN2A (P0.1) CIN2B

CP1

REF

CN1

CP2

CN2

Comparator 1

Comparator 2

Fig 13. Comparator input and output connections.

8.20.1 Internal reference voltage

An internal reference voltage generator may supply a defaultreference when a single comparator input pin is used. The value of the internal reference voltage, referred to as V

, is 1.23 V ±10%.

REF

CO1

Change Detect

CO2

OE1

OE2

CMP1 (P0.6)

CMF1

Interrupt

CMF2

CMP2 (P0.0)

002aaa422

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8.20.2 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag is set whenever the comparator output changes state. The ﬂag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the ﬂags to determine which comparator caused the interrupt.

8.20.3 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. If the comparator output to a pin is enabled, the pin should be conﬁgured in the push-pull mode in order to obtain fastswitchingtimes while in power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode.

8.21 Keypad interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can conﬁgure the port via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to deﬁne which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to deﬁne a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to deﬁne equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use.

In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held longer than 6 CCLKs.

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8.22 Watchdog timer

The watchdog timer causes a system reset when it underﬂows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz Watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the Watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 14 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few µs to a few seconds. Please refer to the more details.

MOV WFEED1, #0A5H MOV WFEED2, #05AH

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

P89LPC930/931 User’s Manual

WDL (C1H)

for

Watchdog

oscillator

PCLK

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a

feed sequence.

÷32

WDCON (A7H)

PRESCALER

CONTROL REGISTER

PRE2 PRE1 PRE0 – – WDRUN WDTOF WDCLK

8-BIT DOWN

COUNTER

RESET see note (1)

002aaa423

Fig 14. Watchdog timer in Watchdog mode (WDTE = ‘1’).

8.23 Additional features

8.23.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or Watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.

SHADOW REGISTER FOR WDCON

8.23.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1register, without the possibility of inadvertently altering other bits in the register.

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8.24 Flash program memory

8.24.1 General description

The P89LPC930/931 Flash memory provides in-circuit electrical erasure and programming. The Flash can be read, erased, or written as bytes. The Sector and PageErase functions can erase any Flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. In-System Programming and standard parallel programming are both available. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC930/931 Flash reliably stores memory contents even after more than 100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC930/931 uses VDD as the supply voltage to perform the Program/Erase algorithms.

8.24.2 Features

• Byte-erase allowing code memory to be used for data storage.

• Internal ﬁxed boot ROM, containing low-level In-Application Programming (IAP)

• User programs can call these routines to perform In-Application Programming

• Default loader providing In-System Programming via the serial port, located in

• Boot vector allows user-provided Flash loader code to reside anywhere in the

• Programming and erase over the full operating voltage range.

• Programming/Erase using ISP/IAP.

• Any ﬂash program/erase operation in 2 ms.

• Parallel programming with industry-standard commercial programmers.

• Programmable security for the code in the Flash for each sector.

• More than 100,000 typical erase/program cycles for each byte.

• 10 year minimum data retention.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

routines.

(IAP).

upper end of user program memory.

Flash memory space, providing ﬂexibility to the user.

8.24.3 Using Flash as data storage

The Flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.

8.24.4 ISP and IAP capabilities of the P89LPC930/931

Flash organization: The P89LPC930/931 program memory consists of eight 1 KB

sectors. Each sector can be further divided into 64-byte pages. In addition to sector erase and page erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. An In-Application Programming (IAP) interface is provided to allow the end user’s application to erase and reprogram the user code memory. In

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addition, erasing and reprogramming of user-programmable bytes including UCFG1, the Boot Status Bit, and the Boot Vector is supported. As shipped from the factory, the upper 512 bytes of user code space contains a serial In-System Programming (ISP) routine allowing for the device to be programmed in circuit through the serial port.

Flash programming and erasing: There are three methods of erasing or

programming of the Flash memory that may be used. First, the Flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point. Second, the on-chip ISP boot loader may be invoked. This ISP boot loader will, in turn, call low-level routines through the same common entry point that can be used by the end-user application. Third, the Flash may be programmed or erased using the parallel method by using a commercially available EPROM programmer which supports this device. This device does not provide for direct veriﬁcation of code memory contents. Instead this device provides a 32-bit CRC result on either a sector or the entire 8 kbytes of user code space.

Boot ROM: When the microcontroller programs its own Flash memory, all of the low

level details are handled by code that is contained in a Boot ROM that is separate from the Flash memory. A user program simply calls the common entry point in the Boot ROM with appropriate parameters to accomplish the desired operation. The Boot ROM include operations such as erase sector, erase page, program page, CRC, program security bit, etc. The Boot ROM occupies the program memory space at the top of the address space from FF00 to FEFF hex, thereby not conﬂicting with the user program memory space.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Power-on reset code execution: The P89LPC930/931 contains two special Flash

elements: the Boot Vector and the Boot Status Bit. Following reset, the P89LPC930/931 examines the contents of the Boot Status Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code. When the Boot Status Bit is set to a value other than zero, the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to 00H. The factory default setting is 01EH (0EH for the LPC930), corresponds to the address 1E00H (0E00h for the LPC930) for the default ISP boot loader. This boot loader is pre-programmed at the factory into this address space and can be erased by the user. Users who wish to use this

loader should take cautions to avoid erasing the 1 kbyte sector from 1C00H to 1FFFH (0C00H to 0FFFH for the LPC930). Instead, the page erase function can be used to erase the eight (four for the LPC930) 64-byte pages located from 1C00H to 1DFFH (0C00H to 0DFFH for the LPC930). A custom boot loader can be

written with the Boot Vector set to the custom boot loader, if desired.

Hardware activation of the boot loader: The boot loader can also be executed by

forcing the device into ISP mode during a power-on sequence (see the

P89LPC930/931 User’s Manual

having a non-zero status byte. This allows an application to be built that will normally executeuser code but can be manually forced into ISP operation. If the factory default setting for the Boot Vector (1EH for the lPC931, 0EH for the LPC930) is changed, it will no longer point to the factory pre-programmed ISP boot loader code. If this happens, the only way it is possible to change the contents of the Boot Vector is through the parallel programming method, provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of

for speciﬁc information). This has the same effect as

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the Boot Vector and Boot Status Bit. After programming the Flash, the status byte should be programmed to zero in order to allow execution of the user’s application code beginning at address 0000H.

In-System Programming (ISP): In-System Programming is performed without

removing the microcontroller from the system. The In-System Programming facility consists of a series of internal hardware resources coupled with internal ﬁrmware to facilitate remote programming of the P89LPC930/931 through the serial port. This ﬁrmware is provided by Philips and embedded within each P89LPC930/931 device. The Philips In-System Programming facility has made in-system programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ISP function uses ﬁve pins (VDD, VSS, TxD, RxD, and RST). Only a small connector needs to be availableto interface your application to an external circuit in order to use this feature.

In-Application Programming (IAP): Several In-Application Programming (IAP) calls

are available for use by an application program to permit selective erasing, reading, and programming of Flash sectors, pages, security bits, conﬁguration bytes, and device id. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FF00H.

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

8.25 User conﬁguration bytes

A number of user-conﬁgurable features of the P89LPC930/931 must be deﬁned at power-up and therefore cannot be set by the program after start of execution. These features are conﬁgured through the use of the Flash byte UCFG1. Please see the

P89LPC930/931 User’s Manual

for additional details.

8.26 User sector security bytes

There are eight User Sector Security Bytes, each corresponding to one sector. Please see the

P89LPC930/931 User’s Manual

for additional details.

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9. Limiting values

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Table 6: Limiting values

[1]

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

amb(bias)

stg

xtal

OH(I/O)

OL(I/O)

I/O(tot)(max)

tot(pack)

operating bias ambient temperature −55 +125 °C storage temperature range −65 +150 °C voltage on XTAL1, XTAL2 pin to V voltage on any other pin to V

-V

+ 0.5 V

−0.5 +5.5 V HIGH-level output current per I/O pin - 20 mA LOW-level output current per I/O pin - 20 mA maximum total I/O current - 100 mA total power dissipation per package based on package heat

- 1.5 W

transfer, not device power consumption

[1] The following applies to Limiting values:

a) Stresses above those listed under Table 6 may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any conditions other than those described in Table 7 “DC electrical characteristics”, Table 8 “AC

characteristics” and Table 9 “AC characteristics” of this speciﬁcation are not implied.

b) This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

c) Parameters are valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to VSS unless

otherwise noted.

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

10. Static characteristics

Table 7: DC electrical characteristics

VDD= 2.4 V to 3.6 V unless otherwise speciﬁed.

=−40°Cto+85°C for industrial, unless otherwise speciﬁed.

amb

0.4V

[1]

Max Unit

-V

0.7V

- 5.5 V

-V

--V

Symbol Parameter Conditions Min Typ

DD(oper)

DD(idle)

DD(PD)

power supply current, operating 3.6 V; 12 MHz

3.6 V; 18 MHz

power supply current, Idle mode

power supply current,

3.6 V; 12 MHz

3.6 V; 18 MHz

3.6 V

[2]

-1118mA

[2]

-1423mA

[2]

- 3.25 5 mA

[2]

-57mA

[2]

-5580µA Power-down mode, voltage comparators powered-down

DD(TPD)

power supply current, Total

3.6 V

[2]

-15µA Power-down mode

(dV

/dt)rVDD rise rate - - 2 mV/µs

/dt)fVDD fall rate - - 50 mV/µs

(dV

V V V

POR RAM th(HL)

Power-on reset detect voltage - - 0.2 V RAM keep-alive voltage 1.5 - - V negative-going threshold

except SCL, SDA 0.22V

voltage

V V V V V

IL th(LH) IH hys OL

LOW-level input voltage SCL, SDA only −0.5 - 0.3V positive-going threshold voltage except SCL, SDA - 0.6V HIGH-level input voltage SCL, SDA only 0.7V

hysteresis voltage Port 1 - 0.2V LOW-level output voltage; all

ports, all modes except Hi-Z

HIGH-level output voltage, all ports

IOL= 20 mA;

= 2.4 V to 3.6 V

= 3.2 mA;

= 2.4 V to 3.6 V

IOH= −20 µA;

= 2.4 V to 3.6 V;

[3]

- 0.6 1.0 V

[3]

- 0.2 0.3 V

− 0.3 VDD− 0.2 - V

quasi-bidirectional mode I

= −3.2 mA;

= 2.4 V to 3.6 V;

− 0.7 VDD− 0.4 - V

push-pull mode I

= −20 mA;

= 2.4 V to 3.6 V;

0.8V

push-pull mode

RST

input/output pin capacitance logic 0 input current, all ports VIN= 0.4 V input leakage current, all ports VIN=VILor V logic 1-to-0 transition current,

all ports

VIN= 2.0 V at

= 3.6 V

internal reset pull-up resistor 10 - 30 kΩ

[4]

--15pF

[5]

--−80 µA

[6]

--±10 µA

[7]

−30 - −450 µA

DD DD

V V

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Table 7: DC electrical characteristics

…continued

VDD= 2.4 V to 3.6 V unless otherwise speciﬁed.

=−40°Cto+85°C for industrial, unless otherwise speciﬁed.

amb

Symbol Parameter Conditions Min Typ

brownout trip voltage with

2.4 V < VDD< 3.6 V 2.40 - 2.70 V

[1]

Max Unit

BOV = ‘0’, BOPD = ‘1’

REF

(VREF)

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. [2] The I

brownout detect, and watchdog timer.

[3] See Table 6 “Limiting values

VOL/VOH may exceed the related speciﬁcation. [4] Pin capacitance is characterized but not tested. [5] Measured with port in quasi-bidirectional mode. [6] Measured with port in high-impedance mode. [7] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from ‘1’ to ‘0’. This current is highest

when VIN is approximately 2 V.

bandgap reference voltage 1.11 1.23 1.34 V bandgap temperature

- 10 20 ppm/°

coefﬁcient

DD(oper),IDD(idle)

, and I

speciﬁcations are measured using an external clock with the followingfunctionsdisabled: comparators,

DD(PD)

[1]

” on page 41 for steady state (non-transient) limits on IOL or IOH. If IOL/IOH exceeds the test condition,

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P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

11. Dynamic characteristics

Table 8: AC characteristics

VDD = 2.4 V to 3.6 V unless otherwise speciﬁed.

=−40°Cto+85°C for industrial, unless otherwise speciﬁed.

amb

Symbol Parameter Conditions Variable clock f

RCOSC

WDOSC

internal RC oscillator frequency 7.189 7.557 7.189 7.557 MHz internal watchdog oscillator

frequency

osc

CLCL

CLKP

oscillator frequency 0 12 - - MHz clock cycle see Figure 20 83- --ns CLKLP active frequency 0 8 - - MHz

Glitch ﬁlter

glitch rejection, P1.5/ signal acceptance, P1.5/

RST pin - 50 - 50 ns

RST pin 125 - 125 - ns

glitch rejection, any pin except

RST

P1.5/ signal acceptance, any pin except

P1.5/

RST

External clock

CHCX

CLCX

CLCH

CHCL

HIGH time see Figure 20 33 t LOW time see Figure 20 33 t rise time see Figure 20 -8 -8ns fall time see Figure 20 -8 -8ns

Shift register (UART mode 0)

XLXL

QVXH

serial port clock cycle time 16 t output data set-up to clock rising

edge

XHQX

output data hold after clock rising edge

XHDX

input data hold after clock rising edge

DVXH

input data valid to clock rising edge 150 - 150 - ns

SPI interface

SPI

Operating frequency

2.0 MHz (Slave) 0

3.0 MHz (Master) -

SPICYC

Cycle time see Figures

15, 16, 17, 18

2.0 MHz (Slave)

3.0 MHz (Master)

SPILEAD

Enable lead time (Slave) see Figures

17, 18

2.0 MHz 250 - 250 - ns

[1]

Min Max Min Max

320 520 320 520 kHz

- 15 - 15 ns

50 - 50 - ns

− t

CLCL

CLCX

− t

CLCL

CHCX

- 1333 - ns

CLCL

13 t

-t

- 1083 - ns

CLCL

+ 20 - 103 ns

CLCL

-0 -0ns

CCLK

⁄

CCLK

⁄

CCLK

⁄

CCLK

- 500 - ns

- --ns

=12MHz Unit

osc

33 - ns 33 - ns

0 2.0 MHz

- - MHz

9397 750 14472

Product data Rev. 05 — 15 December 2004 44 of 55

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Table 8: AC characteristics

…continued

VDD = 2.4 V to 3.6 V unless otherwise speciﬁed.

=−40°Cto+85°C for industrial, unless otherwise speciﬁed.

amb

[1]

Symbol Parameter Conditions Variable clock f

Min Max Min Max

SPILAG

Enable lag time (Slave) see Figures

17, 18

2.0 MHz 250 - 250 - ns

SPICLKH

SPICLK high time see Figures

15, 16, 17, 18

SPICLKL

Master Slave

SPICLK low time see Figures

⁄

CCLK

⁄

CCLK

- 340 - ns

- 190 - ns

15, 16, 17, 18

SPIDSU

Master Slave

Data set-up time (Master or Slave) see Figures

⁄

CCLK

⁄

CCLK

100 - 100 - ns

- 340 - ns

- 190 - ns

15, 16, 17, 18

SPIDH

Data hold time (Master or Slave) see Figures

100 - 100 - ns

15, 16, 17, 18

SPIA

Access time (Slave) see Figures

0 120 0 120 ns

17, 18

SPIDIS

Disable time (Slave) see Figures

17, 18

2.0 MHz 0 240 - 240 ns

SPIDV

Enable to output data valid see Figures

15, 16, 17, 18

2.0 MHz 0 240 - 240 ns

3.0 MHz 0 167 - 167 ns

SPIOH

Output data hold time see Figures

0- 0-ns

15, 16, 17, 18

SPIR

Rise time see Figures

15, 16, 17, 18

SPI outputs (SPICLK, MOSI,

- 100 - 100 ns

MISO)

- 2000 - 2000 ns

SPIF

SPI inputs (SPICLK, MOSI,

SS)

MISO,

Fall time see Figures

15, 16, 17, 18

SPI outputs (SPICLK, MOSI,

- 100 - 100 ns

MISO) SPI inputs (SPICLK, MOSI,

SS)

MISO,

- 2000 - 2000 ns

=12MHz Unit

osc

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

9397 750 14472

Product data Rev. 05 — 15 December 2004 45 of 55

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Table 9: AC characteristics

VDD = 3.0 V to 3.6 V, unless otherwise speciﬁed.

=−40°Cto+85°C for industrial, unless otherwise speciﬁed.

amb

Symbol Parameter Conditions Variable clock f

RCOSC

WDOSC

internal RC oscillator frequency 7.189 7.557 7.189 7.557 MHz internal Watchdog oscillator

frequency

osc

CLCL

CLKP

oscillator frequency clock cycle see Figure 20 55- --ns CLKLP active frequency 0 8 - - MHz

Glitch ﬁlter

glitch rejection, P1.5/ signal acceptance, P1.5/

RST pin - 50 - 50 ns

RST pin 125 - 125 - ns

glitch rejection, any pin except

RST

P1.5/ signal acceptance, any pin except

P1.5/

RST

External clock

CHCX

CLCX

CLCH

CHCL

HIGH time see Figure 20 22 t LOW time see Figure 20 22 t rise time see Figure 20 -5 -5ns fall time see Figure 20 -5 -5ns

Shift register (UART mode 0)

XLXL

QVXH

serial port clock cycle time 16 t output data set-up to clock rising

edge

XHQX

output data hold after clock rising edge

XHDX

input data hold after clock rising edge

DVXH

input data valid to clock rising edge 150 - 150 - ns

SPI interface

SPI

Operating frequency

3.0 MHz (Slave) 0

4.5 MHz (Master) -

SPICYC

Cycle time see Figures

15, 16, 17, 18

3.0 MHz (Slave)

4.5 MHz (Master)

[1]

Min Max Min Max

320 520 320 520 kHz

[2]

0 18 - - MHz

- 15 - 15 ns

50 - 50 - ns

− t

CLCL

CLCX

− t

CLCL

CHCX

- 888 - ns

CLCL

13 t

-t

- 722 - ns

CLCL

+ 20 - 75 ns

CLCL

-0 -0ns

CCLK

⁄

CCLK

⁄

CCLK

⁄

CCLK

- 333 - ns

- 222 - ns

=18MHz Unit

osc

22 - ns 22 - ns

0 3 MHz

- 4.5 MHz

9397 750 14472

Product data Rev. 05 — 15 December 2004 46 of 55

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Table 9: AC characteristics

…continued

VDD = 3.0 V to 3.6 V, unless otherwise speciﬁed.

=−40°Cto+85°C for industrial, unless otherwise speciﬁed.

amb

[1]

Symbol Parameter Conditions Variable clock f

Min Max Min Max

SPILEAD

Enable lead time (Slave) see Figures

17, 18

3.0 MHz 250 - 250 - ns

SPILAG

Enable lag time (Slave) see Figures

17, 18

3.0 MHz 250 - 250 - ns

SPICLKH

SPICLK high time see Figures

15, 16, 17, 18

SPICLKL

Master Slave

SPICLK low time see Figures

⁄

CCLK

⁄

CCLK

- 111 - ns

- 167 - ns

15, 16, 17, 18

SPIDSU

Master Slave

Data set-up time (Master or Slave) see Figures

⁄

CCLK

⁄

CCLK

100 - 100 - ns

- 111 - ns

- 167 - ns

15, 16, 17, 18

SPIDH

Data hold time (Master or Slave) see Figures

100 - 100 - ns

15, 16, 17, 18

SPIA

Access time (Slave) see Figures

0 80 0 80 ns

17, 18

SPIDIS

Disable time (Slave) see Figures

17, 18

3.0 MHz 0 160 - 160 ns

SPIDV

Enable to output data valid see Figures

15, 16, 17, 18

3.0 MHz 0 160 - 160 ns

4.5 MHz 0 111 - 111 ns

SPIOH

Output data hold time see Figures

0- 0-ns

15, 16, 17, 18

SPIR

Rise time see Figures

15, 16, 17, 18

SPI outputs (SPICLK, MOSI,

- 100 - 100 ns

MISO) SPI inputs (SPICLK, MOSI,

SS)

MISO,

- 2000 - 2000 ns

=18MHz Unit

osc

9397 750 14472

Product data Rev. 05 — 15 December 2004 47 of 55

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Table 9: AC characteristics

…continued

VDD = 3.0 V to 3.6 V, unless otherwise speciﬁed.

=−40°Cto+85°C for industrial, unless otherwise speciﬁed.

amb

Symbol Parameter Conditions Variable clock f

[1]

=18MHz Unit

osc

Min Max Min Max

SPIF

Fall time see Figures

15, 16, 17, 18

SPI outputs (SPICLK, MOSI,

- 100 - 100 ns

MISO) SPI inputs (SPICLK, MOSI,

SS)

MISO,

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz. [2] When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to

hold the device in reset at power-up until VDD has reached its speciﬁed level. When system power is removed VDD will fall below the

minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout

detect circuit may be required to hold the device in reset when VDD falls below the minimum speciﬁed operating voltage.

SPICLK

(CPOL = 0)

(output)

SPICLK

(CPOL = 1)

(output)

MISO

(input)

MOSI

(output)

SPIF

SPIDSU

SPIDV

MSB/LSB in

SPIF

SPICLKH

SPICLKL

SPIDH

CLCL

SPICLKL

SPIR

SPICLKH

SPIOH

- 2000 - 2000 ns

SPIR

LSB/MSB in

Master LSB/MSB outMaster MSB/LSB out

SPIDV

SPIR

002aaa156

Fig 15. SPI master timing (CPHA = 0).

9397 750 14472

Product data Rev. 05 — 15 December 2004 48 of 55

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

SPICLK

(CPOL = 0)

(output)

SPICLK

(CPOL = 1)

(output)

MISO

(input)

MOSI

(output)

SPIF

Fig 16. SPI master timing (CPHA = 1).

SPIF

SPIDSU

MSB/LSB in

SPIDV

SPICLKL

SPIF

SPICLKH

SPIDH

CLCL

SPIR

SPICLKH

SPICLKL

SPIOH

SPIR

LSB/MSB in

SPIDV

Master LSB/MSB outMaster MSB/LSB out

SPIDV

SPIR

002aaa157

SPIR

SPILEAD

SPICLK

(CPOL = 0)

(input)

SPICLK

(CPOL = 1)

(input)

MISO

(output)

MOSI

(input)

SPIA

SPIF

Slave MSB/LSB out

SPIDSUtSPIDH

MSB/LSB in LSB/MSB in

Fig 17. SPI slave timing (CPHA = 0).

SPIF

SPICLKH

SPICLKL

SPIOH t

SPIDV

CLCL

SPICLKL

SPIR

SPICLKH

SPIDSU

SPIOH

SPIDV

SPIR

SPIOH

Slave LSB/MSB out

SPIDSU

SPIDH

SPILAG

Not defined

002aaa158

SPIR

SPIDIS

9397 750 14472

Product data Rev. 05 — 15 December 2004 49 of 55

Philips Semiconductors

SPILEAD

SPICLK

(CPOL = 0)

(input)

SPICLK

(CPOL = 1)

(input)

MISO

(output)

SPIA

SPIR

SPIF

SPIOH

SPIDV

Not defined

CLCL

SPIF

SPICLKH

SPICLKL

Slave MSB/LSB out

SPICLKL

SPIR

SPICLKH

SPIOH

SPIDV

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

SPIR

SPIOH

SPIDV

Slave LSB/MSB out

SPILAG

SPIDIS

MOSI

(input)

Fig 18. SPI slave timing (CPHA = 1).

XLXL

Clock

Output Data

Write to SBUF

Input Data

Clear RI

QVXH

XHDV

01234567

Valid Valid Valid Valid Valid Valid Valid Valid

Fig 19. Shift register mode timing.

SPIDSUtSPIDH

MSB/LSB in LSB/MSB in

XHQX

XHDX

SPIDSU

SPIDH

002aaa159

Set TI

Set RI

002aaa425

- 0.5 V

0.45 V

0.2 V

CHCL

+ 0.9

- 0.1 V

CLCX

CHCX

CLCH

002aaa416

Fig 20. External clock timing.

9397 750 14472

Product data Rev. 05 — 15 December 2004 50 of 55

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Table 10: AC characteristics, ISP entry mode

VDD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

=−40°Cto+85°C for industrial, unless otherwise speciﬁed.

amb

Symbol Parameter Conditions Min Typ Max Unit

Fig 21. ISP entry waveform.

RST delay from VDD active 50 - - µs RST HIGH time 1 - 32 µs RST LOW time 1 - - µs

RST

002aaa426

12. Comparator electrical characteristics

Table 11: Comparator electrical characteristics

VDD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

=−40°Cto+85°C for industrial, unless otherwise speciﬁed.

amb

Symbol Parameter Conditions Min Typ Max Unit

CMRR common mode rejection ratio

[1] This parameter is characterized, but not tested in production.

offset voltage comparator inputs - - ±20 mV common mode range comparator inputs 0 - VDD− 0.3 V

[1]

--−50 dB response time - 250 500 ns comparator enable to output valid - - 10 µs input leakage current, comparator 0 < VIN<V

--±10 µA

9397 750 14472

Product data Rev. 05 — 15 December 2004 51 of 55

Philips Semiconductors

13. Package outline

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm

pin 1 index

114

w M

detail X

SOT361-1

v M

(A )

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A3b

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

max.

0.15

1.1

OUTLINE

VERSION

SOT361-1 MO-153

0.05

0.95

0.25

0.80

IEC JEDEC JEITA

0.30

0.19

(1)E(2) (1)

0.2

9.8

0.1

9.6

REFERENCES

eHELLpQZywv θ

4.5

4.3

0.65

6.6

6.2

0.75

0.50

0.4

0.3

EUROPEAN

PROJECTION

0.8

0.13 0.10.21

ISSUE DATE

99-12-27 03-02-19

0.5

Fig 22. SOT361-1 (TSSOP28).

9397 750 14472

Product data Rev. 05 — 15 December 2004 52 of 55

Philips Semiconductors

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

14. Revision history

Table 12: Revision history

Rev Date CPCN Description

05 20041215 - Product data (9397 750 14472)

Modiﬁcation:

• Added 18 MHz information.

04 20040106 - Product data (9397 750 12284); ECN 853-2406 01-A15015 dated 16 December 2003 03 20031006 - Product data (9397 750 12122); ECN 853-2406 30390 dated 30 September 2003 02 20030526 - Objective data (9397 750 11536) 01 20030514 - Preliminary data (9397 750 11386)

9397 750 14472

Product data Rev. 05 — 15 December 2004 53 of 55

Philips Semiconductors

15. Data sheet status

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

Level Data sheet status

I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips

II Preliminary data Qualiﬁcation This data sheetcontainsdata from the preliminary speciﬁcation.Supplementary datawill be published

III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

[1]

Product status

16. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitablefor the speciﬁed use without further testing or modiﬁcation.

[2][3]

Deﬁnition

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

at a later date.Philips Semiconductors reserves the right to change the speciﬁcationwithout notice, in order to improve the design and supply the best possible product.

right to make changes at anytime in order to improve the design, manufacturingandsupply. Relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, andmakes no representationsor warrantiesthatthese products are free frompatent,copyright, or mask workright infringement, unless otherwise speciﬁed.

18. Licenses

17. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors

Purchase of Philips I2C components

Purchase of Philips I under the Philips’ I

C system provided the system conforms to the I2C speciﬁcation deﬁned by Philips. This speciﬁcation can be ordered using the code 9398 393 40011.

C patent to use the components in the

C components conveys a license

Contact information

For additional information, please visit http://www.semiconductors.philips.com. For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. Fax: +31 40 27 24825

9397 750 14472

Product data Rev. 05 — 15 December 2004 54 of 55

Philips Semiconductors

Contents

P89LPC930/931

8-bit microcontrollers with two-clock 80C51 core

1 General description. . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.1 Pinning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7 Special function registers. . . . . . . . . . . . . . . . . . . . . 11

8 Functional description . . . . . . . . . . . . . . . . . . . . . . . 16

8.1 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.1 Clock deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.2 CPU clock (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . 16

8.2.3 Low speed oscillator option . . . . . . . . . . . . . . . . . . . 16

8.2.4 Medium speed oscillator option . . . . . . . . . . . . . . . . 16

8.2.5 High speed oscillator option. . . . . . . . . . . . . . . . . . . 16

8.2.6 Clock output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8.3 On-chip RC oscillator option . . . . . . . . . . . . . . . . . . 17

8.4 Watchdog oscillator option. . . . . . . . . . . . . . . . . . . . 17

8.5 External clock input option. . . . . . . . . . . . . . . . . . . . 17

8.6 CPU CLock (CCLK) wake-up delay . . . . . . . . . . . . . 19

8.7 CPU CLOCK (CCLK) modiﬁcation: DIVM register. . 19

8.8 Low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.9 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 19

8.10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8.10.1 External interrupt inputs. . . . . . . . . . . . . . . . . . . . . . 20

8.11 I/O ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8.11.1 Port conﬁgurations. . . . . . . . . . . . . . . . . . . . . . . . . . 22

8.11.2 Quasi-bidirectional output conﬁguration. . . . . . . . . . 22

8.11.3 Open-drain output conﬁguration. . . . . . . . . . . . . . . . 22

8.11.4 Input-only conﬁguration . . . . . . . . . . . . . . . . . . . . . . 22

8.11.5 Push-pull output conﬁguration . . . . . . . . . . . . . . . . . 22

8.11.6 Port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 22

8.11.7 Additional port features . . . . . . . . . . . . . . . . . . . . . . 24

8.12 Power monitoring functions . . . . . . . . . . . . . . . . . . . 24

8.12.1 Brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.12.2 Power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.13 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . 24

8.13.1 Idle mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.13.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.13.3 Total Power-down mode. . . . . . . . . . . . . . . . . . . . . . 25

8.14 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.14.1 Reset vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.15 Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . . . . . 26

8.15.1 Mode 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.15.2 Mode 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.15.3 Mode 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.15.4 Mode 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.15.5 Mode 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.15.6 Timer overﬂow toggle output . . . . . . . . . . . . . . . . . . 27

8.16 Real-Time clock/system timer . . . . . . . . . . . . . . . . . 27

8.17 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.17.1 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.17.2 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.17.3 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.17.4 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.17.5 Baud rate generator and selection . . . . . . . . . . . . . . 28

8.17.6 Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.17.7 Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.17.8 Double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.17.9 Transmit interrupts with double buffering

enabled (Modes 1, 2 and 3). . . . . . . . . . . . . . . . . . . 29

8.17.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and

3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.18 I2C-bus serial interface . . . . . . . . . . . . . . . . . . . . . . . 30

8.19 Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . 31

8.19.1 Typical SPI conﬁgurations. . . . . . . . . . . . . . . . . . . . . 33

8.20 Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.20.1 Internal reference voltage. . . . . . . . . . . . . . . . . . . . . 35

8.20.2 Comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 36

8.20.3 Comparators and power reduction modes . . . . . . . . 36

8.21 Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . . . . . . 36

8.22 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.23 Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.23.1 Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.23.2 Dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.24 Flash program memory. . . . . . . . . . . . . . . . . . . . . . . 38

8.24.1 General description. . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.24.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.24.3 Using Flash as data storage. . . . . . . . . . . . . . . . . . . 38

8.24.4 ISP and IAP capabilities of the P89LPC930/931 . . . 38

8.25 User conﬁguration bytes. . . . . . . . . . . . . . . . . . . . . . 40

8.26 User sector security bytes . . . . . . . . . . . . . . . . . . . . 40

9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10 Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 42

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 44

12 Comparator electrical characteristics . . . . . . . . . . . 51

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

16 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

18 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Date of release: 15 December 2004 Document order number: 9397 750 14472

Philips P89LPC930, P89LPC931 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features

3. Ordering information

3.1 Ordering options

4. Block diagram

5. Pinning information

5.1 Pinning

5.2 Pin description

6. Logic symbol

7. Special function registers

8. Functional description

8.1 Enhanced CPU

8.2 Clocks

8.3 On-chip RC oscillator option

8.4 Watchdog oscillator option

8.5 External clock input option

8.6 CPU CLock (CCLK) wake-up delay

8.8 Low power select

8.9 Memory organization

8.10 Interrupts

8.11 I/O ports

8.12 Power monitoring functions

8.13 Power reduction modes

8.14 Reset

8.15 Timers/counters 0 and 1

8.16 Real-Time clock/system timer

8.17 UART

8.18 I2C-bus serial interface

8.19 Serial Peripheral Interface (SPI)

8.20 Analog comparators

8.21 Keypad interrupt (KBI)

8.22 Watchdog timer

8.23 Additional features

8.24 Flash program memory

8.26 User sector security bytes

9. Limiting values

10. Static characteristics

11. Dynamic characteristics

12. Comparator electrical characteristics

13. Package outline

14. Revision history

15. Data sheet status

18. Licenses

17. Disclaimers