Philips P89LPC924, P89LPC925 Technical data

Philips P89LPC924, P89LPC925 Technical data

1. Introduction

2. Clocks

3. A/D converter

4. Interrupts

5. I/O ports

1. Introduction

2. Clocks

3. A/D converter

4. Interrupts

5. I/O ports

1.1 Pin Configuration

1.2 Special function registers

2.1 Enhanced CPU

2.2 Clock definitions

2.3 Clock output

2.4 On-chip RC oscillator option

2.5 Watchdog oscillator option

2.6 External clock input option

2.7 Oscillator Clock (OSCCLK) wake-up delay

2.8 CPU Clock (CCLK) modification: DIVM register

2.9 Low power select

3.1Features

3.2A/D operating modes

3.3Trigger modes

3.5 Clock divider

3.6 I/O pins used with A/D converter functions

3.7 Power-down and idle mode

4.1 Interrupt priority structure

4.2 External Interrupt pin glitch suppression

5.1 Port configurations

5.2 Quasi-bidirectional output configuration

5.3 Open drain output configuration

5.4 Input-only configuration

5.5 Push-pull output configuration

5.6 Port 0 analog functions

5.7 Additional port features

1.1 Pin Configuration

1.2 Special function registers

1.3 Memory organization

2.1 Enhanced CPU

2.2 Clock definitions

2.3 Clock output

2.4 On-chip RC oscillator option

2.5 Watchdog oscillator option

2.6 External clock input option

2.7 Oscillator Clock (OSCCLK) wake-up delay

2.8 CPU Clock (CCLK) modification: DIVM register

2.9 Low power select

3.1Features

3.2A/D operating modes

3.3Trigger modes

3.5 Clock divider

3.6 I/O pins used with A/D converter functions

3.7 Power-down and idle mode

4.1 Interrupt priority structure

4.2 External Interrupt pin glitch suppression

5.1 Port configurations

5.2 Quasi-bidirectional output configuration

5.3 Open drain output configuration

5.4 Input-only configuration

5.5 Push-pull output configuration

5.6 Port 0 analog functions

5.7 Additional port features

0 (0)

UM10108

P89LPC924/925 User manual

Rev. 02 — 2 March 2005 User manual

Document information

Info	Content

Keywords	P89LPC924, P89LPC925

Abstract	Technical information for the P89LPC924 and P89LPC925 devices.

Philips Semiconductors			UM10108
			P89LPC924/925 User manual
Revision history

Rev	Date	Description

02	20050302	Updated to include 18 MHz information.

01	20040628	Initial version (9397 750 13338).

Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com

User manual

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			P89LPC924/925 User manual

The P89LPC924/925 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC924/925 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC924/925 in order to reduce component count, board space, and system cost.

handbook, halfpage

KBI0/CMP2/P0.0 1

P1.7 2

P1.6 3

RST/P1.5 4

VSS 5

XTAL1/P3.1 6

CLKOUT/XTAL2/P3.0 7

INT1/P1.4 8

P89LPC924FDH

P89LPC925FDH

20 P0.1/CIN2B/KBI1/AD10

19 P0.2/CIN2A/KBI2/AD11

18 P0.3/CIN1B/KBI3/AD12

17 P0.4/CIN1A/KBI4/AD13/DAC1

16 P0.5/CMPREF/KBI5

15 VDD

14 P0.6/CMP1/KBI6

13 P0.7/T1/KBI7

Fig 1. TSSOP20 pin configuration.

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				P89LPC924/925 User manual
Table 1:	Pin description

Symbol		Pin	Type	Description
P0.0 to P0.7			I/O	Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset
				Port 0 latches are configured in the input only mode with the internal pull-up disabled.
				The operation of Port 0 pins as inputs and outputs depends upon the port configuration
				selected. Each port pin is configured independently. Refer to Section 5.1 “Port
				configurations” for details.
				The Keypad Interrupt feature operates with Port 0 pins.
				All pins have Schmitt triggered inputs.
				Port 0 also provides various special functions as described below:

	1		I/O	P0.0 — Port 0 bit 0.

			O	CMP2 — Comparator 2 output.

			I	KBI0 — Keyboard input 0.

	20		I/O	P0.1 — Port 0 bit 1.

			I	CIN2B — Comparator 2 positive input B.

			I	KBI1 — Keyboard input 1.

			I	AD10 — ADC1 channel 0 analog input.

	19		I/O	P0.2 — Port 0 bit 2.

			I	CIN2A — Comparator 2 positive input A.

			I	KBI2 — Keyboard input 2.

			I	AD11 — ADC1 channel 1analog input.

	18		I/O	P0.3 — Port 0 bit 3.

			I	CIN1B — Comparator 1 positive input B.

			I	KBI3 — Keyboard input 3.

			I	AD12 — ADC1 channel 2 analog input.

	17		I/O	P0.4 — Port 0 bit 4.

			I	CIN1A — Comparator 1 positive input A.

			I	KBI4 — Keyboard input 4.

			I	AD13 — ADC1 channel 3 analog input.

			I	DAC1 — Digital-to-analog converter output 1.

	16		I/O	P0.5 — Port 0 bit 5.

			I	CMPREF — Comparator reference (negative) input.

			I	KBI5 — Keyboard input 5.

	14		I/O	P0.6 — Port 0 bit 6.

			O	CMP1 — Comparator 1 output.

			I	KBI6 — Keyboard input 6.

	13		I/O	P0.7 — Port 0 bit 7.

			I/O	T1 — Timer/counter 1 external count input or overflow output.

			I	KBI7 — Keyboard input 7.

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Philips Semiconductors						UM10108
						P89LPC924/925 User manual
Table 1:	Pin description

Symbol		Pin	Type	Description
P1.0 to P1.7			I/O, I [1]	Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three
				pins as noted below. During reset Port 1 latches are configured in the input only mode
				with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs
				and outputs depends upon the port configuration selected. Each of the configurable port
				pins are programmed independently. Refer to Section 5.1 “Port configurations” for
				details.
				P1.2 and P1.3 are open drain when used as outputs. P1.5 is input only.
				All pins have Schmitt triggered inputs.
				Port 1 also provides various special functions as described below:

	12		I/O	P1.0		— Port 1 bit 0.

			O	TXD — Transmitter output for the serial port.

	11		I/O	P1.1		— Port 1 bit 1.

			I	RXD — Receiver input for the serial port.

	10		I/O	P1.2		— Port 1 bit 2 (open-drain when used as output).

			I/O	T0 — Timer/counter 0 external count input or overflow output (open-drain when used as
				output).

			I/O	SCL — I2C serial clock input/output.
	9		I/O	P1.3		— Port 1 bit 3 (open-drain when used as output).

			I			— External interrupt 0 input.
			I	INT0		— External interrupt 0 input.

			I/O	SDA — I2C serial data input/output.
	8		I/O	P1.4		— Port 1 bit 4.

			I			— External interrupt 1 input.
			I	INT1		— External interrupt 1 input.

	4		I	P1.5		— Port 1 bit 5 (input only).

			I		— External Reset input (if selected via FLASH configuration). A LOW on this pin
			I	RST
				resets the microcontroller, causing I/O ports and peripherals to take on their default
				states, and the processor begins execution at address 0. When using an oscillator
				frequency above 12 MHz, the reset input function of P1.5 must be enabled. An
				external circuit is required to hold the device in reset at powerup until VDD has
				reached its specified level. When system power is removed VDD will fall below the
				minimum specified operating voltage. When using an oscillator frequency above
				12 MHz, in some applications, an external brownout detect circuit may be
				required to hold the device in reset when VDD falls below the minimum specified
				operating voltage.

	3		I/O	P1.6		— Port 1 bit 6.

	2		I/O	P1.7		— Port 1 bit 7.

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Philips Semiconductors			UM10108
			P89LPC924/925 User manual
Table 1:	Pin description

Symbol	Pin	Type	Description
P3.0 to P3.1		I/O	Port 3: Port 3 is an 2-bit I/O port with a user-configurable output type. During reset
			Port 3 latches are configured in the input only mode with the internal pull-up disabled.

The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1 “Port configurations” for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

7I/O P3.0 — Port 3 bit 0.

O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is selected via the FLASH configuration.

O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the real time clock/system timer.

	6	I/O	P3.1 — Port 3 bit 1.
		I	XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when
			selected via the FLASH configuration). It can be a port pin if internal RC oscillator or
			Watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used
			to generate the clock for the real time clock/system timer.

VSS	5	I	Ground: 0 V reference.
VDD	15	I	Power Supply: This is the power supply voltage for normal operation as well as Idle
			and Power-down modes.

[1] Input/Output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

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Philips P89LPC924, P89LPC925 Technical data

Philips Semiconductors			UM10108
			P89LPC924/925 User manual

	PROGRAMMABLE		CPU
	OSCILLATOR DIVIDER		CPU
	OSCILLATOR DIVIDER		CLOCK



CRYSTAL	CONFIGURABLE		ON-CHIP
OR	CONFIGURABLE		RC
OR	OSCILLATOR		RC
RESONATOR	OSCILLATOR		OSCILLATOR
	P89LPC924/925		HIGH PERFORMANCE
		ACCELERATED 2-CLOCK 80C51 CPU
	4 kB/8 kB			UART
	CODE FLASH
		INTERNAL BUS
	256-BYTE			REAL-TIME CLOCK/
	DATA RAM			SYSTEMTIMER
	PORT 3			I2C
	CONFIGURABLE I/Os
	PORT 1			TIMER 0
	CONFIGURABLE I/Os			TIMER 1
	PORT 0			WATCHDOGTIMER
	CONFIGURABLE I/Os			AND OSCILLATOR
	KEYPAD			ANALOG
	INTERRUPT			COMPARATORS
				ADC1/DAC1

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

002aaa786

Fig 2. P89LPC924/925 block diagram.

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Philips Semiconductors			UM10108
			P89LPC924/925 User manual

Remark: Special Function Registers (SFRs) accesses are restricted in the following ways:

•User must not attempt to access any SFR locations not defined.

•Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

•SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

–‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

–‘0’ must be written with ‘0’, and will return a ‘0’ when read.

–‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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Table 2:

Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

ACC*

Accumulator

E0H

00000000

ADCON1

A/D control register 1

97H

ENBI1

ENADCI

TMM1

EDGE1

ADCI1

ENADC1

ADCS11

ADCS10

00000000

ADINS

A/D input select

A3H

ADI13

ADI12

ADI11

ADI10

00000000

ADMODA

A/D mode register A

C0H

BNDI1

BURST1

SCC1

SCAN1

00000000

ADMODB

A/D mode register B

A1H

CLK2

CLK1

CLK0

ENDAC1

BSA1

000x0000

AD1BH

A/D_1 boundary HIGH

C4H

11111111

AD1BL

A/D_1 boundary LOW

BCH

00000000

AD1DAT0

A/D_1 data register 0

D5H

00000000

AD1DAT1

A/D_1 data register 1

D6H

00000000

AD1DAT2

A/D_1 data register 2

D7H

00000000

AD1DAT3

A/D_1 data register 3

F5H

00000000

AUXR1

Auxiliary function register

A2H

CLKLP

EBRR

ENT1

ENT0

SRST

DPS

00[1]

000000x0

Bit address

B register

F0H

00000000

BRGR0[2]

Baud rate generator rate

BEH

00000000

LOW

BRGR1[2]

Baud rate generator rate

BFH

00000000

HIGH

BRGCON

Baud rate generator control

BDH

SBRGS

BRGEN

xxxxxx00

CMP1

Comparator 1 control register

ACH

CE1

CP1

CN1

OE1

CO1

CMF1

00[1]

xx000000

CMP2

Comparator 2 control register

ADH

CE2

CP2

CN2

OE2

CO2

CMF2

00[1]

xx000000

DIVM

CPU clock divide-by-M

95H

00000000

control

DPTR

Data pointer (2 bytes)

DPH

Data pointer HIGH

83H

00000000

DPL

Data pointer LOW

82H

00000000

FMADRH

Program Flash address HIGH

E7H

00000000

Semiconductors Philips

manual User P89LPC924/925

UM10108

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2005 March 2 — 02 .Rev

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Table 2:

Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

FMADRL

Program Flash address LOW

E6H

00000000

FMCON

Program Flash control (Read)

E4H

BUSY

HVA

HVE

01110000

Program Flash control (Write)

E4H

FMCMD.

FMCMD. FMCMD. FMCMD. FMCMD. FMCMD.

FMDATA

Program Flash data

E5H

00000000

I2ADR

I2C slave address register

DBH

I2ADR.6

I2ADR.5

I2ADR.4

I2ADR.3

I2ADR.2

I2ADR.1

I2ADR.0

00000000

Bit address

I2CON*

I2C control register

D8H

I2EN

STA

STO

CRSEL

x00000x0

I2DAT

I2C data register

DAH

I2SCLH

Serial clock generator/SCL

DDH

00000000

duty cycle register HIGH

I2SCLL

Serial clock generator/SCL

DCH

00000000

duty cycle register LOW

I2STAT

I2C status register

D9H

STA.4

STA.3

STA.2

STA.1

STA.0

11111000

Bit address

IEN0*

Interrupt enable 0

A8H

EWDRT

EBO

ES/ESR

ET1

EX1

ET0

EX0

00[1]

00000000

Bit address

IEN1*

Interrupt enable 1

E8H

EAD

EST

EKBI

EI2C

00[1]

00x00000

Bit address

IP0*

Interrupt priority 0

B8H

PWDRT

PBO

PS/PSR

PT1

PX1

PT0

PX0

00[1]

x0000000

IP0H

Interrupt priority 0 HIGH

B7H

PWDRT

PBOH

PSH/

PT1H

PX1H

PT0H

PX0H

00[1]

x0000000

PSRH

Bit address

IP1*

Interrupt priority 1

F8H

PAD

PST

PKBI

PI2C

00[1]

00x00000

IP1H

Interrupt priority 1 HIGH

F7H

PADH

PSTH

PCH

PKBIH

PI2CH

00[1]

00x00000

KBCON

Keypad control register

94H

PATN

KBIF

00[1]

xxxxxx00

_SEL

KBMASK

Keypad interrupt mask

86H

00000000

KBPATN

Keypad pattern register

93H

11111111

Semiconductors Philips

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UM10108

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2005 March 2 — 02 .Rev

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Table 2:

Special function registers

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Bit address

P0*

Port 0

80H

T1/KB7

CMP1

CMPREF

CIN1A

CIN1B

CIN2A

CIN2B

CMP2

[1]

/KB6

/KB5

/KB4

/KB3

/KB2

/KB1

/KB0

Bit address

P1*

Port 1

90H

T0/SCL

RXD

TXD

[1]

RST

INT1

INT0/

SDA

Bit address

P3*

Port 3

B0H

XTAL1

XTAL2

[1]

P0M1

Port 0 output mode 1

84H

(P0M1.7)

(P0M1.6)

(P0M1.5)

(P0M1.4)

(P0M1.3)

(P0M1.2)

(P0M1.1)

(P0M1.0)

11111111

P0M2

Port 0 output mode 2

85H

(P0M2.7)

(P0M2.6)

(P0M2.5)

(P0M2.4)

(P0M2.3)

(P0M2.2)

(P0M2.1)

(P0M2.0)

00000000

P1M1

Port 1 output mode 1

91H

(P1M1.7)

(P1M1.6)

(P1M1.4)

(P1M1.3)

(P1M1.2)

(P1M1.1)

(P1M1.0)

D3[1]

11x1xx11

P1M2

Port 1 output mode 2

92H

(P1M2.7)

(P1M2.6)

(P1M2.4)

(P1M2.3)

(P1M2.2)

(P1M2.1)

(P1M2.0)

00[1]

00x0xx00

P3M1

Port 3 output mode 1

B1H

(P3M1.1)

(P3M1.0)

03[1]

xxxxxx11

P3M2

Port 3 output mode 2

B2H

(P3M2.1)

(P3M2.0)

00[1]

xxxxxx00

PCON

Power control register

87H

SMOD1

SMOD0

BOPD

BOI

GF1

GF0

PMOD1

PMOD0

00000000

PCONA

Power control register A

B5H

RTCPD

VCPD

ADPD

I2PD

SPD

00[1]

00000000

Bit address

PSW*

Program status word

D0H

RS1

RS0

00H

00000000

PT0AD

Port 0 digital input disable

F6H

PT0AD.5

PT0AD.4

PT0AD.3

PT0AD.2

PT0AD.1

00H

xx00000x

RSTSRC

Reset source register

DFH

BOF

POF

R_BK

R_WD

R_SF

R_EX

[3]

RTCCON

Real-time clock control

D1H

RTCF

RTCS1

RTCS0

ERTC

RTCEN

60[1][6]

RTCH

Real-time clock register HIGH

D2H

00[6]

00000000

RTCL

Real-time clock register LOW

D3H

00[6]

00000000

SADDR

Serial port address register

A9H

00000000

SADEN

Serial port address enable

B9H

00000000

SBUF

Serial Port data buffer

99H

xxxxxxxx

Bit address

SCON*

Serial port control

98H

SM0/FE

SM1

SM2

REN

TB8

RB8

00000000

Semiconductors Philips

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UM10108

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Table 2:

Special function registers

Philips

* indicates SFRs that are bit addressable.

Name

Description

SFR

Bit functions and addresses

Reset value

addr.

MSB

LSB

Hex

Binary

Semiconductors

SSTAT

Serial port extended status

BAH

DBMOD

INTLO

CIDIS

DBISEL

STINT

00000000

Stack pointer

81H

00000111

TAMOD

Timer 0 and 1 auxiliary mode

8FH

T1M2

T0M2

xxx0xxx0

Bit address

TCON*

Timer 0 and 1 control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00000000

TH0

Timer 0 HIGH

8CH

00000000

TH1

Timer 1 HIGH

8DH

00000000

TL0

Timer 0 LOW

8AH

00000000

TL1

Timer 1 LOW

8BH

00000000

TMOD

Timer 0 and 1 mode

89H

T1GATE

T1C/T

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

00000000

TRIM

Internal oscillator trim register

96H

RCCLK

ENCLK

TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5] [6]

WDCON

Watchdog control register

A7H

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

[4] [6]

WDL

Watchdog load

C1H

11111111

WFEED1

Watchdog feed 1

C2H

WFEED2

Watchdog feed 2

C3H

[1] All ports are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reflects the cause of the P89LPC924/925 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is

xx110000.

.reservedrightsAll.2004.V.NElectronicsPhilipsKoninklijke©

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power-on reset.

UM10108

Other resets will not affect WDTOF.

manualUserP89LPC924/925

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset source that affects these SFRs is power-on reset.

Philips Semiconductors		UM10108
		P89LPC924/925 User manual
	1.3 Memory organization

FF00h	IAP entry-
	IAP entry-
FFEFh	points

1FFFh

ISP CODE (512B)*

1E00h

SECTOR 7

1C00h

1BFFh

SECTOR 6

1800h

17FFh

SECTOR 5

1400h

13FFh

SECTOR 4

1000h

0FFFh

SECTOR 3

0C00h

0BFFh

SECTOR 2

0800h

07FFh

SECTOR 1

0400h

03FFh

SECTOR 0

0000h

Read-protected

IAP calls only

IDATA routines entry points for:

-51 ASM. code -C code

ISP serial loader entry points for:

-UART (auto-baud) -I2C, SPI, etc.*

Flexible choices: -as supplied (UART) -Philips libraries* -user-defined

FFEFh
FFEFh		SPECIAL FUNCTION	IDATA (incl. DATA)
			IDATA (incl. DATA)
FF1Fh	entry		128 BYTES ON-CHIP
FF1Fh		REGISTERS	128 BYTES ON-CHIP
			DATA MEMORY (STACK
	points
		(DIRECTLY ADDRESSABLE)
FF00h			AND INDIR. ADDR.)



			DATA
1FFFh			128 BYTES ON-CHIP
1FFFh			DATA MEMORY (STACK,
			DIRECT AND INDIR. ADDR.)
			4 REG. BANKS R[7:0]
1E00h
1E00h			data memory
			data memory
			(DATA, IDATA)

002aaa948

Note: ISP code is located at the end of Sector 4 on the LPC924, and at the end of Sector 7 on the LPC925.

Fig 3. P89LPC924/925 memory map.

The various P89LPC924/925 memory spaces are as follows:

DATA — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.

IDATA — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

SFR — Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC924/925 has 4 kB/8 kB of on-chip Code memory.

Table 3:	Data RAM arrangement
Type	Data RAM	Size (bytes)
DATA	Directly and indirectly addressable memory	128
IDATA	Indirectly addressable memory	256

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The P89LPC924/925 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

The P89LPC924/925 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources and can also be optionally divided to a slower frequency (see Figure 5 and Section 2.8 “CPU Clock (CCLK) modification: DIVM register”). Note: fosc is defined as the OSCCLK frequency.

CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is CCLK/2.

2.2.1Oscillator Clock (OSCCLK)

The P89LPC924/925 provides several user-selectable oscillator options. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip Watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz.

2.2.2Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.

2.2.3Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.

2.2.4High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration.When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit

is required to hold the device in reset at powerup until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.

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The P89LPC924/925 supports a user-selectable clock output function on the XTAL2 / CLKOUT pin when the crystal oscillator is not being used. This condition occurs if a different clock source has been selected (on-chip RC oscillator, Watchdog oscillator, external clock input on X1) and if the Real-time Clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC924/925. This output is enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of bits 5:0 of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.

quartz crystal or ceramic resonator

P89LPC924/925

XTAL1

[1]

XTAL2

002aaa951

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

(1)A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals (see text).

Fig 4. Using the crystal oscillator.

The P89LPC924/925 has a TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ± 1 %. (Note: the initial value is better than 1 %; please refer to the data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency.

Table 4:	On-chip RC oscillator trim register (TRIM - address 96h) bit allocation
Bit	7	6	5	4	3	2	1	0

Symbol	RCCLK	ENCLK	TRIM.5	TRIM.4	TRIM.3	TRIM.2	TRIM.1	TRIM.0

Reset	0	0		Bits 5:0 loaded with factory stored value during reset.

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Table 5: On-chip RC oscillator trim register (TRIM - address 96h) bit description

Bit Symbol Description

0	TRIM.0
1	TRIM.1

2	TRIM.2

3	TRIM.3

4	TRIM.4

5	TRIM.5

Trim value. Determines the frequency of the internal RC oscillator. During reset, these bits are loaded with a stored factory calibration value. When writing to either bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value by reading this register, modifying bits 6 or 7 as required, and writing the result to this register.

6	ENCLK	when = 1, CCLK/2 is output on the XTAL2 pin provided the crystal oscillator is not being used.
7	RCCLK	when = 1, selects the RC Oscillator output as the CPU clock (CCLK)

The Watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

In this configuration, the processor clock is derived from an external source driving the XTAL1 / P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at powerup until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.

XTAL1	High freq.
XTAL2	Med.freq.	RTC
	Low freq.
		ADC1/
		DAC1

OSCCLK

CCLK

DIVM

CPU

OSCILLATOR

(7.3728 MHz)

WDT

WATCHDOG

OSCILLATOR

(400 kHz)

PCLK

TIMER 0 and

I2C

BAUD RATE

UART

TIMER 1

GENERATOR

002aaa790

Fig 5. Block diagram of oscillator control.

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The P89LPC924/925 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections, the delay is 992 OSCCLK cycles plus 60 µs to 100 µs. If the clock source is either the internal RC oscillator or the Watchdog oscillator, the delay is 224 OSCCLK cycles plus 60 µs to 100 µs.

The OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK frequency using the following formula:

CCLK frequency = fosc / (2N)

Where: fosc is the frequency of OSCCLK

N is the value of DIVM.

Since N ranges from 0 to 255, the CCLK frequency can be in the range of fosc to fosc/510. (for N = 0, CCLK = fosc).

This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events other than those that can cause interrupts (i.e., events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. This can allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

The P89LPC924/925 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.

The P89LPC924/925 has an 8-bit, 4-channel, multiplexed successive approximation analog-to-digital converter module (ADC1) and one DAC module (DAC1). A block diagram of the A/D converter is shown in Figure 6. The A/D consists of a 4-input multiplexer which feeds a sample and hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the successive approximation register (SAR) drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.

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	COMP
INPUT	+
INPUT	SAR
MUX	SAR
MUX	–
	–
		CONTROL
	8	LOGIC
	DAC1
	CCLK
		002aaa791

Fig 6. A/D converter block diagram.

•An 8-bit, 4-channel, multiplexed input, successive approximation A/D converter

•Four A/D result registers

•Six operating modes

–Fixed channel, single conversion mode

–Fixed channel, continuous conversion mode

–Auto scan, single conversion mode

–Auto scan, continuous conversion mode

–Dual channel, continuous conversion mode

–Single step mode

•Three conversion start modes

–Timer triggered start

–Start immediately

–Edge triggered

•8-bit conversion time of ≥ 3.9 µs at an ADC clock of 3.3 MHz

•Interrupt or polled operation

•Boundary limits interrupt

•DAC output to a port pin with high output impedance

•Clock divider

•Power-down mode

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3.2.1Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel (See Table 6). An interrupt, if enabled, will be generated after the conversion completes. The input channel is selected in the ADINS register. This mode is selected by setting the SCAN1 bit in the ADMODA register.

Table 6: Input channels and Result registers for fixed channel single, auto scan single, and autoscan continuous conversion modes.

Result register	Input channel	Result register	Input channel
AD1DAT0	AD10	AD1DAT2	AD12

AD1DAT1	AD11	AD1DAT3	AD13

3.2.2Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result registers Table 7. An interrupt, if enabled, will be generated after every four conversions. Additional conversion results will again cycle through the four result registers, overwriting the previous results. Continuous conversions continue until terminated by the user. This mode is selected by setting the SCC1 bit in the ADMODA register.

3.2.3Auto scan, single conversion mode

Any combination of the four input channels can be selected for conversion by setting a channel’s respective bit in the ADINS register. The channels are converted from LSB to MSB order (in ADINS). A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel (See Table 6). An interrupt, if enabled, will be generated after all selected channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode. This mode is selected by setting the SCAN1 bit in the ADMODA register.

Table 7: Result registers and conversion results for fixed channel, continuous conversion mode.

Result register	Contains
AD1DAT0	Selected channel, first conversion result

AD1DAT1	Selected channel, second conversion result

AD1DAT2	Selected channel, third conversion result

AD1DAT3	Selected channel, forth conversion result

3.2.4Auto scan, continuous conversion mode

Any combination of the four input channels can be selected for conversion by setting a channel’s respective bit in the ADINS register. The channels are converted from LSB to MSB order (in ADINS). A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel (See Table 6). An interrupt, if enabled, will be generated after all selected channels have been converted. The process will repeat starting with the first selected channel. Additional

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conversion results will again cycle through the result registers of the selected channels, overwriting the previous results. Continuous conversions continue until terminated by the user. This mode is selected by setting the BURST1 bit in the ADMODA register.

3.2.5Dual channel, continuous conversion mode

Any combination of two of the four input channels can be selected for conversion. The result of the conversion of the first channel is placed in the first result register. The result of the conversion of the second channel is placed in the second result register. The first channel is again converted and its result stored in the third result register. The second channel is again converted and its result placed in the fourth result register (See Table 8). An interrupt is generated, if enabled, after every set of four conversions (two conversions per channel). This mode is selected by setting the SCC1 bit in the ADMODA register.

Table 8: Result registers and conversion results for dual channel, continuous conversion mode.

Result register	Contains
AD1DAT0	First channel, first conversion result

AD1DAT1	Second channel, first conversion result

AD1DAT2	First channel, second conversion result

AD1DAT3	Second channel, second conversion result

3.2.6Single step

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any combination of the four input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next start condition. The result of each channel is placed in the result register which corresponds to the selected input channel (See Table 6). May be used with any of the start modes. This mode is selected by clearing the BURST1, SCC1, and SCAN1 bits in the ADMODA register.

3.2.7Conversion mode selection bits

The A/D uses three bits in ADMODA to select the conversion mode. These mode bits are summarized in Table 9, below. Combinations of the three bits, other than the combinations shown, are undefined.

Table 9: Conversion mode bits.

BURST1	SCC1	Scan1	ADC1 conversion	BURST0	SCC0	Scan0	ADC0 conversion
			mode				mode
0	0	0	single step	0	0	0	single step

0	0	1	fixed	0	0	1	fixed
			channel,single				channel,single

			auto scan, single				auto scan, single

0	1	0	fixed channel,	0	1	0	fixed channel,
			continuous				continuous

			dual channel,				dual channel,
			continuous				continuous

1	0	0	auto scan,	1	0	0	auto scan,
			continuous				continuous

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3.3.1Timer triggered start

An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all A/D operating modes. This mode is selected by the TMM1 bit and the ADCS11 and ADCS10 bits (See Table 11).

3.3.2Start immediately

Programming this mode immediately starts a conversion. This start mode is available in all A/D operating modes. This mode is selected by setting the ADCS11 and ADCS10 bits in the ADCON1 register (See Table 11).

3.3.3Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all A/D operating modes. This mode is selected by setting the ADCS11 and ADCS10 bits in the ADCON1 register (See Table 11).

3.3.4Boundary limits interrupt

The A/D converter has both a HIGH and LOW boundary limit register. After the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary HIGH and LOW registers. If the four MSBs of the conversion are outside the limit an interrupt will be generated, if enabled. If the conversion result is within the limits, the boundary limits will again be compared after all eight bits have been converted. An interrupt will be generated, if enabled, if the result is outside the boundary limits. The boundary limit may be disabled by clearing the boundary limit interrupt enable.

3.4DAC output to a port pin with high-impedance

The AD0DAT3 register is used to hold the value fed to the DAC. After a value has been written to AD0DAT3 the DAC output will appear on the DAC0 pin. The DAC output is enabled by the ENDAC0 bit in the ADMODB register (See Table 15).

The A/D converter requires that its internal clock source be in the range of 500 kHz to 3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose (See Table 15).

The analog input pins used with for the A/D converter have a digital input and output function. In order to give the best analog performance, pins that are being used with the ADC or DAC should have their digital outputs and inputs disabled and have the 5 V tolerance disconnected. Digital outputs are disabled by putting the port pins into the input-only mode as described in the Port Configurations section (see Table 21).

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Digital inputs will be disconnected automatically from these pins when the pin has been selected by setting its corresponding bit in the ADINS register and the A/D or DAC has been enabled. Pins selected in ADINS will be 3 V tolerant provided that the A/D is enabled and the device is not in power-down, otherwise the pin will remain 5 V tolerant.

In idle mode the A/D converter, if enabled, will continue to function and can cause the device to exit idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is enabled, it will consume power. Power can be reduced by disabling the A/D.

Table 10: A/D Control register 1 (ADCON1 - address 97h) bit allocation

Bit	7	6	5	4	3	2	1	0

Symbol	ENBI1	ENADCI1	TMM1	EDGE1	ADCI1	ENADC1	ADCS11	ADCS10

Reset	0	0	0	0	0	0	0	0

Table 11: A/D Control register 1 (ADCON1 - address 97h) bit description

Bit	Symbol		Description

0	ADCS10		A/D start mode bits [11:10]:
			00 — Timer Trigger Mode when TMM1 = 1. Conversions starts on overflow of
1	ADCS11
			Timer 0. Stop mode when TMM1 = 0, no start occurs.
			01 — Immediate Start Mode. Conversions starts immediately.
			10 — Edge Trigger Mode. Conversion starts when edge condition defined by bit
			EDGE1 occurs.

2	ENADC1		Enable A/D channel 1. When set = 1, enables ADC1. Must also be set for D/A
			operation of this channel.

3	ADCI1		A/D Conversion complete Interrupt 1. Set when any conversion or set of multiple
			conversions has completed. Cleared by software.

4	EDGE1		When = 0, an Edge conversion start is triggered by a falling edge on P1.4.
			When = 1, an Edge conversion start is triggered by a rising edge on P1.4.

5	TMM1		Timer Trigger Mode 1. Selects either stop mode (TMM1 = 0) or timer trigger mode
			(TMM1 = 1) when the ADCS11 and ADCS10 bits = 00.

6	ENADCI1		Enable A/D Conversion complete Interrupt 1. When set, will cause an interrupt if the
			ADCI1 flag is set and the A/D interrupt is enabled.

7	ENBI1		Enable A/D boundary interrupt 1. When set, will cause an interrupt if the boundary
			interrupt 1 flag, BNDI1, is set and the A/D interrupt is enabled.

Table 12: A/D Mode Register A (ADMODA - address C0h) bit allocation

Bit	7	6	5	4	3	2	1	0
Symbol	BNBI1	BURST1	SCC1	SCAN1	-	-	-	-

Reset	0	0	0	0	0	0	0	0

Table 13: A/D Mode Register A (ADMODA - address C0h) bit description

Bit	Symbol		Description

0:3	-		reserved

4	SCAN1		when = 1, selects single conversion mode (auto scan or fixed channel) for ADC1

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Table 13: A/D Mode Register A (ADMODA - address C0h) bit description

Bit	Symbol		Description
5	SCC1		when = 1, selects fixed channel, continuous conversion mode for ADC1

6	BURST1		when = 1, selects auto scan, continuous conversion mode for ADC1

7	BNBI1		ADC1 boundary interrupt flag. When set, indicates that the converted result from
			ADC1 is outside of the range defined by the ADC1 boundary registers

Table 14: A/D Mode Register B (ADMODB - address A1h) bit allocation

Bit	7	6	5	4	3	2	1	0

Symbol	CLK2	CLK1	CLK0	-	ENDAC1	-	BSA1	-

Reset	0	0	0	0	0	0	0	0

Table 15: A/D Mode Register B (ADMODB - address A1h) bit description

Bit	Symbol		Description

0	-		reserved

1	BSA1		ADC1 Boundary Select All. When = 1, BNDI1 will be set if any ADC1 input exceeds
			the boundary limits. When = 0, BNDI1 will be set only if the AD10 input exceeded
			the boundary limits.

2	-		reserved

3	ENDAC1		When = 1 selects DAC mode for ADC1; when = 0 selects ADC mode.

4	-		reserved

5	CLK0
6	CLK1

7	CLK2

Clock divider to produce the ADC clock. Divides CCLK by the value indicated below. The resulting ADC clock should be 3.3 MHz or less. A minimum of 0.5 MHz is required to maintain A/D accuracy. A/D start mode bits:

CLK2:0 — divisor 000 — 1

001 — 2

010 — 3

011 — 4

100 — 5

101 — 6

110 — 7

111 — 8

Table 16: A/D Input Select register (ADINS - address A3h) bit allocation

Bit	7	6	5	4	3	2	1	0
Symbol	AIN13	AIN12	AIN11	AIN10	-	-	-	-

Reset	0	0	0	0	0	0	0	0

Table 17: A/D Input Select register (ADINS - address A3h) bit description

Bit	Symbol		Description
0:3	-		reserved

4	AIN10		when set, enables the AD10 pin for sampling and conversion

5	AIN11		when set, enables the AD11 pin for sampling and conversion

6	AIN12		when set, enables the AD12 pin for sampling and conversion

7	AIN13		when set, enables the AD13 pin for sampling and conversion

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The P89LPC924/925 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P89LPC924/925’s 12 interrupt sources.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global enable bit, EA, which enables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced.

If requests of the same priority level are pending at the start of an instruction cycle, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used for pending requests of the same priority level. Table 19 summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may wake up the CPU from a Power-down mode.

Table 18: Interrupt priority level

Priority bits
IPxH	IPx	Interrupt priority level

0	0	Level 0 (lowest priority)

0	1	Level 1

1	0	Level 2

1	1	Level 3

There are four SFRs associated with the four interrupt levels: IP0, IP0H, IP1, IP1H. Every interrupt has two bits in IPx and IPxH (x = 0,1) and can therefore be assigned to one of four levels, as shown in Table 18.

The P89LPC924/925 has two external interrupt inputs in addition to the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by clearing or setting bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is triggered by a LOW level detected at the INTn pin. If ITn = 1, external interrupt n is edge triggered. In this mode if consecutive samples of the INTn pin show a HIGH level in one cycle and a LOW level in the next cycle, interrupt request flag IEn in TCON is set, causing an interrupt request.

Since the external interrupt pins are sampled once each machine cycle, an input HIGH or LOW level should be held for at least one machine cycle to ensure proper sampling. If the external interrupt is edge-triggered, the external source has to hold the request pin HIGH

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for at least one machine cycle, and then hold it LOW for at least one machine cycle. This is to ensure that the transition is detected and that interrupt request flag IEn is set. IEn is automatically cleared by the CPU when the service routine is called.

If the external interrupt is level-triggered, the external source must hold the request active until the requested interrupt is generated. If the external interrupt is still asserted when the interrupt service routine is completed, another interrupt will be generated. It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive, it simply tracks the input pin level.

If an external interrupt has been programmed as level-triggered and is enabled when the P89LPC924/925 is put into Power-down or Idle mode, the interrupt occurrence will cause the processor to wake up and resume operation. Refer to Section 6.3 “Power reduction modes” on page 32 for details.

Most of the P89LPC924/925 pins have glitch suppression circuits to reject short glitches (please refer to the P89LPC924/925 data sheet, Dynamic characteristics for glitch filter specifications). However, pins SDA/INT0/P1.3 and SCL/T0/P1.2 do not have the glitch suppression circuits. Therefore, INT1 has glitch suppression while INT0 does not.

Table 19: Summary of interrupts

Description	Interrupt flag	Vector	Interrupt enable	Interrupt	Arbitration	Power-
	bit(s)	address	bit(s)	priority	ranking	down
						wake-up
External interrupt 0	IE0	0003h	EX0 (IEN0.0)	IP0H.0,IP0.0	1 (highest)	Yes

Timer 0 interrupt	TF0	000Bh	ET0 (IEN0.1)	IP0H.1,IP0.1	4	No

External interrupt 1	IE1	0013h	EX1 (IEN0.2)	IP0H.2,IP0.2	7	Yes

Timer 1 interrupt	TF1	001Bh	ET1 (IEN0.3)	IP0H.3,IP0.3	10	No

Serial port TX and RX	TI and RI	0023h	ES/ESR (IEN0.4)	IP0H.4,IP0.4	13	No

Serial port RX	RI

Brownout detect	BOF	002Bh	EBO (IEN0.5)	IP0H.5,IP0.5	2	Yes

Watchdog timer/Real-time clock	WDOVF/RTCF	0053h	EWDRT (IEN0.6)	IP0H.6,IP0.6	3	Yes

I2C interrupt	SI	0033h	EI2C (IEN1.0)	IP0H.0,IP0.0	5	No
KBI interrupt	KBIF	003Bh	EKBI (IEN1.1)	IP0H.0,IP0.0	8	Yes

Comparators 1 and 2 interrupts	CMF1/CMF2	0043h	EC (IEN1.2)	IP0H.0,IP0.0	11	Yes

Serial port TX	TI	006Bh	EST (IEN1.6)	IP0H.0,IP0.0	12	No

ADC	ADCI1,BNDI1	0073h	EAD (IEN1.7)	IP1H.7,IP1.7	15 (lowest)	No

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Philips Semiconductors			UM10108
			P89LPC924/925 User manual

	IE0
	EX0
	IE1
	EX1
	BOPD
	EBO
RTCF	KBIF	WAKE-UP
ERTC	EKBI	(IF IN POWER-DOWN)
(RTCCON.1)
WDOVF	EWDRT
	EWDRT
	CMF2
	CMF1
	EC
	EA (IE0.7)
	TF0
	ET0
	TF1
	ET1
	TI & RI/RI
	ES/ESR
	TI	INTERRUPT
	EST	TO CPU

EI2C

ENADCI1

ADCI1

ENBI1

BNDI1

EAD

002aaa792

Fig 7. Interrupt sources, interrupt enables, and power-down wake up sources.

The P89LPC924/925 has three I/O ports: Port 0, Port 1, and Port 3. Ports 0 and 1 are 8-bit ports and Port 3 is a 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen (see Table 20).

Table 20: Number of I/O pins available

Clock source	Reset option			Number of I/O
				pins

On-chip oscillator or Watchdog	No external reset (except during power up)			26
oscillator

	External RST pin supported			25
	External RST pin supported			25

External clock input	No external reset (except during power up)			25

	External		pin supported[1]	24
	External	RST	pin supported[1]	24
Low/medium/high speed oscillator	No external reset (except during power up)			24
(external crystal or resonator)
	External		pin supported[1]	23
	External	RST	pin supported[1]	23

[1]Required for operation above 12 MHz.

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Philips Semiconductors			UM10108
			P89LPC924/925 User manual

All but three I/O port pins on the P89LPC924/925 may be configured by software to one of four types on a pin-by-pin basis, as shown in Table 21. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin.

P1.5 (RST) can only be an input and cannot be configured.

P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or open drain.

Table 21: Port output configuration settings

PxM1.y	PxM2.y	Port output mode
0	0	Quasi-bidirectional

0	1	Push-pull

1	0	Input only (high-impedance)

1	1	Open drain

Quasi-bidirectional outputs can be used both as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch for the pin contains a logic 1. This very weak pull-up sources a very small current that will pull the pin HIGH if it is left floating.

A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled LOW by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin LOW under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the port pin below its input threshold voltage.

The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up LOW-to-HIGH transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the port pin HIGH.

The quasi-bidirectional port configuration is shown in Figure 8.

Although the P89LPC924/925 is a 3 V device most of the pins are 5 V-tolerant. If 5 V is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to VDD causing extra power consumption. Therefore, applying 5 V to pins configured in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit.

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Philips Semiconductors			UM10108
			P89LPC924/925 User manual

(Please refer to the P89LPC924/925 data sheet, Dynamic characteristics for glitch filter specifications).

			VDD
2 CPU	P	P	very	P
CLOCK DELAY	P	P	very	P
CLOCK DELAY		strong	weak	weak
			weak

port

port latch data

input

data

002aaa914

glitch rejection

Fig 8. Quasi-bidirectional output.

The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the quasi-bidirectional mode.

The open drain port configuration is shown in Figure 9.

An open drain port pin has a Schmitt triggered input that also has a glitch suppression circuit.

Please refer to the P89LPC924/925 data sheet, Dynamic characteristics for glitch filter specifications.

port

port latch data

input data

glitch rejection

002aaa915

Fig 9. Open drain output.

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Philips Semiconductors			UM10108
			P89LPC924/925 User manual

The input port configuration is shown in Figure 10. It is a Schmitt triggered input that also has a glitch suppression circuit.

(Please refer to the P89LPC924/925 data sheet, Dynamic characteristics for glitch filter specifications).

input	port
data	pin
	glitch rejection

002aaa916

Fig 10. Input only.

The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output.

The push-pull port configuration is shown in Figure 11.

A push-pull port pin has a Schmitt triggered input that also has a glitch suppression circuit.

(Please refer to the P89LPC924/925 data sheet, Dynamic characteristics for glitch filter specifications).

VDD

strong

port pin

port latch	N
data

input

data

glitch rejection

002aaa917

Fig 11. Push-pull output.

The P89LPC924/925 incorporates two Analog Comparators. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both the digital outputs and digital inputs disabled.

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Philips Semiconductors			UM10108
			P89LPC924/925 User manual

Digital outputs are disabled by putting the port pins into the input-only mode as described in the Port Configurations section (see Figure 10).

Digital inputs on Port 0 may be disabled through the use of the PT0AD register. Bits 1 through 5 in this register correspond to pins P0.1 through P0.5 of Port 0, respectively. Setting the corresponding bit in PT0AD disables that pin’s digital input. Port bits that have their digital inputs disabled will be read as logic 0 by any instruction that accesses the port.

On any reset, PT0AD bits 1 through 5 default to logic 0s to enable the digital functions.

After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.

•After power-up, all I/O pins except P1.5, may be configured by software.

•Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or open drain.

Every output on the P89LPC924/925 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to the P89LPC924/925 data sheet for detailed specifications.

All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

Table 22: Port output configuration

Port pin	Configuration SFR bits
	PxM1.y	PxM2.y	Alternate usage	Notes
P0.0	P0M1.0	P0M2.0	KBIO, CMP2

P0.1	P0M1.1	P0M2.1	KBI1, CIN2B, AD10
P0.2	P0M1.2	P0M2.2	KBI2, CIN2A, AD11

P0.3	P0M1.3	P0M2.3	KBI3, CIN1B, AD12

P0.4	P0M1.4	P0M2.4	KBI4, CIN1A, AD13,
			DAC1

P0.5	P0M1.5	P0M2.5	KBI5, CMPREF

Refer to Section 5.6 “Port 0 analog functions” for usage as analog inputs.

P0.6	P0M1.6	P0M2.6	KBI6, CMP1
P0.7	P0M1.7	P0M2.7	KBI7, T1

P1.0	P1M1.0	P1M2.0	TXD

P1.1	P1M1.1	P1M2.1	RXD

P1.2	P1M1.2	P1M2.2	T0, SCL		Input-only or open-drain

P1.3	P1M1.3	P1M2.3		SDA	input-only or open-drain
P1.3	P1M1.3	P1M2.3	INTO,	SDA	input-only or open-drain

P1.4	P1M1.4	P1M2.4
P1.4	P1M1.4	P1M2.4	INT1

P1.5	P1M1.5	P1M2.5
P1.5	P1M1.5	P1M2.5	RST

P1.6	P1M1.6	P1M2.6

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SDA/INT0/P1.3

SCL/T0/P1.2