Philips P89LPC907, P89LPC906, P89LPC908 User Manual

INTEGRATED CIRCUITS

USER MANUAL

P89LPC906/907/908

8-bit microcontrollers with accelerated two-clock 80C51 core 1KB 3V Low-Power byte-eraseable Flash with 128 Byte RAM

Philips Semiconductors

PHILIPS

2003 Dec 8

Philips Semiconductors

User’s Manual - Preliminary -

Table of Contents

P89LPC906/907/908

1. General Description................................................................................ 7

Pin Configurations ..................................................................................... 7

Product comparison................................................................................... 8

Pin Descriptions - P89LPC906 ................................................................ 12

Pin Descriptions - P89LPC907 ................................................................ 13

Pin Descriptions - P89LPC908 ................................................................ 14

Special function registers ......................................................................... 15

Memory Organization .............................................................................. 24

2. Clocks................................................................................................... 25

Enhanced CPU ........................................................................................ 25

Clock Definitions ...................................................................................... 25

CPU Clock (OSCCLK) ............................................................................. 25

Low Speed Oscillator Option - P89LPC906............................................. 25

Medium Speed Oscillator Option - P89LPC906 ...................................... 25

High Speed Oscillator Option - P89LPC906............................................ 25

Oscillator Option Selection- P89LPC906................................................. 26

Clock Output - P89LPC906 ..................................................................... 26

On-Chip RC oscillator Option .................................................................. 26

If CCLK is 8MH or slower, the CLKLP SFR bit (AUXR1.7) can be set to ’1’ to reduce power consumption. On reset, CLKLP is ’0’ allowing highest performance access. This bit

can then be set in software if CCLK is running at 8MHz or slower ............................... 26

Watchdog Oscillator Option ..................................................................... 26

External Clock Input Option - P89LPC906 .............................................. 27

CPU Clock (CCLK) Wakeup Delay.......................................................... 27

CPU Clock (CCLK) Modification: DIVM Register..................................... 27

Low Power Select (P89LPC906) ........................................................... 28

................................................................................................................. 29

3. Interrupts .............................................................................................. 31

Interrupt Priority Structure........................................................................ 31

External Interrupt Inputs .......................................................................... 32

External Interrupt Pin Glitch Suppression................................................ 32

4. I/O Ports ............................................................................................... 35

Port Configurations.................................................................................. 35

Quasi-Bidirectional Output Configuration ................................................ 35

Open Drain Output Configuration ............................................................ 36

Input-Only Configuration.......................................................................... 37

Push-Pull Output Configuration ............................................................... 37

Port 0 Analog Functions .......................................................................... 37

5. Timers 0 and 1...................................................................................... 41

Mode 0..................................................................................................... 42

Mode 2..................................................................................................... 42

Mode 3..................................................................................................... 43

Mode 6 - P89LPC907 .............................................................................. 43

Timer Overflow toggle output - P89LPC907............................................ 45

2003 Dec 8 2

Philips Semiconductors

User’s Manual - Preliminary -

Table of Contents

P89LPC906/907/908

6. Real-Time Clock/System Timer............................................................ 47

Real-time Clock Source........................................................................... 47

Changing RTCS1-0 ................................................................................. 50

Real-time Clock Interrupt/Wake Up ......................................................... 50

Reset Sources Affecting the Real-time Clock.......................................... 50

7. Power Monitoring Functions ................................................................. 53

Brownout Detection ................................................................................. 53

Power-On Detection ................................................................................ 54

Power Reduction Modes.......................................................................... 54

8. UART (P89LPC907, P89LPC908)........................................................ 59

Mode 0..................................................................................................... 59

Mode 1..................................................................................................... 59

Mode 2..................................................................................................... 59

Mode 3..................................................................................................... 59

SFR Space .............................................................................................. 60

Baud Rate Generator and Selection........................................................ 60

Updating the BRGR1 and BRGR0 SFRs................................................. 60

Framing Error........................................................................................... 61

Break Detect............................................................................................ 61

More About UART Mode 0 ...................................................................... 63

More About UART Mode 1 ...................................................................... 64

More About UART Modes 2 and 3........................................................... 65

Framing Error and RI in Modes 2 and 3 with SM2 = 1 ............................ 65

Break Detect............................................................................................ 65

Double Buffering...................................................................................... 66

Double Buffering in Different Modes........................................................ 66

Transmit Interrupts with Double Buffering Enabled (Modes 1, 2 and 3) .. 66

The 9th Bit (Bit 8) in Double Buffering (Modes 1, 2 and 3)...................... 67

Multiprocessor Communications.............................................................. 68

Automatic Address Recognition............................................................... 68

9. Reset .................................................................................................... 71

Power-On reset code execution .............................................................. 71

10. Analog Comparators........................................................................... 73

Comparator Configuration ....................................................................... 73

Internal Reference Voltage ...................................................................... 74

Comparator Interrupt ............................................................................... 74

Comparator and Power Reduction Modes............................................... 74

Comparator Configuration Example ........................................................ 75

11. Keypad Interrupt (KBI)........................................................................ 77

12. Watchdog Timer ................................................................................. 79

Watchdog Function.................................................................................. 79

Feed Sequence ....................................................................................... 80

Watchdog Timer in Timer Mode .............................................................. 83

2003 Dec 8 3

Philips Semiconductors

User’s Manual - Preliminary -

Table of Contents

P89LPC906/907/908

Power down operation ............................................................................. 84

Watchdog Clock Source .......................................................................... 84

Periodic wakeup from Power down without an external oscillator ........... 85

13. Additional Features............................................................................. 87

Software Reset ........................................................................................ 87

Dual Data Pointers................................................................................... 87

14. Flash program memory ...................................................................... 89

General description.................................................................................. 89

Features................................................................................................... 89

Introduction to IAP-Lite ............................................................................ 89

Using Flash as data storage .................................................................... 89

Accessing additional flash elements........................................................ 92

Erase-programming additional flash elements ........................................ 93

Reading additional flash elements........................................................... 93

User Configuration Bytes......................................................................... 96

User Security Bytes ................................................................................. 97

Boot Vector.............................................................................................. 98

Boot Status .............................................................................................. 98

15. Instruction set ..................................................................................... 99

16. Revision History................................................................................ 103

17. Index................................................................................................. 105

2003 Dec 8 4

Philips Semiconductors

User’s Manual - Preliminary -

List of Figures

P89LPC906/907/908

List of Figures

Special function registers table - P89LPC906. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Special function registers table - P89LPC907. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Special function registers table - P89LPC908. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

P89LPC906/907/908 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Using the Crystal Oscillator - P89LPC906 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

On-Chip RC Oscillator TRIM Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Block Diagram of Oscillator Control - P89LPC906 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Block Diagram of Oscillator Control- P89LPC907,P89LPC908 . . . . . . . . . . . . . . . . . . . . 29

Interrupt priority level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Summary of Interrupts - P89LPC906 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Summary of Interrupts - P89LPC907,P89LPC908 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Interrupt sources, enables, and Power down Wake-up sources - P89LPC906 . . . . . . . . 33

Interrupts sources, enables, and Power down Wake-up sources - P89LPC907,P89LPC908 33

Number of I/O Pins Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Port Output Configuration Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Quasi-Bidirectional Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Open Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Input Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Push-Pull Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Port Output Configuration - P89LPC906 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Port Output Configuration - P89LPC907 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Port Output Configuration - P89LPC908. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Additional Port Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Timer/Counter Mode Control register (TMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Timer/Counter Auxiliary Mode Control register (TAMOD). . . . . . . . . . . . . . . . . . . . . . . . . 42

Timer/Counter Control register (TCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Timer/Counter 0 or 1 in Mode 0 (13-bit counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Timer/Counter 0 or 1 in Mode 1 (16-bit counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Timer/Counter 0 or 1 in Mode 2 (8-bit auto-reload). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Timer/Counter 0 Mode 3 (two 8-bit counters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Timer/Counter 0 in Mode 6 (PWM auto-reload), P89LPC907. . . . . . . . . . . . . . . . . . . . . . 45

Real-time clock/system timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Real-time Clock/System Timer Clock Source - P89LPC906. . . . . . . . . . . . . . . . . . . . . . . 48

Real-time Clock/System Timer Clock Source - P89LPC907,P89LPC908 . . . . . . . . . . . . 49

RTCCON Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Brownout Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Power Reduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Power Control Register (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Power Control Register (PCONA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

SFR Locations for UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Baud Rate Generation for UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

BRGCON Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Baud Rate Generations for UART (Modes 1, 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

2003 Dec 8 5

Philips Semiconductors

User’s Manual - Preliminary -

List of Figures

P89LPC906/907/908

Serial Port Control Register (SCON). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Serial Port Status Register (SSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Serial Port Mode 0 (Double Buffering Must Be Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 64

Serial Port Mode 1 (Only Single Transmit Buffering Case Is Shown) . . . . . . . . . . . . . . . . 64

Serial Port Mode 2 or 3 (Only Single Transmit Buffering Case Is Shown) . . . . . . . . . . . . 65

FE and RI when SM2 = 1 in Modes 2 and 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Transmission with and without Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Block Diagram of Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Reset Sources Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Comparator Control Register (CMP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Comparator Input and Output Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Comparator Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Keypad Pattern Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Keypad Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Keypad Interrupt Mask Register (KBM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

.Watchdog timer configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Watchdog Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

P89LPC906/907/908 Watchdog Timeout Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Watchdog Timer in Watchdog Mode (WDTE = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Watchdog Timer in Timer Mode (WDTE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

AUXR1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Flash Memory Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Assembly language routine to erase/program all or part of a page. . . . . . . . . . . . . . . . . . 92

C-language routine to erase/program all or part of a page . . . . . . . . . . . . . . . . . . . . . . . . 92

Flash elements accesable through IAP-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Assembly language routine to erase/program a flash element . . . . . . . . . . . . . . . . . . . . . 94

C-language routine to erase/program a flash element . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

C-language routine to read a flash element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Flash User Configuration Byte 1 (UCFG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

User Sector Security Bytes (SEC0 ... SEC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Effects of Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Boot Vector (BOOTVEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Boot Status (BOOTSTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

2003 Dec 8 6

Philips Semiconductors

User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

1. GENERAL DESCRIPTION

The P89LPC906/907/908 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC906/907/908 is based on a high performance processor architecture that executes instructions six times the rate of standard 80C51 devices. Many system level functions have been incorporated into the P89LPC906/907/908 in order to reduce component count, board space, and system cost.

PIN CONFIGURATIONS

8-Pin Packages

P89LPC906

RST

/P1.5

VSS

P0.6/CMP1/KBI6

XTAL1/P3.1

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

VDD

CLKOUT/XTAL2/P3.0

RST/P1.5

VSS

P0.6/CMP1/KBI6

P1.2/T0

/P1.5

RST

VSS

P0.6/CMP1/KBI6

P1.1/RxD

P89LPC907

P89LPC908

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

VDD

P1.0/TxD

P0.4/CIN1A/KBI4

P0.5/CMPREF/KBI5

VDD

P1.0/TXD

2003 Dec 8 7

Philips Semiconductors

Logic Symbols

VDDV

User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

KBI4 KBI5

CLKOUT

KBI4 KBI5 KBI6

CIN1A

CMPREF

CMP1KBI6

PORT0

XTAL2

XTAL1

CIN1A

CMPREF

CMP1

CIN1A

CMPREF

CMP1 RxD

PORT3

PORT0

P89

LPC906

VDDV

P89

LPC907

VDDV

P89

LPC908

PORT1

RST

T0 TxD

RST

TxD

PRODUCT COMPARISON

The following table highlights differences between these three devices.

Part number Ext crystal pins CLKOUT output T0 PWM output

P89LPC906 XX-X--

P89LPC907 --XXX-

P89LPC908 ---XXX

2003 Dec 8 8

Analog

comparator

UART

TxD RxD

Philips Semiconductors

Block Diagram - P89LPC906

Accelerated 2-clock 80C51

1 KB Code

Flash

128 byte

Data RAM

Port 3

Configurable I/Os

Port 1

Input

High Performance

CPU

Internal Bus

Real-Time Clock/

User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

Timer0 Timer1

System Timer

Crystal or

Resonator

Port 0

Configurable I/Os

Keypad

Interrupt

Watchdog Timer

and Oscillator

Programmable

Oscillator Divider

Configurable

Oscillator

CPU

Clock

On-Chip

Oscillator

Analog

Comparator

Power Monitor

(Power-On Reset,

Brownout Reset)

2003 Dec 8 9

Philips Semiconductors

Block Diagram - P89LPC907

User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

High Performance

Accelerated 2-clock 80C51

CPU

1 KB Code

Flash

Internal Bus

UART

128 byte

Data RAM

Timer0 Timer1

Port 1

Configurable I/O

Port 0

Configurable I/Os

Keypad

Interrupt

Watchdog Timer

and Oscillator

Programmable

Oscillator Divider

On-Chip

Oscillator

Real-Time Clock/

System Timer

Analog

Comparator

CPU

Clock

Power Monitor

(Power-On Reset,

Brownout Reset)

2003 Dec 8 10

Philips Semiconductors

Block Diagram - P89LPC908

User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

High Performance

Accelerated 2-clock 80C51

CPU

1 KB Code

Flash

128 byte

Data RAM

Port 1

Configurable I/Os

Port 0

Configurable I/Os

Keypad

Interrupt

Watchdog Timer

and Oscillator

Programmable

Oscillator Divider

UART

Internal Bus

Timer0 Timer1

Real-Time Clock/

System Timer

Analog

Comparator

CPU

Clock

On-Chip

Oscillator

2003 Dec 8 11

Power Monitor

(Power-On Reset,

Brownout Reset)

Philips Semiconductors

User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

PIN DESCRIPTIONS - P89LPC906

Mnemonic Pin no. Type Name and function

P0.4 - P0.6 3, 7,8 I/O Port 0: Port 0 is an I/O port with a user-configurable output types. During reset Port

0 latches are configured in the input only mode with the internal pullup disabled. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section Port Configurations on page 35 and the DC Electrical Characteristics in the datasheet for details.

The Keypad Interrupt feature operates with port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below.

8I/OP0.4 Port 0 bit 4.

I CIN1A Comparator 1 positive input. I KBI4 Keyboard Input 4.

7I/OP0.5 Port 0 bit 5.

I CMPREFComparator reference (negative) input. I KBI5 Keyboard Input 5.

3I/OP0.6 Port 0 bit 6.

O CMP1 Comparator 1 output.

I KBI6 Keyboard Input 6.

P1.5 1 I P1.5 Port 1 bit 5. (Input only)

I RST

P3.0 - P3.1 4,5 I/O Port 3 Port 3 is an I/O port with a user-configurable output types. During reset Port

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

5I/OP3.0 Port 3 bit 0.

O XTAL2 Output from the oscillator amplifier (when a crystal oscillator option is

OCLKOUTCPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can

4I/OP3.1 Port 3 bit 1.

I XTAL1 Input to the oscillator circuit and internal clock generator circuits (when

2IGround: 0V reference.

6IPower Supply: This is the power supply voltage for normal operation as well as Idle and

Power down modes.

External Reset input during power-on or if selected via UCFG1. When functioning as a reset input a low on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-Circuit Programming mode.

3 latches are configured in the input only mode with the internal pullups disabled. The operation of port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to the section Port Configurations on page 35 and the DC Electrical Characteristics in the datasheet for details.

selected via the FLASH configuration).

be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the Real-Time clock/system timer.

selected via the FLASH configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, AND if XTAL1/XTAL2 are not used to generate the clock for the Real-Time clock/ system timer.

2003 Dec 8 12

Philips Semiconductors

User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

PIN DESCRIPTIONS - P89LPC907

Mnemonic Pin no. Type Name and function

P0.4 - P0.6 3, 7,8 I/O Port 0: Port 0 is an I/O port with a user-configurable output types. During reset Port

The Keypad Interrupt feature operates with port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below.

8 I/O P0.4 Port 0 bit 4.

I CIN1A Comparator 1 positive input. I KBI4 Keyboard Input 4.

7 I/O P0.5 Port 0 bit 5.

I CMPREFComparator reference (negative) input. I KBI5 Keyboard Input 5.

3 I/O P0.6 Port 0 bit 6.

O CMP1 Comparator 1 output.

I KBI6 Keyboard Input 6.

P1.0-P1.5 1,4,5 Port 1: Port 1 is an I/O port with a user-configurable output types. During reset Port

1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to the section Port Configurations on page 35 and the DC Electrical Characteristics in the datasheet for details.

P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below.

5 I/O P1.0 Port 1 bit 0.

O TxD Serial port transmitter data.

4 I/O P1.2 Port 1 bit 2.

I/O T0 Timer 0 external clock input, toggle output, PWM output.

1IP1.5 Port 1 bit 5. (Input only)

I RST

2IGround: 0V reference.

6IPower Supply: This is the power supply voltage for normal operation as well as Idle

and Power down modes.

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User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

PIN DESCRIPTIONS - P89LPC908

Mnemonic Pin no. Type Name and function

P0.4 - P0.6 3, 7,8 I/O Port 0: Port 0 is an I/O port with a user-configurable output types. During reset Port

The Keypad Interrupt feature operates with port 0 pins.

All pins have Schmitt triggered inputs.

Port 0 also provides various special functions as described below.

8 I/O P0.4 Port 0 bit 4.

I CIN1A Comparator 1 positive input. I KBI4 Keyboard Input 4.

7 I/O P0.5 Port 0 bit 5.

I CMPREFComparator reference (negative) input. I KBI5 Keyboard Input 5.

3 I/O P0.6 Port 0 bit 6.

O CMP1 Comparator 1 output.

I KBI6 Keyboard Input 6.

P1.0 - P1.5 1,4,5 Port 1: Port 1 is an I/O port with a user-configurable output types. During reset Port

P1.5 is input only.

All pins have Schmitt triggered inputs.

Port 1 also provides various special functions as described below.

5 I/O P1.0 Port 1 bit 0.

O TxD Serial port transmitter data.

4 I/O P1.1 Port 1 bit 1.

I RxD Serial port receiver data.

1IP1.5 Port 1 bit 5. (Input only)

I RST

2IGround: 0V reference.

6IPower Supply: This is the power supply voltage for normal operation as well as Idle

and Power down modes.

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P89LPC906/907/908GENERAL DESCRIPTION

Special function registers

Note: Special function registers (SFRs) accesses are restricted in the following ways:

1. User must NOT attempt to access any SFR locations not defined.

2. Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

3. SFR bits labeled ’-’, ’0’ or ’1’ can ONLY be written and read as follows:

- ’-’ Unless otherwise specified, MUST be written with ’0’, but can return any value when read (even if it was written with ’0’). It is a reserved bit and may be used in future derivatives.

- ’0’ MUST be written with ’0’, and will return a ’0’ when read.

- ’1’ MUST be written with ’1’, and will return a ’1’ when read.

Table 1: Special function registers table - P89LPC906

Name Description

ACC* Accumulator E0H 00H 00000000

AUXR1# Auxiliary Function Register A2H CLKLP - - ENT0 SRST 0 - DPS 00H

SFR

Address

MSB

E7 E6 E5 E4 E3 E2 E1 E0

Bit Functions and Addresses Reset Value

LSB

Hex Binary

000000x0

F7 F6 F5 F4 F3 F2 F1 F0

B* B Register F0H 00H 00000000

CMP1# Comparator 1Control Register ACH - - CE1 - CN1 OE1 CO1 CMF1 00H

DIVM# CPU Clock Divide-by-M Control 95H 00H 00000000

DPTR Data Pointer (2 bytes)

DPH Data Pointer High 83H 00H 00000000

DPL Data Pointer Low 82H 00H 00000000

FMADRH# Program Flash Address High E7H 00H 00000000

FMADRL# Program Flash Address Low E6H 00H 00000000

Program Flash Control (Read)

FMCON#

FMDATA# Program Flash Data E5H 00H 00000000

IEN0* Interrupt Enable 0 A8H EA EWDRT EBO - ET1 - ET0 - 00H 00000000

IEN1*# Interrupt Enable 1 E8H - - - - - EC EKBI - 00H

IP0* Interrupt Priority 0 B8H - PWDRT PBO - PT1 - PT0 - 00H

Program Flash Control (Write)

BUSY - - - HVA HVE SV OI 70H 01110000

E4H

FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

EF EE ED EC EB EA E9 E8

BF BE BD BC BB BA B9 B8

xx000000

00x00000

x0000000

IP0H# Interrupt Priority 0 High B7H -

IP1*# Interrupt Priority 1 F8H - - - - - PC PKBI - 00H

2003 Dec 8 15

PWDRT

FF FE FD FC FB FA F9 F8

PBOH - PT1H - PT0H - 00H

x0000000

00x00000

Philips Semiconductors

User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

Name Description

SFR

Address

MSB

Bit Functions and Addresses Reset Value

LSB

Hex Binary

IP1H# Interrupt Priority 1 High F7H - - - - - PCH PKBIH - 00H100x00000

KBCON# Keypad Control Register 94H - - - - - -

PATN_S

KBIF 00H

xxxxxx00

KBMASK# Keypad Interrupt Mask Register 86H 00H 00000000

KBPATN# Keypad Pattern Register 93H FFH 11111111

87 86 85 84 83 82 81 80

P0* Port 0 80H -

KB6

CMPREF/

KB5

CIN/1A

KB4

---- Note 1

CMP1/

97 96 95 94 93 92 91 90

P1* Port 1 90H - - RST

-----

B7 B6 B5 B4 B3 B2 B1 B0

P3*Port 3 B0H------XTAL1XTAL2Note 1

P0M1# Port 0 Output Mode 1 84H - (P0M1.6) (P0M1.5) (P0M1.4) - - - - FFH 11111111

P0M2# Port 0 Output Mode 2 85H - (P0M2.6) (P0M2.5) (P0M2.4) - - - - 00H 00000000

P1M1# Port 1 Output Mode 1 91H - - (P1M1.5) - - - - - FFH

P1M2# Port 1 Output Mode 2 92H - - (P1M2.5) - - - - - 00H

P3M1# Port 3 Output Mode 1 B1H - - - - - - (P3M1.1) (P3M1.0) 03H

P3M2# Port 3 Output Mode 2 B2H - - - - - - (P3M2.1) (P3M2.0) 00H

11111111

00000000

xxxxxx11

xxxxxx00

PCON# Power Control Register 87H - - BOPD BOI GF1 GF0 PMOD1 PMOD0 00H 00000000

PCONA# Power Control Register A B5H RTCPD - VCPD - - - - -

00H

00000000

D7 D6 D5 D4 D3 D2 D1 D0

PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV F1 P 00H 00000000

PT0AD# Port 0 Digital Input Disable F6H - - PT0AD.5 PT0AD.4 - - - - 00H xx00000x

RSTSRC# Reset Source Register DFH - - BOF POF - R_WD R_SF R_EX Note 2

1,5

RTCCON# Real-Time Clock Control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60H

RTCH# Real-Time Clock Register High D2H 00H

RTCL# Real-Time Clock Register Low D3H 00H

011xxx00

00000000

SP Stack Pointer 81H 07H 00000111

TAMOD# Timer 0 Auxiliary Mode 8FH - - - - - - - T0M2 00H xxx0xxx0

8F 8E 8D 8C 8B 8A 89 88

TCON* Timer 0 and 1 Control 88H TF1 TR1 TF0 TR0 - - - - 00H 00000000

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P89LPC906/907/908GENERAL DESCRIPTION

Name Description

TH0 Timer 0 High 8CH 00H 00000000

TH1 Timer 1 High 8DH 00H 00000000

TL0 Timer 0 Low 8AH 00H 00000000

TL1 Timer 1 Low 8BH 00H 00000000

TMOD Timer 0 and 1 Mode 89H - - T1M1 T1M0 - - T0M1 T0M0 00H 00000000

TRIM# Internal Oscillator Trim Register 96H - ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 Notes 4,5

WDCON# Watchdog Control Register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK Notes 3,5

WDL# Watchdog Load C1H FFH 11111111

WFEED1# Watchdog Feed 1 C2H

WFEED2# Watchdog Feed 2 C3H

SFR

Address

MSB

Bit Functions and Addresses Reset Value

LSB

Hex Binary

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User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

Table 2: Special function registers table - P89LPC907

Name Description

SFR

Address

MSB

E7 E6 E5 E4 E3 E2 E1 E0

ACC* Accumulator E0H 00H 00000000

Bit Functions and Addresses Reset Value

LSB

Hex Binary

AUXR1# Auxiliary Function Register A2H ----SRST0-DPS00H

000000x0

F7 F6 F5 F4 F3 F2 F1 F0

B* B Register F0H 00H 00000000

BRGR0#§ Baud Rate Generator Rate Low BEH 00H 00000000

BRGR1#§ Baud Rate Generator Rate High BFH 00H 00000000

BRGCON#Baud Rate Generator Control BDH------SBRGSBRGEN00Hxxxxxx00

CMP1# Comparator 1 Control Register ACH - - CE1 - CN1 OE1 CO1 CMF1 00H

xx000000

DIVM# CPU Clock Divide-by-M Control 95H 00H 00000000

DPTR Data Pointer (2 bytes)

DPH Data Pointer High 83H 00H 00000000

DPL Data Pointer Low 82H 00H 00000000

FMADRH# Program Flash Address High E7H 00H 00000000

FMADRL# Program Flash Address Low E6H 00H 00000000

FMCON#

Program Flash Control (Read)

Program Flash Control (Write)

E4H

BUSY - - - HVA HVE SV OI 70H 01110000

FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

FMDATA# Program Flash Data E5H 00H 00000000

IEN0* Interrupt Enable 0 A8H EA EWDRT EBO ES ET1 - ET0 - 00H 00000000

EF EE ED EC EB EA E9 E8

IEN1*# Interrupt Enable 1 E8H - EST - - - EC EKBI - 00H

BF BE BD BC BB BA B9 B8

IP0* Interrupt Priority 0 B8H - PWDRT PBO PS PT1 - PT0 - 00H

IP0H# Interrupt Priority 0 High B7H -

PWDRT

PBOH PSH PT1H - PT0H - 00H

FF FE FD FC FB FA F9 F8

IP1*# Interrupt Priority 1 F8H - PST - - - PC PKBI - 00H

IP1H# Interrupt Priority 1 High F7H - PSTH - - - PCH PKBIH - 00H

KBCON#Keypad Control Register 94H------

PATN_S

KBIF 00H

2003 Dec 8 18

00x00000

x0000000

00x00000

xxxxxx00

Philips Semiconductors

User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

Name Description

SFR

Address

MSB

Bit Functions and Addresses Reset Value

LSB

Hex Binary

KBMASK# Keypad Interrupt Mask Register 86H 00H 00000000

KBPATN# Keypad Pattern Register 93H FFH 11111111

87 86 85 84 83 82 81 80

P0* Port 0 80H -

KB6

CMPREF/

KB5

CIN1A/

KB4

-KB2-KB0 Note 1

CMP1/

97 96 95 94 93 92 91 90

P1* Port 1 90H - - RST

--T0-TxD

B7 B6 B5 B4 B3 B2 B1 B0

P0M1# Port 0 Output Mode 1 84H - (P0M1.6) (P0M1.5) (P0M1.4) - (P0M1.2) - (P0M1.0) FFH 11111111

P0M2# Port 0 Output Mode 2 85H - (P0M2.6) (P0M2.5) (P0M2.4) - (P0M2.2) - (P0M2.0) 00H 00000000

P1M1# Port 1 Output Mode 1 91H - - (P1M1.5) - - (P1M1.2) - (P1M1.0) FFH

P1M2# Port 1 Output Mode 2 92H - - (P1M2.5) - - (P1M2.2) - (P1M2.0) 00H

11111111

00000000

PCON# Power Control Register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00H 00000000

PCONA# Power Control Register A B5H RTCPD VCPD - SPD

00H

00000000

D7 D6 D5 D4 D3 D2 D1 D0

PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV F1 P 00H 00000000

PT0AD#Port 0 Digital Input Disable F6H--PT0AD.5PT0AD.4----00Hxx00000x

RSTSRC# Reset Source Register DFH - - BOF POF - R_WD R_SF R_EX Note 2

1,5

RTCCON# Real-Time Clock Control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60H

RTCH# Real-Time Clock Register High D2H 00H

RTCL# Real-Time Clock Register Low D3H 00H

011xxx00

00000000

SBUF Serial Port Data Buffer Register 99H xxH xxxxxxxx

9F 9E 9D 9C 9B 9A 99 98

SCON* Serial Port Control 98H SM0 SM1 SM2 - TB8 - TI - 00H 00000000

SSTAT# Serial Port Extended Status Register BAH DBMOD INTLO CIDIS DBISEL ----00H00000000

SP Stack Pointer 81H 07H 00000111

TAMOD# Timer 0 Auxiliary Mode 8FH -------T0M200Hxxx0xxx0

8F 8E 8D 8C 8B 8A 89 88

TCON*Timer 0 and 1 Control 88HTF1TR1TF0TR0----00H00000000

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User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

Name Description

TH0 Timer 0 High 8CH 00H 00000000

TH1 Timer 1 High 8DH 00H 00000000

TL0 Timer 0 Low 8AH 00H 00000000

TL1 Timer 1 Low 8BH 00H 00000000

TMOD Timer 0 and 1 Mode 89H - - T1M1 T1M0 - - T0M1 T0M0 00H 00000000

TRIM# Internal Oscillator Trim Register 96H - - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 Notes 4,5

WDCON# Watchdog Control Register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK Notes 3,5

WDL# Watchdog Load C1H FFH 11111111

WFEED1# Watchdog Feed 1 C2H

WFEED2# Watchdog Feed 2 C3H

SFR

Address

MSB

Bit Functions and Addresses Reset Value

LSB

Hex Binary

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User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

Table 3: Special function registers table - P89LPC908

Name Description

SFR

Address

MSB

E7 E6 E5 E4 E3 E2 E1 E0

ACC* Accumulator E0H 00H 00000000

Bit Functions and Addresses Reset Value

LSB

Hex Binary

AUXR1# Auxiliary Function Register A2H - EBRR - - SRST 0 - DPS 00H

000000x0

F7 F6 F5 F4 F3 F2 F1 F0

B* B Register F0H 00H 00000000

BRGR0#§ Baud Rate Generator Rate Low BEH 00H 00000000

BRGR1#§ Baud Rate Generator Rate High BFH 00H 00000000

BRGCON#Baud Rate Generator Control BDH------SBRGSBRGEN00Hxxxxxx00

CMP1# Comparator 1 Control Register ACH - - CE1 - CN1 OE1 CO1 CMF1 00H

xx000000

DIVM# CPU Clock Divide-by-M Control 95H 00H 00000000

DPTR Data Pointer (2 bytes)

DPH Data Pointer High 83H 00H 00000000

DPL Data Pointer Low 82H 00H 00000000

FMADRH# Program Flash Address High E7H 00H 00000000

FMADRL# Program Flash Address Low E6H 00H 00000000

FMCON#

Program Flash Control (Read)

Program Flash Control (Write)

E4H

BUSY - - - HVA HVE SV OI 70H 01110000

FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

FMDATA# Program Flash Data E5H 00H 00000000

IEN0* Interrupt Enable 0 A8H EA EWDRT EBO ES/ESR ET1 - ET0 - 00H 00000000

EF EE ED EC EB EA E9 E8

IEN1*# Interrupt Enable 1 E8H - EST - - - EC EKBI - 00H

BF BE BD BC BB BA B9 B8

IP0* Interrupt Priority 0 B8H - PWDRT PBO PS/PSR PT1 - PT0 - 00H

IP0H# Interrupt Priority 0 High B7H -

PWDRT

PBOH

PSH/

PSRH

PT1H - PT0H - 00H

FF FE FD FC FB FA F9 F8

IP1*# Interrupt Priority 1 F8H - PST - - - PC PKBI - 00H

IP1H# Interrupt Priority 1 High F7H - PSTH - - - PCH PKBIH - 00H

KBCON#Keypad Control Register 94H------

PATN_S

KBIF 00H

2003 Dec 8 21

00x00000

x0000000

00x00000

xxxxxx00

Philips Semiconductors

User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

Name Description

SFR

Address

MSB

Bit Functions and Addresses Reset Value

LSB

Hex Binary

KBMASK# Keypad Interrupt Mask Register 86H 00H 00000000

KBPATN# Keypad Pattern Register 93H FFH 11111111

87 86 85 84 83 82 81 80

P0* Port 0 80H -

KB6

CMPREF/

KB5

CIN1A/

KB4

-KB2- - Note 1

CMP1/

97 96 95 94 93 92 91 90

P1* Port 1 90H - - RST

---RxDTxD

P0M1# Port 0 Output Mode 1 84H - (P0M1.6) (P0M1.5) (P0M1.4) - (P0M1.2) - - FFH 11111111

P0M2# Port 0 Output Mode 2 85H - (P0M2.6) (P0M2.5) (P0M2.4) - (P0M2.2) - - 00H 00000000

P1M1# Port 1 Output Mode 1 91H - - (P1M1.5) - - - (P1M1.1) (P1M1.0) FFH

P1M2# Port 1 Output Mode 2 92H - - (P1M2.5) - - - (P1M2.1) (P1M2.0) 00H

11111111

00000000

PCON# Power Control Register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00H 00000000

PCONA# Power Control Register A B5H RTCPD VCPD - SPD

00H

00000000

D7 D6 D5 D4 D3 D2 D1 D0

PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV F1 P 00H 00000000

PT0AD# Port 0 Digital Input Disable F6H - - PT0AD.5 PT0AD.4 - PT0AD.2 - - 00H xx00000x

RSTSRC# Reset Source Register DFH - - BOF POF R_BK R_WD R_SF R_EX Note 2

1,5

RTCCON# Real-Time Clock Control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60H

RTCH# Real-Time Clock Register High D2H 00H

RTCL# Real-Time Clock Register Low D3H 00H

011xxx00

00000000

SADDR# Serial Port Address Register A9H 00H 00000000

SADEN# Serial Port Address Enable B9H 00H 00000000

SBUF Serial Port Data Buffer Register 99H xxH xxxxxxxx

9F 9E 9D 9C 9B 9A 99 98

SCON* Serial Port Control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00H 00000000

SSTAT# Serial Port Extended Status Register BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00H 00000000

SP Stack Pointer 81H 07H 00000111

8F 8E 8D 8C 8B 8A 89 88

TCON*Timer 0 and 1 Control 88HTF1TR1TF0TR0----00H00000000

TH0 Timer 0 High 8CH 00H 00000000

TH1 Timer 1 High 8DH 00H 00000000

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P89LPC906/907/908GENERAL DESCRIPTION

Name Description

TL0 Timer 0 Low 8AH 00H 00000000

TL1 Timer 1 Low 8BH 00H 00000000

TMOD Timer 0 and 1 Mode 89H - - T1M1 T1M0 - - T0M1 T0M0 00H 00000000

TRIM# Internal Oscillator Trim Register 96H - - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 Notes 4,5

WDCON# Watchdog Control Register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK Notes 3,5

WDL# Watchdog Load C1H FFH 11111111

WFEED1# Watchdog Feed 1 C2H

WFEED2# Watchdog Feed 2 C3H

SFR

Address

MSB

Bit Functions and Addresses Reset Value

LSB

Hex Binary

Notes:

* SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs.

- Reserved bits, must be written with 0’s.

§ BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ’0’. If any of them is written if BRGEN = 1, result is unpredictable.

Unimplemented bits in SFRs (labeled ’-’ ) are X (unknown) at all times. Unless otherwise specified, ones should not be written to

these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are ’0’s although they are unknown when read.

1. All ports are in input only (high impendance) state after power-up.

2. The RSTSRC register reflects the cause of theP89LPC906/907/908 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF - the power-on reset value is xx110000.

3. After reset, the value is 111001x1, i.e., PRE2-PRE0 are all 1, WDRUN=1 and WDCLK=1. WDTOF bit is 1 after watchdog reset and is 0 after power-on reset. Other resets will not affect WDTOF.

4. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

5. The only reset source that affects these SFRs is power-on reset.

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Philips Semiconductors

MEMORY ORGANIZATION

The P89LPC906/907/908 memory map is shown in Figure 1-1.

03FFh

Sector 3

0300h 02FFh

Sector 2

0200h 01FFh

Sector 1

0100h

00FFh

Sector 0

0000h

1 KB Flash Code

Memory Space

Special Function

Registers

(directly addressable)

DATA

128 Bytes On-Chip

Data Memory (stack,

direct and indir. addr.)

4 Reg. Banks R0-R7

Data Memory

(DATA, IDATA)

User’s Manual - Preliminary -

P89LPC906/907/908GENERAL DESCRIPTION

FFh

80h 7Fh

00h

Figure 1-1: P89LPC906/907/908 Memory Map

The various P89LPC906/907/908 memory spaces are as follows:

DATA 128 bytes of internal data memory space (00h..7Fh) accessed via direct or indirect addressing, using instructions

other than MOVX and MOVC.

SFR Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via

direct addressing.

CODE 1KB of Code memory accessed as part of program execution and via the MOVC instruction.

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User’s Manual - Preliminary -

CLOCKS

P89LPC906/907/908

2. CLOCKS

ENHANCED CPU

The P89LPC906/907/908 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

CLOCK DEFINITIONS

The P89LPC906/907/908 device has several internal clocks as defined below:

• OSCCLK - Input to the DIVM clock divider. OSCCLK is selected from one of the clock sources (see Figure 2-3,Figure 2-4,) and

can also be optionally divided to a slower frequency (see section "CPU Clock (CCLK) Modification: DIVM Register"). Note: f

is defined as the OSCCLK frequency.

OSC

• XCLK - Output of the crystal oscillator (P89LPC906)

• CCLK - CPU clock .

• PCLK - Clock for the various peripheral devices and is CCLK/2

CPU CLOCK (OSCCLK)

The P89LPC906 provides several user-selectable oscillator options. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.

The P89LPC907 and P89LPC908 devices allow the user to select between an on-chip watchdog oscillator and an on-chip RC oscillator as the CPU clock source.

LOW SPEED OSCILLATOR OPTION - P89LPC906

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.

MEDIUM SPEED OSCILLATOR OPTION - P89LPC906

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.

HIGH SPEED OSCILLATOR OPTION - P89LPC906

This option supports an external crystal in the range of 4MHz to 12 MHz. Ceramic resonators are also supported in this configuration. If CCLK is 8MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ’1’ to reduce power consumption. On reset, CLKLP is ’0’ allowing highest performance access. This bit can then be set in software if CCLK is running at 8MHz or slower.

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User’s Manual - Preliminary -

CLOCKS

Quartz crystal or

ceramic resonator

The oscillator must be configured in one of the following modes:

- Low Frequency Crystal

- Medium Frequency Crystal

- High Frequency Crystal

* A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals.

Figure 2-1: Using the Crystal Oscillator - P89LPC906

P89LPC906/907/908

P89LPC906

XTAL1

XTAL2

OSCILLATOR OPTION SELECTION- P89LPC906

The oscillator option is selectable either by the FOSC2:0 bits in UCFG1 or by the RTCS1:0 bits in RTCCON. If the FOSC2:0 bits select an OSCCLK source of either the internal RC oscillator or the WDT oscillator, then the RTCS1:0 bits will select the oscillator option for the crystal oscillator. Otherwise, the crystal oscillator option is selected by FOSC2:0. See Table 6-1 and Table 6-2.

CLOCK OUTPUT - P89LPC906

The P89LPC906 supports a user selectable clock output function on the XTAL2 / CLKOUT pin when no crystal oscillator is being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-Time clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC906. This output is enabled by the ENCLK bit in the TRIM register

The frequency of this clock output is 1/2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of bits 5:0 of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the "ANL direct" or "ORL direct" instructions can be used to clear or set bit 6 of the TRIM register.Increasing the TRIM value will decrease the oscillator frequency.

ON-CHIP RC OSCILLATOR OPTION

The P89LPC906/907/908 has a 6-bit field within the TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±1%. (Note: the initial value is better than 1%; please refer to the datasheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency.

If CCLK is 8MH or slower, the CLKLP SFR bit (AUXR1.7) can be set to ’1’ to reduce power consumption. On reset, CLKLP is ’0’ allowing highest performance access. This bit can then be set in software if CCLK is running at 8MHz or slower

WATCHDOG OSCILLATOR OPTION

The watchdog has a separate oscillator which has a nominal frequency of 400KHz. This oscillator can be used to save power when a high clock frequency is not needed.

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User’s Manual - Preliminary -

CLOCKS

P89LPC906/907/908

EXTERNAL CLOCK INPUT OPTION - P89LPC906

In this configuration, the processor clock is derived from an external source driving the XTAL1 / P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output.

TRIM

Address: 96h

Not bit addressable

Reset Source(s): Power-up only

Reset Value: On power-up reset, ENCLK = 0, and TRIM.5-0 are loaded with the factory programmed value.

BIT SYMBOL FUNCTION

TRIM.7 - Reserved.

TRIM.6 ENCLK When ENCLK =1, CCLK/ 2 is output on the XTAL2 pin (P3.0) provided that the crystal

TRIM.5-0 Trim value.

Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. When setting or clearing the ENCLK bit, the user should retain the contents of bits 5:0 of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the "ANL direct" or "ORL direct" instructions can be used to clear or set bit 6 of the TRIM register.

76543210

- ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0

oscillator is not being used. When ENCLK=0, no clock output is enabled (P89LPC906).

Figure 2-2: On-Chip RC Oscillator TRIM Register

CPU CLOCK (CCLK) WAKEUP DELAY

The P89LPC906/907/908 has an internal wakeup timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections (P89LPC906), the delay is 992 OSCCLK cycles plus 60-100µs. If the clock source is either the internal RC oscillator or the Watchdog oscillator, the delay is 224 OSCCLK cycles plus 60-100µs.

CPU CLOCK (CCLK) MODIFICATION: DIVM REGISTER

The OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK frequency using the following formula:

CCLK frequency = f

Where: f

Since N ranges from 0 to 255, the CCLK frequency can be in the range of f

This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. This can allow bypassing the oscillator start-up time in cases where Power down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

is the frequency of OSCCLK

OSC

N is the value of DIVM.

OSC

/ (2N)

OSC

to f

/510 ( for N =0, CCLK = f

OSC

) .

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Philips Semiconductors

User’s Manual - Preliminary -

CLOCKS

P89LPC906/907/908

LOW POWER SELECT (P89LPC906)

The P89LPC906 is designed to run at 12MHz (CCLK) maximum. However, if CCLK is 8MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a ’1’ to lower the power consumption further. On any reset, CLKLP is ’0’ allowing highest performance. This bit can then be set in software if CCLK is running at 8MHz or slower.

RTCS1:0

XTAL1

XTAL2

RC Oscillator

(7.3728MHz)

Watchdog

Oscillator

High freq.

Med freq.

Low freq.

FOSC2:0

OSC

CLK

Oscillator

Clock

DIVM

CPU

Clock

RTC

CCLK

CPU

PCLK

WDT

(400KHz)

Timer 0 & 1

Figure 2-3: Block Diagram of Oscillator Control - P89LPC906

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CLOCKS

RC Oscillator

(7.3728MHz)

Watchdog

Oscillator

(400KHz)

FOSC2:0

OSC

CLK

DIVM

CPU

Clock

CCLK

P89LPC906/907/908

RTCS1:0

RTC

CPU

WDT

PCLK

Baud rate

UART

Timer 0 & 1

Generator

Figure 2-4: Block Diagram of Oscillator Control- P89LPC907,P89LPC908

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Philips Semiconductors

User’s Manual - Preliminary -

CLOCKS

P89LPC906/907/908

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