Philips P89LPC901, P89LPC902, P89LPC903 Technical data

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM

Rev. 04 — 21 November 2003 Product data

1. General description

The P89LPC901/902/903 are single-chip microcontrollers in low-cost 8-pin packages, based on a highperformance processorarchitecture that executesinstructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC901/902/903 in order to reduce component count, board space, and system cost.

2. Features

2.1 Principal features

■ 1 kB byte-erasable Flash code memory organized into 256-byte sectors and

16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

■ 128-byte RAM data memory.

■ Two 16-bit counter/timers. (P89LPC901 Timer 0 may be conﬁgured to toggle a

port output upon timer overﬂow or to become a PWM output.)

■ 23-bit system timer that can also be used as a Real-Time clock.

■ Two analog comparators (P89LPC902 and P89LPC903, single analog

comparator on P89LPC901).

■ Enhanced UART with fractional baudrate generator, break detect, framing error

detection, automatic address detection and versatile interrupt capabilities (P89LPC903).

■ High-accuracy internal RC oscillator option allows operation without external

oscillator components. The RC oscillator option is selectable and ﬁne tunable.

■ 2.4 V to 3.6 V VDDoperating range with 5 V tolerant I/O pins (may be pulled up or

driven to 5.5 V). Industry-standard pinout with VDD, VSS, and reset at locations 1, 8, and 4.

■ Up to six I/O pins when using internal oscillator and reset options.

■ 8-pin SO-8 package.

2.2 Additional features

■ A high performance 80C51 CPU provides instruction cycle times of 167 ns to

333 ns for all instructions except multiply and divide when executing at 12 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.

■ In-Application Programming (IAP-Lite) and byte erase allows code memory to be

used for non-volatile data storage.

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■ Serial Flash In-Circuit Programming (ICP) allows simple production coding with

■ Watchdog timer with separate on-chip oscillator, requiring no external

■ Low voltage reset (Brownout detect) allows a graceful system shutdown when

■ Idle and two different Power-downreduced power modes. Improved wake-up from

■ Active-LOWreset. On-chippower-on reset allows operation without external reset

■ Conﬁgurable on-chip oscillator with frequency range options selected by user

■ Watchdog timer with separate on-chip oscillator, requiring no external

■ Programmable port output conﬁguration options: quasi-bidirectional, open drain,

■ Port ‘input pattern match’ detect. Port 0may generate aninterrupt when thevalue

■ LED drive capability (20 mA) on all port pins. A maximum limit is speciﬁed for the

■ Controlled slew rate port outputs to reduce EMI. Outputs have approximately

■ Only power and ground connections are required to operate the

■ Four interrupt priority levels.

■ Two (P89LPC901), three (P89LPC903), or ﬁve (P89LPC902) keypad interrupt

■ Second data pointer.

■ Schmitt trigger port inputs.

■ Emulation support.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

commercial EPROMprogrammers.Flash security bits prevent reading of sensitive application programs.

components. The watchdog prescaler is selectable from 8 values.

power fails. May optionally be conﬁgured as an interrupt.

Power-down mode (a low interrupt input starts execution). Typical Power-down current is 1 µA (total Power-down with voltage comparators disabled).

components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.

programmed Flash conﬁguration bits. Oscillatoroptions support frequencies from 20 kHz to the maximum operating frequency of 12 MHz (P89LPC901).

components. The watchdog prescaler is selectable from 8 values.

push-pull, input-only.

of the pins match or do not match a programmable pattern.

entire chip.

10 ns minimum ramp times.

P89LPC901/902/903 when internal reset option is selected.

inputs.

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3. Ordering information

Table 1: Ordering information

Type number Package

P89LPC901FD SO8 plastic small outline package; 8 leads; P89LPC902FD P89LPC903FD P89LPC901FN DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 P89LPC902FN

3.1 Ordering options

Table 2: Part options

Type number Temperature range Frequency

P89LPC901xx −40 °Cto+85°C 0 to 12 MHz P89LPC902xx Internal RC or watchdog P89LPC903xx Internal RC or watchdog

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Name Description Version

SOT96-1

body width 7.5 mm

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4. Block diagram

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

CRYSTAL

OR

RESONATOR

P89LPC901

1 kB

CODE FLASH

128-BYTE

DATA RAM

PORT 3

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

CONFIGURABLE

OSCILLATOR

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

INTERNAL BUS

CPU CLOCK

ON-CHIP

RC

OSCILLATOR

TIMER 0 TIMER 1

REAL-TIME CLOCK/

SYSTEM TIMER

ANALOG

COMPARATOR

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

002aaa444

Fig 1. P89LPC901 block diagram.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

P89LPC902

CODE FLASH

128-BYTE

DATA RAM

PORT 1

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

ON-CHIP

OSCILLATOR

1 kB

INPUT

RC

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

INTERNAL

BUS

CPU CLOCK

TIMER 0 TIMER 1

REAL-TIME CLOCK/

SYSTEM TIMER

ANALOG

COMPARATORS

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

002aaa445

Fig 2. P89LPC902 block diagram.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

P89LPC903

1 kB

CODE FLASH

128-BYTE

DATA RAM

PORT 1

INPUT

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

ON-CHIP

RC

OSCILLATOR

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

INTERNAL

BUS

CPU CLOCK

UART

TIMER 0 TIMER 1

REAL-TIME CLOCK/

SYSTEM TIMER

ANALOG

COMPARATORS

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

002aaa446

Fig 3. P89LPC903 block diagram.

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Philips Semiconductors

5. Pinning information

5.1 Pinning

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

handbook, halfpage

Fig 4. P89LPC901 pinning (SO8).

handbook, halfpage

CLKOUT/XTAL2/P3.0

Fig 5. P89LPC901 pinning (DIP8).

handbook, halfpage

V

DD

XTAL1/P3.1

CLKOUT/XTAL2/P3.0

RST/P1.5

V

DD

XTAL1/P3.1

RST/P1.5

V

DD

P0.2/CIN2A/KBI2

P0.0/CMP2/KBI0

RST/P1.5

1 2 3 4

P89LPC901FD

002aaa438

P89LPC901FN

002aaa469

P89LPC902FD

002aaa439

V

8

SS

P0.4/CIN1A/KBI4

7

P0.5/CMPREF/KBI5

6

P1.2/T0

5

V

8

SS

P0.4/CIN1A/KBI4

7

P0.5/CMPREF/KBI5

6

P1.2/T0

5

V

8

SS

7

P0.4/CIN1A/KBI4

6

P0.5/CMPREF/KBI5

5

P0.6/CMP1/KBI6

Fig 6. P89LPC902 pinning (SO8).

handbook, halfpage

P0.2/CIN2A/KBI2

P0.0/CMP2/KBI0

V

DD

RST/P1.5

1 2 3 4

P89LPC902FN

002aaa470

V

8

SS

7

P0.4/CIN1A/KBI4

6

P0.5/CMPREF/KBI5 P0.6/CMP1/KBI6

5

Fig 7. P89LPC902 pinning (DIP8).

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

handbook, halfpage

P0.2/CIN2A/KBI2

V

DD

P1.1/RxD RST/P1.5

1 2 3 4

P89LPC903FD

002aaa440

V

8

SS

P0.4/CIN1A/KBI4

7

P0.5/CMPREF/KBI5

6

P1.0/TxD

5

Fig 8. P89LPC903 pinning (SO8).

5.2 Pin description

Table 3: P89LPC901 pin description

Symbol Pin Type Description

P0.0 - P0.6 6, 7 I/O Port 0: Port 0 isan I/O port with a user-conﬁgurable output type. During reset Port 0

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port

conﬁgurations” and Table 13 “DC electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

7 I/O P0.4 — Port 0 bit 4.

I CIN1A — Comparator 1 positive input. I KBI4 — Keyboard input 4.

6 I/O P0.5 — Port 0 bit 5.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5.

P1.0 - P1.5 4, 5 Port 1: Port 1 is an I/O port with a user-conﬁgurable output type. During resetPort 1

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the port conﬁguration selected. Each of the conﬁgurable port pins are programmed independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “DC

electrical characteristics” for details. P1.5 is input only.

All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

5 I/O P1.2 — Port 1 bit 2.

O T0 — Timer/counter 0 external count input or overﬂow output.

4IP1.5 — Port 1 bit 5 (input only).

I

RST — External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input aLOW on this pin resetsthe microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Table 3: P89LPC901 pin description

Symbol Pin Type Description

P3.0 - P3.1 2, 3 I/O Port 3: Port 3 is an I/O port with a user-conﬁgurableoutput types. During reset Port 3

3 I/O P3.0 — Port 3 bit 0.

O XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is

O CLKOUT — CPU clock divided by 2 when enabled via SFR bit(ENCLK -TRIM.6). It

2 I/O P3.1 — Port 3 bit 1.

I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

V

SS

V

DD

8IGround: 0 V reference. 1IPower Supply: This is the power supply voltage for normal operation as well as Idle

…continued

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of port 3 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port

conﬁgurations” and Table 13 “DC electrical characteristics” for details.

All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below:

selected via the FLASH conﬁguration).

can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the real time clock/system timer.

selected via the FLASH conﬁguration).It can be a port pin if internal RC oscillator or Watchdog oscillator is used as the CPU clock source,and if XTAL1/XTAL2 are not used to generate the clock for the real time clock/system timer.

and Power-down modes.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Table 4: P89LPC902 pin description

Symbol Pin Type Description

P0.0 - P0.6 2, 3, 5, 6,7I/O Port 0: Port 0 is an I/O port with a user-conﬁgurable output type. During reset Port 0

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port

conﬁgurations” and Table 13 “DC electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

3 I/O P0.0 — Port 0 bit 0.

I CMP2 — Comparator 2 output. I KBI0 — Keyboard input 0.

2 I/O P0.2 — Port 0 bit 2.

I CIN2A — Comparator 2 positive input. I KBI2 — Keyboard input 2.

7 I/O P0.4 — Port 0 bit 4.

I CIN1A — Comparator 1 positive input. I KBI4 — Keyboard input 4.

6 I/O P0.5 — Port 0 bit 5.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5.

5 I/O P0.6 — Port 0 bit 6.

O CMP1 — Comparator 1 output. I KBI6 — Keyboard input 6.

P1.0 - P1.5 4 Port 1: Port 1 is an I/O port with a user-conﬁgurable output type. During reset Port 1

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the port conﬁguration selected. Each of the conﬁgurable port pins are programmed independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “DC

electrical characteristics” for details. P1.5 is input only.

All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

4IP1.5 — Port 1 bit 5 (input only).

I

V

SS

V

DD

8IGround: 0 V reference. 1IPower Supply: This is the power supply voltage for normal operation as well as Idle

RST — External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

and Power-down modes.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Table 5: P89LPC903 pin description

Symbol Pin Type Description

P0.0 - P0.6 2, 6, 7 I/O Port 0: Port 0 is an I/O port with a user-conﬁgurable output type. During reset Port 0

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port

conﬁgurations” and Table 13 “DC electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

2 I/O P0.2 — Port 0 bit 2.

I CIN2A — Comparator 2 positive input. I KBI2 — Keyboard input 2.

7 I/O P0.4 — Port 0 bit 4.

I CIN1A — Comparator 1 positive input. I KBI4 — Keyboard input 4.

6 I/O P0.5 — Port 0 bit 5.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5.

P1.0 - P1.5 3, 4, 5 Port 1: Port 1 is an I/O port with a user-conﬁgurable output type. During reset Port 1

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the port conﬁguration selected. Each of the conﬁgurable port pins are programmed independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “DC

electrical characteristics” for details. P1.5 is input only.

All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

5 I/O P1.0 — Port 1 bit 0.

O TxD — Serial port transmitter data.

3 I/O P1.1 — Port 1 bit 1.

I RxD — Serial port receiver data.

4IP1.5 — Port 1 bit 5 (input only).

I

V

SS

V

DD

8IGround: 0 V reference. 1IPower Supply: This is the power supply voltage for normal operation as well as Idle

RST — External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

and Power-down modes.

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6. Logic symbols

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

V

DDVSS

KBI4 KBI5

CLKOUT

Fig 9. P89LPC901 logic symbol.

KBI4 KBI5 KBI6 KBI2 KBI0

Fig 10. P89LPC902 logic symbol.

CIN1A

CMPREF

XTAL2 XTAL1

CIN1A

CMPREF

CMP1

CIN2A

CMP2

PORT 0

PORT 3

VDDV

P89LPC901

002aaa441

SS

P89LPC902

002aaa442

PORT 1

RST

RST T0

VDDV

SS

KBI4 KBI5 KBI2

CIN1A

CMPREF

CIN2A

PORT 0

PORT 1

RST RxD TxD

P89LPC903

002aaa443

Fig 11. P89LPC903 logic symbol.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Table 6 highlights the differences between these three devices. For a complete list of

device features, please see Section 2 “Features” on page 1.

Table 6: Product comparison overview

Type number External

crystal pins

P89LPC901xx X X X - - - P89LPC902xx - - - X X - P89LPC903xx - - - X - X X

CLKOUT output T0 PWM output CMP2 input CMP1 and

CMP2 outputs

UART TxD Rxd

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7. Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following

ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the

SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read. – ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

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Product data Rev. 04 — 21 November 2003 14 of 55

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Table 7: P89LPC901 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP - - ENT0 SRST 0 - DPS 00

B* B register F0H 00 00000000 CMP1 Comparator 1 control register ACH - - CE1 - CN1 - CO1 CMF1 00 DIVM CPU clock divide-by-M

DPTR Data pointer (2 bytes)

DPH Data pointer HIGH 83H 00 00000000

DPL Data pointer LOW 82H 00 00000000 FMADRH Program Flash address HIGH E7H 00 00000000 FMADRL Program Flash address LOW E6H 00 00000000 FMCON Program Flash Control

FMDATA Program Flash data E5H 00 00000000 IEN0* Interrupt enable 0 A8H EA EWDRT EBO - ET1 - ET0 - 00 00000000

IEN1* Interrupt enable 1 E8H -----ECEKBI - 00

IP0* Interrupt priority 0 B8H - PWDRT PBO - PT1 - PT0 - 00 IP0H Interrupt priority 0 HIGH B7H - PWDRTHPBOH - PT1H - PT0H - 00

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

addr.

Bit address E7 E6 E5 E4 E3 E2 E1 E0

Bit address F7 F6 F5 F4 F3 F2 F1 F0

95H 00 00000000

control

E4H BUSY - - - HVA HVE SV OI 70 01110000

(Read) Program Flash Control

(Write)

Bit address EF EE ED EC EB EA E9 E8

Bit address BF BE BD BC BB BA B9 B8

MSB LSB Hex Binary

FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

Bit functions and addresses Reset value

[1]

0

[1]

[1] [1]

Philips Semiconductors

000000x0

xx000000

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903

00x00000

x0000000 x0000000

Bit address FF FE FD FC FB FA F9 F8

IP1* Interrupt priority 1 F8H -----PCPKBI - 00 IP1H Interrupt priority 1 HIGH F7H -----PCHPKBIH - 00 KBCON Keypad control register 94H ------PATN

KBIF 00

_SEL

[1] [1] [1]

00x00000 00x00000 xxxxxx00

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Table 7: P89LPC901 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

P0* Port 0 80H - - CMPREF

P1* Port 1 90H - -

P3*Port3 B0H------XTAL1XTAL2 P0M1 Port 0 output mode 1 84H - - (P0M1.5) (P0M1.4) ----FF11111111 P0M2 Port 0 output mode 2 85H - - (P0M2.5) (P0M2.4) ----0000000000 P1M1 Port 1 output mode 1 91H - - (P1M1.5) - - (P1M1.2) - - FF P1M2 Port 1 output mode 2 92H - - (P1M2.5) - - (P1M2.2) - - 00 P3M1 Port 3 output mode 1 B1H ------(P3M1.1) (P3M1.0) 03 P3M2 Port 3 output mode 2 B2H ------(P3M2.1) (P3M2.0) 00 PCON Power control register 87H - - BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD VCPD - - 00 PCONB reserved for Power Control

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 ----00xx00000x RSTSRC Reset source register DFH - - BOF POF - R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60

RTCH Real-time clock register HIGH D2H 00 RTCL Real-time clock register LOW D3H 00 SP Stack pointer 81H 07 00000111 TAMOD Timer 0 auxiliary mode 8FH -------T0M2 00 xxx0xxx0

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

addr.

86H 00 00000000

register

Bit address 87 86 85 84 83 82 81 80

Bit address 97 96 95 94 93 92 91 90

Bit address B7 B6 B5 B4 B3 B2 B1 B0

B6H--------00

Register B

Bit address D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB Hex Binary

Bit functions and addresses Reset value

[1]

[3]

[6]

/KB5

CIN1A

/KB4

----

RST - - T0 - -

[1] [1] [1] [1]

[1] [1]

[1]

[6] [6]

11111111 00000000 xxxxxx11 xxxxxx00

00000000 xxxxxxxx

011xxx00

00000000 00000000

Philips Semiconductors

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Product data Rev. 04 — 21 November 2003 17 of 55

Table 7: P89LPC901 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 ----0000000000 TH0 Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TL0 Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H - - T1M1 T1M0 - - T0M1 T0M0 00 00000000 TRIM Internal oscillator trim register 96H - - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H

[1] All ports are in input only (high impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reﬂects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOFbit is ‘1’ after Watchdogreset and is ‘0’ after power-on reset. Other resets will

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset.

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

Bit address 8F 8E 8D 8C 8B 8A 89 88

Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise speciﬁed, ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.

value is xx110000.

not affect WDTOF.

MSB LSB Hex Binary

[5] [6] [4] [6]

Philips Semiconductors

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

9397 750 12293

Product data Rev. 04 — 21 November 2003 18 of 55

Table 8: P89LPC902 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000 AUXR1 Auxiliary function register A2H ----SRST 0 - DPS 00

B* B register F0H 00 00000000 CMP1 Comparator 1 control register ACH - - CE1 - CN1 OE1 CO1 CMF1 00 CMP2 Comparator 2 control register ADH - - CE2 - CN2 OE2 CO2 CMF2 00 DIVM CPU clock divide-by-M

DPTR Data pointer (2 bytes)

DPH Data pointer HIGH 83H 00 00000000

DPL Data pointer LOW 82H 00 00000000 FMADRH Program Flash address HIGH E7H 00 00000000 FMADRL Program Flash address LOW E6H 00 00000000 FMCON Program Flash Control

FMDATA Program Flash data E5H 00 00000000 IEN0* Interrupt enable 0 A8H EA EWDRT EBO - ET1 - ET0 - 00 00000000

IEN1* Interrupt enable 1 E8H -----ECEKBI - 00

IP0* Interrupt priority 0 B8H - PWDRT PBO - PT1 - PT0 - 00 IP0H Interrupt priority 0 HIGH B7H - PWDRTHPBOH - PT1H - PT0H - 00

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

addr.

Bit address E7 E6 E5 E4 E3 E2 E1 E0

Bit address F7 F6 F5 F4 F3 F2 F1 F0

95H 00 00000000

control

E4H BUSY - - - HVA HVE SV OI 70 01110000

(Read) Program Flash Control

(Write)

Bit address EF EE ED EC EB EA E9 E8

Bit address BF BE BD BC BB BA B9 B8

MSB LSB Hex Binary

FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

Bit functions and addresses Reset value

[1]

[1] [1]

0

[1]

[1] [1]

Philips Semiconductors

000000x0

xx000000 xx000000

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903

00x00000

x0000000 x0000000

Bit address FF FE FD FC FB FA F9 F8

IP1* Interrupt priority 1 F8H -----PCPKBI - 00 IP1H Interrupt priority 1 HIGH F7H -----PCHPKBIH - 00

[1] [1]

00x00000 00x00000

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Product data Rev. 04 — 21 November 2003 19 of 55

Table 8: P89LPC902 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

KBCON Keypad control register 94H ------PATN

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

P0* Port 0 80H - CMP1

P1* Port 1 90H - -

P0M1 Port 0 output mode 1 84H - (P0M1.6) (P0M1.5) (P0M1.4) - (P0M1.2) - (P0M1.0) FF 11111111 P0M2 Port 0 output mode 2 85H - (P0M2.6) (P0M2.5) (P0M2.4) - (P0M2.2) - (P0M2.0) 00 00000000 P1M1 Port 1 output mode 1 91H - - (P1M1.5) -----FF P1M2 Port 1 output mode 2 92H - - (P1M2.5) -----00 PCON Power control register 87H - - BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD VCPD - - 00 PCONB reserved for Power Control

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000

PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 - PT0AD.2 - - 00 xx00000x RSTSRC Reset source register DFH - - BOF POF - R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60

RTCH Real-time clock register HIGH D2H 00 RTCL Real-time clock register LOW D3H 00 SP Stack pointer 81H 07 00000111

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…continued

addr.

86H 00 00000000

register

Bit address 87 86 85 84 83 82 81 80

Bit address 97 96 95 94 93 92 91 90

Bit address B7 B6 B5 B4 B3 B2 B1 B0

B6H--------00

Register B

Bit address D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB Hex Binary

/KB6

Bit functions and addresses Reset value

KBIF 00

_SEL

CMPREF

/KB5

CIN1A

/KB4

- KB2 - KB0

RST-----

[1]

[1] [1]

[3]

[1]

[6]

[6] [6]

xxxxxx00

11111111 00000000

00000000 xxxxxxxx

011xxx00

00000000 00000000

Philips Semiconductors

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Product data Rev. 04 — 21 November 2003 20 of 55

Table 8: P89LPC902 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 ----0000000000 TH0 Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TL0 Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H - - T1M1 T1M0 - - T0M1 T0M0 00 00000000 TRIM Internal oscillator trim register 96H - - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H

[1] All ports are in input only (high impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reﬂects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOFbit is ‘1’ after Watchdogreset and is ‘0’ after power-on reset. Other resets will

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset.

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

Bit functions and addresses Reset value

addr.

Bit address 8F 8E 8D 8C 8B 8A 89 88

Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise speciﬁed, ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.

value is xx110000.

not affect WDTOF.

MSB LSB Hex Binary

[5] [6] [4] [6]

Philips Semiconductors

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Product data Rev. 04 — 21 November 2003 21 of 55

Table 9: P89LPC903 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000 AUXR1 Auxiliary function register A2H - EBRR - - SRST 0 - DPS 00

B* B register F0H 00 00000000 BRGR0

BRGR1

BRGCON Baud rate generator control BDH ------SBRGS BRGEN 00 CMP1 Comparator 1 control register ACH - - CE1 - CN1 - CO1 CMF1 00 CMP2 Comparator 2 control register ADH - - CE2 - CN2 - CO2 CMF2 00 DIVM CPU clock divide-by-M

DPTR Data pointer (2 bytes)

DPH Data pointer HIGH 83H 00 00000000

DPL Data pointer LOW 82H 00 00000000 FMADRH Program Flash address HIGH E7H 00 00000000 FMADRL Program Flash address LOW E6H 00 00000000 FMCON Program Flash Control

FMDATA Program Flash data E5H 00 00000000 IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 - ET0 - 00 00000000

IEN1* Interrupt enable 1 E8H - EST - - - EC EKBI - 00

IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 - PT0 - 00

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

[2]

Baud rate generator rate LOW

[2]

Baud rate generator rate HIGH

control

(Read) Program Flash Control

(Write)

addr.

Bit address E7 E6 E5 E4 E3 E2 E1 E0

Bit address F7 F6 F5 F4 F3 F2 F1 F0

BEH 00 00000000

BFH 00 00000000

95H 00 00000000

E4H BUSY - - - HVA HVE SV OI 70 01110000

Bit address EF EE ED EC EB EA E9 E8

Bit address BF BE BD BC BB BA B9 B8

MSB LSB Hex Binary

FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

Bit functions and addresses Reset value

[1]

[6] [1] [1]

0

[1]

Philips Semiconductors

000000x0

xxxxxx00 xx000000 xx000000

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903

00x00000

x0000000

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Product data Rev. 04 — 21 November 2003 22 of 55

Table 9: P89LPC903 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

IP0H Interrupt priority 0 HIGH B7H - PWDRTHPBOH PSH

IP1* Interrupt priority 1 F8H - PST - - - PC PKBI - 00 IP1H Interrupt priority 1 HIGH F7H - PSTH - - - PCH PKBIH - 00 KBCON Keypad control register 94H ------PATN

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

P0* Port 0 80H - - CMPREF

P1* Port 1 90H - P0M1 Port 0 output mode 1 84H - - (P0M1.5) (P0M1.4) - (P0M1.2) - - FF 11111111 P0M2 Port 0 output mode 2 85H - - (P0M2.5) (P0M2.4) - (P0M2.2) - - 00 00000000 P1M1 Port 1 output mode 1 91H - - (P1M1.5) - - - (P1M1.1) (P1M1.0) FF P1M2 Port 1 output mode 2 92H - - (P1M2.5) - - - (P1M2.1) (P1M2.0) 00 PCON Power control register 87H SMOD1 SMOD0 BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD VCPD - SPD 00

PCONB reserved for Power Control

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 - PT0AD.2 - - 00 xx00000x RSTSRC Reset source register DFH - - BOF POF R_BK R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60

RTCH Real-time clock register HIGH D2H 00

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…continued

addr.

Bit address FF FE FD FC FB FA F9 F8

86H 00 00000000

register

Bit address 87 86 85 84 83 82 81 80

Bit address 97 96 95 94 93 92 91 90

B6H--------00

Register B

Bit address D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB Hex Binary

Bit functions and addresses Reset value

PT1H - PT0H - 00

/PSRH

KBIF 00

_SEL

[1]

/KB5

CIN1A

/KB4

- KB2 - -

RST - - - RxD TxD

[3]

[6]

[1]

[1] [1] [1]

[1]

[1] [1]

[1]

[6]

x0000000

00x00000 00x00000 xxxxxx00

11111111 00000000

00000000 xxxxxxxx

011xxx00

00000000

Philips Semiconductors

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Product data Rev. 04 — 21 November 2003 23 of 55

Table 9: P89LPC903 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

RTCL Real-time clock register LOW D3H 00 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial port data buffer register 99H xx xxxxxxxx

SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status

SP Stack pointer 81H 07 00000111

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 ----0000000000 TH0 Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TL0 Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H - - T1M1 T1M0 - - T0M1 T0M0 00 00000000 TRIM Internal oscillator trim register 96H - - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H

WFEED2 Watchdog feed 2 C3H

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…continued

addr.

Bit address 9F 9E 9D 9C 9B 9A 99 98

BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000

register

Bit address 8F 8E 8D 8C 8B 8A 89 88

MSB LSB Hex Binary

Bit functions and addresses Reset value

[6]

[5] [6] [4] [6]

Philips Semiconductors

00000000

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903

[1] All ports are in input only (high impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.

Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise speciﬁed, ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.

[3] The RSTSRC register reﬂects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset

value is xx110000.

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOFbit is ‘1’ after Watchdogreset and is ‘0’ after power-on reset. Other resets will

not affect WDTOF. [5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset.

Philips Semiconductors

8. Functional description

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Remark: Please refer to the

functional description.

8.1 Enhanced CPU

The P89LPC901/902/903 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

8.2 Clocks

8.2.1 Clock deﬁnitions

The P89LPC901/902/903 device has several internal clocks as deﬁned below: OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of the

clock sources (see Figures 12, 13, and 14) and can also be optionally divided to a slower frequency (see Section 8.7 “CPU CLOCK (CCLK) modiﬁcation: DIVM

register”).

Note: f CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per

machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output. PCLK — Clock for the various peripheral devices and is CCLK/2

is deﬁned as the OSCCLK frequency.

OSC

P89LPC901/902/903 User’s Manual

for a more detailed

8.2.2 CPU clock (OSCCLK)

The P89LPC901/902/903 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are conﬁgured when the FLASH is programmed and include an on-chip Watchdog oscillator and an on-chip RC oscillator.

The P89LPC901, in addition, includes an option for an oscillator using an external crystal or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.

8.2.3 Low speed oscillator option (P89LPC901)

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this conﬁguration.

8.2.4 Medium speed oscillator option (P89LPC901)

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this conﬁguration.

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Philips Semiconductors

8.2.5 High speed oscillator option (P89LPC901)

This option supports an external crystal in the range of 4 MHz to 12 MHz. Ceramic resonators are also supported in this conﬁguration. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to reduce power consumption. On reset, CLKLP is ‘0’ allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

8.2.6 Clock output (P89LPC901)

The P89LPC901 supports a user selectable clock output function on the XTAL2/CLKOUTpin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, Watchdog oscillator, external clock input on X1) and if the Real-Time clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC901. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is1⁄2that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.3 On-chip RC oscillator option

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

The P89LPC901/902/903 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz, ±2.5%. End-user applications can write to the Trim register to adjust the on-chip RC oscillator to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to reduce power consumption. On reset, CLKLP is ‘0’ allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

8.4 Watchdog oscillator option

The Watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.

8.5 External clock input option (P89LPC901)

In this conﬁguration, the processor clock is derived from an external source driving the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2/P3.0 pin may be used as a standard port pin or a clock output.

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Product data Rev. 04 — 21 November 2003 25 of 55

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

XTAL1 XTAL2

High freq. Med. freq.

Low freq.

RC

OSCILLATOR (7.3728 MHz)

WATCHDOG

OSCILLATOR

(400 kHz)

DIVM

CCLKOSCCLK

Fig 12. Block diagram of oscillator control (P89LPC901).

RC

OSCILLATOR

(7.3728 MHz)

WATCHDOG

OSCILLATOR

(400 kHz)

DIVM

CCLKOSCCLK

¸

2

PCLK

¸

2

PCLK

TIMERS 0 & 1

RTC

CPU

WDT

TIMERS 0 & 1

002aaa447

RTC

CPU

WDT

Fig 13. Block diagram of oscillator control (P89LPC902).

RC

OSCILLATOR

(7.3728 MHz)

WATCHDOG

OSCILLATOR

(400 kHz)

BAUD RATE

GENERATOR

DIVM

CCLKOSCCLK

UART

Fig 14. Block diagram of oscillator control (P89LPC903).

002aaa448

RTC

CPU

¸

2

WDT

PCLK

TIMERS 0 & 1

002aaa449

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Philips Semiconductors

8.6 CPU CLock (CCLK) wake-up delay

The P89LPC901/902/903 has an internal wake-up timer that delays the clock until it stabilizes depending to the clock source used. If the clock source is any of the three crystal selections (P89LPC901) the delay is 992 OSCCLK cycles plus 60 to 100 µs.

8.7 CPU CLOCK (CCLK) modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

8.8 Low power select

The P89LPC901 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower,the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

8.9 Memory organization

The various P89LPC901/902/903 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC901/902/903 has 1 kB of on-chip Code memory.

8.10 Data RAM arrangement

The 128 bytes of on-chip RAM is organized as follows:

Table 10: On-chip data memory usages

Type Data RAM Size (Bytes)

DATA Memory that can be addressed directly and indirectly 128

8.11 Interrupts

The P89LPC901/902/903 uses a four priority level interrupt structure. This allows great ﬂexibility in controlling the handling of the many interrupt sources.

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Philips Semiconductors

The P89LPC901 supports 6 interrupt sources: timers 0 and 1, brownout detect, Watchdog/real-time clock, keyboard, and the comparator.

The P89LPC902 supports 6 interrupt sources: timers 0 and 1, brownout detect, Watchdog/real-time clock, keyboard, and comparators 1 and 2.

The P89LPC903 supports 9 interrupt sources: timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx, brownout detect, Watchdog/real-time clock, keyboard, and comparators 1 and 2.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.

8.11.1 External interrupt inputs

The P89LPC901/902/903 has a Keypad Interrupt function. This can be used as an external interrupt input.

If enabled when the P89LPC901/902/903 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section

8.14 “Power reduction modes” for details.

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RTCF ERTC

(RTCCON.1)

WDOVF

BOPD

EBO

KBIF EKBI

EWDRT

CMF

EC

EA (IE0.7)

TF1 ET1

TF0 ET0

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

WAKE-UP (IF IN POWER-DOWN)

INTERRUPT TO CPU

002aaa450

Fig 15. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC901).

BOPD

EBO RTCF ERTC

(RTCCON.1)

WDOVF

KBIF EKBI

EWDRT

CMF

EC

EA (IE0.7)

TF1 ET1

TF0 ET0

WAKE-UP (IF IN POWER-DOWN)

002aaa451

Fig 16. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC902).

INTERRUPT TO CPU

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RTCF ERTC

(RTCCON.1)

WDOVF

BOPD

EBO

KBIF EKBI

EWDRT

CMF

EC

EA (IE0.7)

TF1

ET1

TI & RI/RI

ES/ESR

EST

TF0

ET0

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

WAKE-UP (IF IN POWER-DOWN)

TI

INTERRUPT TO CPU

002aaa452

Fig 17. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC903).

8.12 I/O ports

The P89LPC901 has between 3 and 6 I/O pins: P0.4, P0.5, P1.2, P1.5, P3.0, and P3.1 The exact number of I/O pins available depends on the clock and reset options chosen, as shown in Table 11.

Table 11: Number of I/O pins available

Clock source Reset option Number of I/O pins

(8-pin package)

On-chip oscillator or Watchdog oscillator No external reset (except during power-up) 6

External

External clock input No external reset (except during power-up) 5

External

Low/medium/high speed oscillator (external crystal or resonator)

No external reset (except during power-up) 4 External

The P89LPC902 and P89LPC903 devices have either 5 or 6 I/O pins depending on the reset pin option chosen.

8.12.1 Port conﬁgurations

All but one I/O port pin on the P89LPC901/902/903 may be conﬁgured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two conﬁguration registers for each port select the output type for each port pin.

RST pin supported 5

RST pin supported 4

RST pin supported 3

P1.5 (RST) can only be an input and cannot be conﬁgured.

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8.12.2 Quasi-bidirectional output conﬁguration

Quasi-bidirectional output type can be used as both an input and output without the need to reconﬁgure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes.

The P89LPC901/902/903 is a 3 V device, however, the pins are 5 V-tolerant (except for XTAL1 and XTAL2). In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current ﬂowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

8.12.3 Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be used as a logic output, a port conﬁgured in this manner must have an external pull-up, typically a resistor tied to VDD.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

An open-drain port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

8.12.4 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt-triggered input that also has a glitch suppression circuit.

8.12.5 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic ‘1’. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

8.12.6 Port 0 analog functions

The P89LPC901/902/903 incorporates an Analog Comparator. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port output into the Input-Only (high impedance) mode as described in Section 8.12.4 “Input-only conﬁguration”.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any reset, the PT0AD bits default to ‘0’s to enable digital functions.

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8.12.7 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different from the LPC76x series of devices.

• After power-up all I/O pins, except P1.5, may be conﬁgured by software.

• Pin P1.5 is input only.

Every output on the P89LPC901/902/903 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 13 “DC electrical characteristics” for detailed speciﬁcations.

All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

8.13 Power monitoring functions

The P89LPC901/902/903 incorporates power monitoring functions designed to preventincorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout detect.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

8.13.1 Brownout detection

The Brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a Brownout detection to cause a processor reset, however, it may alternatively be conﬁgured to generate an interrupt.

Brownout detection may be enabled or disabled in software. If Brownout detection is enabled, the operating voltagerangefor VDDis 2.7 V to 3.6 V,

and the brownout condition occurs when VDD falls below the brownout trip voltage, VBO (see Table 13 “DC electrical characteristics”), and is negated when VDD rises above VBO. If brownout detection is disabled, the operating voltage range for VDD is

2.4 V to 3.6 V. If the P89LPC901/902/903 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating.

For correct activation of Brownout detect, the VDD rise and fall times must be observed. Please see Table 13 “DC electrical characteristics” for speciﬁcations.

8.13.2 Power-on detection

The Power-onDetect has a function similar to the Brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where Brownout detect can work. The POF ﬂag in the RSTSRC register is set to indicate an initial power-up condition. The POF ﬂag will remain set until cleared by software.

8.14 Power reduction modes

The P89LPC901/902/903 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and total Power-down mode.

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8.14.1 Idle mode

Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.

8.14.2 Power-down mode

The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC901/902/903 exits Power-downmode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage V Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to V via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited.

Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during Power-down.These include: Brownout detect, Watchdog Timer, Comparators (note that Comparators can be powered-down separately), and Real-Time Clock (RTC)/System Timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

. This retains the RAM contents at the point where

RAM

, therefore it is highly recommended to wake up the processor

RAM

8.14.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during Power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the Real-Time Clock running during Power-down.

8.15 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin will always function as a reset input. An external circuit connected to this pin

should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this input will function either as an external reset

input or as a digital input as deﬁned by the RPE bit. Only a power-up reset will temporarily override the selection deﬁned by RPE bit. Other sources of reset will not override the RPE bit.

Remark: During a power cycle, VDDmust fallbelowV

(see Table13 “DC electrical

POR

characteristics”) before power is reapplied, in order to ensure a power-on reset.

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Reset can be triggered from the following sources:

• External reset pin (during power-up or if user conﬁgured via UCFG1)

• Power-on detect

• Brownout detect

• Watchdog Timer

• Software reset

• UART break character detect reset (P80LPC903).

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These ﬂag bits can be cleared in software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

• For any other reset, previously set ﬂag bits that have not been cleared will remain

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

cleared.

set.

8.16 Timers/counters 0 and 1

The P89LPC901/902/903 has two general purpose timers which are similar to the standard 80C51 Timer 0 and Timer 1. These timers have four operating modes (modes 0, 1, 2, and 3). Modes 0, 1, and 2 are the same for both Timers. Mode 3 is different.

8.16.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is conﬁgured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.

8.16.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.

8.16.3 Mode 2

Mode 2 conﬁgures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.

8.16.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.

8.16.5 Mode 6 (P89LPC901)

In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.

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8.16.6 Timer overﬂow toggle output (P89LPC901)

Timers 0 and 1 can be conﬁgured to automatically toggle a port output whenever a timer overﬂow occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the ﬁrst timer overﬂow when this mode is turned on.

8.17 Real-Time clock/system timer

The P89LPC901/902/903 has a simple Real-Time clock that allows a user to continue running an accurate timer while the rest of the device is powered-down. The Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF ﬂag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as its clock source. Only power-on reset will reset the Real-Time clock and its associated SFRs to the default state.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

8.18 UART (P89LPC903)

The P89LPC903 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source. The P89LPC903 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overﬂow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU clock/16.

8.18.1 Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at1⁄16 of the CPU clock frequency.

8.18.2 Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit (logical ‘0’), 8 data bits (LSB ﬁrst), and a stop bit (logical ‘1’). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in Section 8.18.5 “Baud rate generator and selection”).

8.18.3 Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logical ‘0’), 8 data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logical ‘1’). When data is transmitted, the 9thdata bit (TB8 in SCON) can be assigned the value of ‘0’ or ‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not saved. The baud rate is programmable to either1⁄16 or1⁄32 of the CPU clock frequency, as determined by the SMOD1 bit in PCON.

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8.18.4 Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit (logical ‘0’), 8 data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logical ‘1’). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in section Section 8.18.5 “Baud rate generator

and selection”).

8.18.5 Baud rate generator and selection

The P89LPC903 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing functions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 18). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent Baud Rate Generator uses CCLK.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Timer 1 Overflow

(PCLK-based)

Baud Rate Generator

(CCLK-based)

Fig 18. Baud rate sources for UART (Modes 1, 3).

8.18.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is ‘1’, framing errors can be made available in SCON.7, respectively. If SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is ‘0’.

8.18.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device.

8.18.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the ﬁrst character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character.

¸

2

SMOD1 = 1

SMOD1 = 0

SBRGS = 0

SBRGS = 1

Baud Rate Modes 1 and 3

002aaa419

Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = ‘0’), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = ‘0’).

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8.18.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)

Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated when the double buffer is ready to receive new data.

8.18.10 The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)

If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the Tx interrupt.

If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.

8.19 Analog comparators

One analog comparator is provided on the P89LPC901. Two analog comparators are provided on the P89LPC902 and P89LPC903 devices. Comparator operation is such that the output is a logical one (which may be read in a register) when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. The comparator may be conﬁgured to cause an interrupt when the output value changes.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

The connections to the comparator are shown in Figure 19. Note: Not all possible comparator conﬁgurations are available on all three devices. Please refer to the Logic diagrams in Section 6 “Logic symbols” on page 12. The comparator functions to VDD= 2.4 V.

When the comparator is ﬁrst enabled, the comparator output and interrupt ﬂag are not guaranteed to be stable for 10 microseconds. The comparator interrupt should not be enabled during that time, and the comparator interrupt ﬂag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.

When a comparator is disabled the comparator’s output, COx, goes HIGH. If the comparator output was LOW and then is disabled, the resulting transition of the comparator output from a LOW to HIGH state will set the comparator ﬂag, CMFx. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator ﬂag, CMFx, after disabling the comparator.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Comparator 1

(P0.4) CIN1A

(P0.5) CMPREF

V

REF

CN1

Comparator 2

(P0.2) CIN2A

CN2

Fig 19. Comparator input and output connections.

8.20 Internal reference voltage

An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as V

, is 1.23 V ±10%.

REF

CO1

Change Detect

CO2

OE1

OE2

CMP1 (P0.6)

CMF1

Interrupt

EC

CMF2

CMP2 (P0.0)

002aaa453

8.21 Comparator interrupt

Each comparator has an interrupt ﬂag contained in its conﬁguration register. This ﬂag is set whenever the comparator output changes state. The ﬂag may be polled by software or may be used to generate an interrupt.

8.22 Comparator and power reduction modes

The comparators may remain enabled when Power-down or Idle mode is activated, but the comparators are disabled automatically in Total Power-down mode.

If the comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor.If the comparator output to a pin is enabled, the pin should be conﬁgured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place.

The comparator consumes power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparator via PCONA.5 or put the device in Total Power-down mode.

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8.23 Keypad interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can conﬁgure the port via SFRs for different tasks.

The Keypad Interrupt Mask Register (KBMASK) is used to deﬁne which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to deﬁne a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to deﬁne equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery powered systems that need to carefully manage power consumption yet also need to be convenient to use.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

In order to set the ﬂag and cause an interrupt, the pattern on Port 0 must be held longer than 6 CCLKs.

8.24 Watchdog timer

The Watchdog timer causes a system reset when it underﬂows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz Watchdog oscillator. The Watchdog timer can only be reset by a power-on reset. When the Watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 20 shows the Watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the Watchdog clock and the CPU is powered-down, the watchdog is disabled. The Watchdog timer has a time-out period that ranges from afewµs to a few seconds. Please refer to the more details.

P89LPC901/902/903 User’s Manual

for

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MOV WFEED1, #0A5H MOV WFEED2, #05AH

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

WDL (C1H)

Watchdog

oscillator

PCLK

(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a

feed sequence.

÷32

WDCON (A7H)

PRESCALER

CONTROL REGISTER

PRE2 PRE1 PRE0 – – WDRUN WDTOF WDCLK

8-BIT DOWN

COUNTER

RESET see note (1)

002aaa423

Fig 20. Watchdog timer in Watchdog mode (WDTE = ‘1’).

8.25 Additional features

8.25.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or Watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.

SHADOW REGISTER FOR WDCON

8.25.2 Dual data pointers

The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic ‘0’ so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1register, without the possibility of inadvertently altering other bits in the register.

8.26 Flash program memory

8.26.1 General description

The P89LPC901/902/903 Flash memory provides in-circuit electrical erasure and programming. The Flash can be erased, read, and written as bytes. The Sector and PageErase functions can erase any Flash sector (256 bytes) or page (16 bytes). The Chip Erase operation will erase the entire program memory. In-Circuit Programming using standard commercial programmers is available. In addition, In-Application Programming (IAP) and byte erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC901/902/903 Flash reliably stores memory contents even after more than 100,000 erase and program cycles. The cell is

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designed to optimize the erase and programming mechanisms. The P89LPC901/902/903 uses VDD as the supply voltage to perform the Program/Erase algorithms.

8.26.2 Features

• Programming and erase over the full operating voltage range.

• Byte-erase allowing code memory to be used for data storage.

• Read/Programming/Erase using ICP.

• Any ﬂash program/erase operation in 2 ms.

• Programming with industry-standard commercial programmers.

• Programmable security for the code in the Flash for each sector.

• More than 100,000 minimum erase/program cycles for each byte.

• 10-year minimum data retention.

8.26.3 Flash organization

The P89LPC901/902/903 program memory consists of four 256 byte sectors. Each sector can be further divided into 16-byte pages. In addition to sector erase, page erase, and byte erase, a 16-byte page register is included which allows from 1 to 16 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. In addition, erasing and reprogramming of user-programmable conﬁguration bytes including UCFG1, the Boot Status Bit, and the Boot Vector is supported.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

8.26.4 Flash programming and erasing

Different methods of erasing or programming of the Flash are available. The Flash may be programmed or erased in the end-user application (IAP) under control of the application’s ﬁrmware. Another option is to use the In-Circuit Programming (ICP) mechanism. This ICP system provides for programming through a serial clock- serial data interface. Third, the Flash may be programmed or erased using a commercially available EPROM programmer which supports this device. This device does not provide for direct veriﬁcation of code memory contents. Instead this device provides a 32-bit CRC result on either a sector or the entire 1 KB of user code space.

8.26.5 In-circuit programming (ICP)

In-Circuit Programming is performed without removing the microcontroller from the system. The In-Circuit Programming facility consists of internal hardware resources to facilitate remote programming of the P89LPC901/902/903 through a two-wire serial interface. The Philips In-Circuit Programming facility has made in-circuit programming in an embedded application, using commercially available programmers, possible with a minimum of additional expense in components and circuit board area. The ICP function uses ﬁve pins. Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the

Manual

.

P89LPC901/902/903 User’s

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8.26.6 In-application programming

In-Application Programming is performed in the application under the control of the microcontroller’s ﬁrmware. The IAP facility consists of internal hardware resources to facilitate programming and erasing. The Philips In-Application Programming has made in-application programming in an embedded application possible without additional components. This is accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the

8.26.7 Using ﬂash as data storage

The Flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.

8.26.8 User conﬁguration bytes

Some user-conﬁgurable features of the P89LPC901/902/903 must be deﬁned at power-up and therefore cannot be set by the program after start of execution. These features are conﬁgured through the use of the Flash byte UCFG1. Please see the

P89LPC901/902/903 User’s Manual

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903 User’s Manual

for additional details.

.

8.26.9 User sector security bytes

There are four User Sector Security Bytes, each corresponding to one sector. Please see the

P89LPC901/902/903 User’s Manual

for additional details.

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Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

9. Limiting values

Table 12: Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

T

amb(bias)

T

stg

V

xtal

V

n

I

OH(I/O)

I

OL(I/O)

I

I/O(tot)(max)

P

tot(pack)

[1] Stresses above those listed under Table 12 “Limiting values” may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any conditions other than those described in Table 13 “DC electrical characteristics” and Table 14 “AC characteristics” section of this speciﬁcation are not implied.

[2] This product includes circuitry speciﬁcally designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.

[3] Parametersare valid over operating temperature range unless otherwise speciﬁed. All voltages are with respect to VSSunless otherwise

noted.

operating bias ambient temperature −55 +125 °C storage temperature range −65 +150 °C voltage on XTAL1, XTAL2 pin to VSS,

-V

+ 0.5 V

DD

as applicable voltage on any other pin to V

SS

−0.5 +5.5 V HIGH-level output current per I/O pin - 8 mA LOW-level output current per I/O pin - 20 mA maximum total I/O current - 120 mA total power dissipation per package based on package heat

- 1.5 W

transfer, not device power consumption

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Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

10. Static characteristics

Table 13: DC electrical characteristics

VDD= 2.4 V to 3.6 V unless otherwise speciﬁed.

=−40°C to +85°C for industrial, unless otherwise speciﬁed.

T

amb

Symbol Parameter Conditions Min Typ

I

DD

I

ID

I

DD

I

ID

I

PD

I

PD1

V V V V V

V

V V

V

C I

IL

I

LI

I

TL

R

DDR DDF POR RAM th(HL)

th(LH)

hys OL

OH

io

RST

power supply current,

3.6 V; 12 MHz

operating (P89LPC901) power supply current, Idle

3.6 V; 12 MHz

mode (P89LPC901) power supply current,

3.6 V; 7.373 MHz operating (P89LPC902, P89LPC903)

power supply current, Idle

3.6 V; 7.373 MHz mode (P89LPC902, P89LPC903)

Power supply current,

3.6 V Power-down mode, voltage comparators powered-down

Power supply current, Total

3.6 V Power-down mode

VDD rise time - - 2 mV/µs VDD fall time - - 50 mV/µs Power-on reset detect voltage - - 0.2 V RAM keep-alive voltage 1.5 - - V negative-going threshold

voltage (Schmitt input) positive-going threshold

voltage (Schmitt input) hysteresis voltage - 0.2V LOW-level output voltage; all

ports, all modes except Hi-Z

HIGH-level output voltage, all ports

IOL= 20 mA - 0.6 1.0 V

= 10 mA - 0.3 0.5 V

I

OL

= 3.2 mA - 0.2 0.3 V

I

OL

IOH= −8 mA; push-pull mode

I

= −3.2 mA;

OH

push-pull mode I

= −20 µA;

OH

quasi-bidirectional mode input/output pin capacitance logical 0 input current,

VIN= 0.4 V all ports

input leakage current, all ports VIN=VILor V logical 1-to-0 transition

current, all ports

VIN= 2.0 V at

= 3.6 V

V

DD

IH

internal reset pull-up resistor 10 - 30 kΩ

[7]

[8]

[7][8]

[6] [5]

[4] [2][3]

-1118mA

-14mA

- 7 <t.b.d.> mA

- 1 <t.b.d.> mA

- - <t.b.d.> µA

-15µA

0.22V

DD

0.4V

- 0.6V

VDD− TBD - - V

VDD− 0.7 VDD− 0.4 - V

VDD− 0.3 VDD− 0.2 - V

- - 15 pF

--−80 µA

--±10 µA

−30 - −450 µA

[1]

DD

Max Unit

-V

0.7V

DD

V

-V

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Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Table 13: DC electrical characteristics

…continued

VDD= 2.4 V to 3.6 V unless otherwise speciﬁed.

=−40°C to +85°C for industrial, unless otherwise speciﬁed.

T

amb

Symbol Parameter Conditions Min Typ

V

BO

brownout trip voltage with

2.4 V < VDD< 3.6 V 2.40 - 2.70 V

[1]

Max Unit

BOV = ‘1’, BOPD = ‘0’

V

REF

TC

(VREF)

[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V. [2] Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups) [3] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from ‘1’ to ‘0’. This current is highest

when VIN is approximately 2 V. [4] Measured with port in high-impedance mode. [5] Measured with port in quasi-bidirectional mode. [6] Pin capacitance is characterized but not tested. [7] The IDD, IPD speciﬁcations are measured using an external clock with the following functions disabled: comparators, brownout detect,

and Watchdog timer (P89LPC901). [8] The IDD, IPD speciﬁcations are measured with the following functions disabled: comparators, brownout detect, and Watchdog timer

(P89LPC902, P89LPC903).

bandgap reference voltage 1.11 1.23 1.34 V bandgap temperature

- 10 20 ppm/

coefﬁcient

°C

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Product data Rev. 04 — 21 November 2003 45 of 55

Philips Semiconductors

11. Dynamic characteristics

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Table 14: AC characteristics

T

=−40°C to +85°C for industrial, unless otherwise speciﬁed.

amb

[1]

Symbol Parameter Conditions Variable clock f

Min Max Min Max

f

RCOSC

internal RC oscillator frequency

7.189 7.557 7.189 7.557 MHz

(nominal f = 7.3728 MHz) trimmed

amb

=25°C

280 480 280 480 kHz

f

WDOSC

to ± 1% at T internal Watchdog oscillator

frequency (nominal f = 400 kHz)

Crystal oscillator (P89LPC901)

f

OSC

t

CLCL

f

CLKP

oscillator frequency 0 12 - - MHz clock cycle see Figure 22 83- --ns CLKLP active frequency 0 8 - - MHz

Glitch ﬁlter

glitch rejection, P1.5/ signal acceptance, P1.5/ glitch rejection, any pin except

RST

P1.5/ signal acceptance, any pin except

P1.5/

RST

RST pin - 50 - 50 ns

RST pin 125 - 125 - ns

- 15 - 15 ns

50 - 50 - ns

External clock (P89LPC901)

t

CHCX

t

CLCX

t

CLCH

t

CHCL

HIGH time see Figure 22 33 t LOW time see Figure 22 33 t

CLCL CLCL

− t

CLCX CHCX

rise time see Figure 22 -8 -8ns fall time see Figure 22 -8 -8ns

Shift register (UART mode 0 - P89LPC903)

t

XLXL

t

QVXH

serial port clock cycle time see Figure 21 16 t output data set-up to clock rising

see Figure 21 13 t

- 1333 - ns

CLCL

- 1083 - ns

CLCL

edge

t

XHQX

output data hold after clock rising

see Figure 21 -t

+ 20 - 103 ns

CLCL

edge

t

XHDX

input data hold after clock rising

see Figure 21 -0 -0ns

edge

t

DVXH

input data valid to clock rising edge see Figure 21 150 - 150 - ns

=12MHz Unit

OSC

33 - ns 33 - ns

[1] Parameters are valid over operating temperature range unless otherwise speciﬁed. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.

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Philips Semiconductors

Clock

t

Output Data

Write to SBUF

Input Data

Clear RI

Fig 21. Shift register mode timing.

QVXH

t

XHDV

V

- 0.5 V

DD

0.45 V

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

t

XLXL

t

XHQX

01234567

t

XHDX

Valid Valid Valid Valid Valid Valid Valid Valid

0.2 V

+ 0.9

DD

0.2 V

- 0.1 V

DD

t

CHCL

t

CLCX

t

C

t

CHCX

t

CLCH

002aaa416

Set TI

Set RI

002aaa425

Fig 22. External clock timing.

12. Comparator electrical characteristics

Table 15: Comparator electrical characteristics

VDD= 2.4 V to 3.6 V, unless otherwise speciﬁed.

=−40°C to +85°C for industrial, unless otherwise speciﬁed.

T

amb

Symbol Parameter Conditions Min Typ Max Unit

V

IO

V

CR

CMRR common mode rejection ratio

I

IL

[1] This parameter is characterized, but not tested in production.

offset voltage comparator inputs - - ±20 mV common mode range comparator inputs 0 - VDD− 0.3 V

[1]

--−50 dB response time - 250 500 ns comparator enable to output valid - - 10 µs input leakage current, comparator 0 < VIN<V

DD

--±10 µA

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Product data Rev. 04 — 21 November 2003 47 of 55

Philips Semiconductors

13. Package outline

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

SO8: plastic small outline package; 8 leads; body width 3.9 mm

D

c

y

Z

8

pin 1 index

1

e

5

A

2

A

4

w M

b

p

SOT96-1

E

H

E

1

L

detail X

A

X

v M

A

Q

(A )

L

p

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

OUTLINE

VERSION

SOT96-1

A

A1A2A3b

max.

0.25

1.75

0.10

0.010

0.069

0.004

p

1.45

1.25

0.057

0.049

IEC JEDEC JEITA

076E03 MS-012

0.25

0.01

0.49

0.36

0.019

0.014

0.25

0.19

0.0100

0.0075

UNIT

inches

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

(1)E(2)

cD

5.0

4.8

0.20

0.19

REFERENCES

eHELLpQZywv θ

4.0

3.8

0.16

0.15

1.27

0.05

6.2

5.8

0.244

0.228

1.05

1.0

0.4

0.039

0.016

0.7

0.6

0.028

0.024

0.25 0.10.25

0.010.010.041 0.004

EUROPEAN

PROJECTION

(1)

0.7

0.3

0.028

0.012

ISSUE DATE

99-12-27 03-02-18

o

8

o

0

Fig 23. SOT96-1

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Product data Rev. 04 — 21 November 2003 48 of 55

Philips Semiconductors

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

DIP8: plastic dual in-line package; 8 leads (300 mil)

D

seating plane

A

L

Z

e

b

8

pin 1 index

1

w M

b

1

b

2

5

SOT97-1

M

E

A

2

A

c

(e )

1

M

H

E

1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

UNIT

max.

mm

inches

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

OUTLINE VERSION

SOT97-1

12

min.

max.

050G01 MO-001 SC-504-8

b

1.73

1.14

0.068

0.045

IEC JEDEC JEITA

b

0.53

0.38

0.021

0.015

4

0 5 10 mm

scale

1

0.042

0.035

b

2

0.36

1.07

0.23

0.89

0.014

0.009

REFERENCES

(1) (1)

cD E e M

9.8

9.2

0.39

0.36

6.48

6.20

0.26

0.24

L

e

1

M

3.60

8.25

3.05

7.80

0.14

0.32

0.12

0.31

EUROPEAN

PROJECTION

E

10.0

0.39

0.33

H

8.3

w

max.

0.2542.54 7.62

0.010.1 0.3

0.0450.17 0.02 0.13

ISSUE DATE

99-12-27 03-02-13

1.154.2 0.51 3.2

(1)

Z

Fig 24. SOT97-1

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Product data Rev. 04 — 21 November 2003 49 of 55

Philips Semiconductors

14. Soldering

14.1 Introduction

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our

Packages

There is no soldering method that is ideal for all IC packages. Wavesoldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch SMDs. In these situations reﬂow soldering is recommended. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing.

14.2 Through-hole mount packages

14.2.1 Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Data Handbook IC26; Integrated Circuit

(document order number 9398 652 90011).

The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the

plastic body must not exceed the speciﬁed maximum storage temperature (T If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

14.2.2 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.

14.3 Surface mount packages

14.3.1 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.

stg(max)

).

Typical reﬂow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all the BGA and SSOP-T packages

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Philips Semiconductors

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) forpackageswith

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

14.3.2 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally developed.

If wave soldering is used the following conditions must be observed for optimal results:

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

– for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called

thick/large packages.

a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.

• Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most applications.

14.3.3 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

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Product data Rev. 04 — 21 November 2003 51 of 55

Philips Semiconductors

14.4 Package related soldering information

Table 16: Suitability of IC packages for wave, reﬂow and dipping soldering methods

Mounting Package

Through-hole mount

Through-holesurface mount

Surface mount BGA, LBGA, LFBGA,

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

[1]

DBS, DIP, HDIP, RDBS, SDIP, SIL

[4]

PMFP

[5]

SQFP, SSOP-T

,

TFBGA, VFBGA DHVQFN, HBCC, HBGA,

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS

[7]

PLCC

, SO, SOJ suitable suitable − LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO,

VSSOP

Soldering method Wave Reﬂow

suitable

[3]

not suitable νοτ

not suitable suitable −

not suitable

[6]

not recommended

− suitable

συιταβλε

suitable −

[7][8]

suitable −

[9]

suitable −

[2]

Dipping

−

[1] For more detailed information on the BGA packages refer to the

(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the

Circuit Packages; Section: Packing Methods

[3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the

printed-circuit board. [4] Hot bar soldering or manual soldering is suitable for PMFP packages. [5] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must

on no account be processed through more than one soldering cycle or subjected to infrared reﬂow

soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow

oven. The package body peak temperature must be kept as low as possible. [6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom

side, the solder cannot penetrate betweenthe printed-circuit board and the heatsink. On versions with

the heatsink on the top side, the solder might be deposited on the heatsink surface. [7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners. [8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it

is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65mm. [9] Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5mm.

.

(LF)BGA Application Note

Data Handbook IC26; Integrated

9397 750 12293

Product data Rev. 04 — 21 November 2003 52 of 55

Philips Semiconductors

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903

15. Revision history

Table 17: Revision history

Rev Date CPCN Description

04 20031121 - Product data (9397 750 12293); ECN 853-2434 01-A14555 of 18 November 2003

Modiﬁcations:

• Changed CIN to CIN1A throughout document.

• Changed CMP to CMP1 throughout document.

• Figure 1 “P89LPC901 block diagram.” on page 4; adjusted drawing.

• Figure 2 “P89LPC902 block diagram.” on page 5; adjusted drawing.

• Figure 3 “P89LPC903 block diagram.” on page 6; adjusted drawing.

• Table 5 “P89LPC903 pin description” on page 11; changed CIN to CIN1A.

• Table 8 “P89LPC902 Special function registers” on page 18; removed ENCLK

• Table 9 “P89LPC903 Special function registers” on page 21; removed ENCLK

• Figure 19 “Comparator input and output connections.” on page 38; adjusted drawing.

• Table 13 “DC electrical characteristics” on page 44; changed I

2.0 V.

03 20030929 - Product data (9397 750 12031); ECN 853-2434 30348 of 11 September 2003 02 20030731 - Product data (9397 750 11801); ECN 853-2434 30152 of 28 July 2003 01 20030602 - Preliminary data (9397 750 11494)

value from 1.5 V to

TL VIN

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Product data Rev. 04 — 21 November 2003 53 of 55

Philips Semiconductors

16. Data sheet status

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Level Data sheet status

I Objective data Development This data sheet contains data from the objective speciﬁcation for product development. Philips

II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

III Product data Production This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

[1]

Product status

17. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values deﬁnition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation.

[2][3]

Deﬁnition

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to improve the design and supply the best possible product.

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

18. Disclaimers

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speciﬁed.

Contact information

For additional information, please visit http://www.semiconductors.philips.com. For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. Fax: +31 40 27 24825

9397 750 12293

Product data Rev. 04 — 21 November 2003 54 of 55

Philips Semiconductors

Contents

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 3

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 3

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 7

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8

6 Logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . 12

7 Special function registers. . . . . . . . . . . . . . . . 14

8 Functional description . . . . . . . . . . . . . . . . . . 24

8.1 Enhanced CPU. . . . . . . . . . . . . . . . . . . . . . . . 24

8.2 Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.3 On-chip RC oscillator option. . . . . . . . . . . . . . 25

8.4 Watchdog oscillator option . . . . . . . . . . . . . . . 25

8.5 External clock input option (P89LPC901). . . . 25

8.6 CPU CLock (CCLK) wake-up delay . . . . . . . . 27

8.7 CPU CLOCK (CCLK) modiﬁcation: DIVM

register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.8 Low power select . . . . . . . . . . . . . . . . . . . . . . 27

8.9 Memory organization . . . . . . . . . . . . . . . . . . . 27

8.10 Data RAM arrangement . . . . . . . . . . . . . . . . . 27

8.11 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.12 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.13 Power monitoring functions. . . . . . . . . . . . . . . 32

8.14 Power reduction modes . . . . . . . . . . . . . . . . . 32

8.15 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

8.16 Timers/counters 0 and 1. . . . . . . . . . . . . . . . . 34

8.17 Real-Time clock/system timer. . . . . . . . . . . . . 35

8.18 UART (P89LPC903) . . . . . . . . . . . . . . . . . . . . 35

8.19 Analog comparators . . . . . . . . . . . . . . . . . . . . 37

8.20 Internal reference voltage. . . . . . . . . . . . . . . . 38

8.21 Comparator interrupt. . . . . . . . . . . . . . . . . . . . 38

8.22 Comparator and power reduction modes . . . . 38

8.23 Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . 39

8.24 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 39

8.25 Additional features . . . . . . . . . . . . . . . . . . . . . 40

8.26 Flash program memory. . . . . . . . . . . . . . . . . . 40

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 43

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 44

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 46

12 Comparator electrical characteristics . . . . . . 47

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 48

14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 50

14.2 Through-hole mount packages . . . . . . . . . . . 50

14.3 Surface mount packages . . . . . . . . . . . . . . . . 50

14.4 Package related soldering information. . . . . . 52

15 Revision history . . . . . . . . . . . . . . . . . . . . . . . 53

16 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 54

17 Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Date of release: 21 November 2003 Document order number: 9397 750 12293

Philips P89LPC901, P89LPC902, P89LPC903 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features

2.1 Principal features

2.2 Additional features

3. Ordering information

3.1 Ordering options

4. Block diagram

5. Pinning information

5.1 Pinning

5.2 Pin description

6. Logic symbols

7. Special function registers

8. Functional description

8.1 Enhanced CPU

8.2 Clocks

8.2.2 CPU clock (OSCCLK)

8.2.3 Low speed oscillator option (P89LPC901)

8.2.4 Medium speed oscillator option (P89LPC901)

8.2.5 High speed oscillator option (P89LPC901)

8.2.6 Clock output (P89LPC901)

8.3 On-chip RC oscillator option

8.4 Watchdog oscillator option

8.5 External clock input option (P89LPC901)

8.6 CPU CLock (CCLK) wake-up delay

8.8 Low power select

8.9 Memory organization

8.10 Data RAM arrangement

8.11 Interrupts

8.11.1 External interrupt inputs

8.12 I/O ports

8.12.7 Additional port features

8.13 Power monitoring functions

8.13.1 Brownout detection

8.13.2 Power-on detection

8.14 Power reduction modes

8.14.1 Idle mode

8.14.2 Power-down mode

8.14.3 Total Power-down mode

8.15 Reset

8.16 Timers/counters 0 and 1

8.17 Real-Time clock/system timer

8.18 UART (P89LPC903)

8.18.5 Baud rate generator and selection

8.18.6 Framing error

8.18.7 Break detect

8.18.8 Double buffering

8.19 Analog comparators

8.20 Internal reference voltage

8.21 Comparator interrupt

8.22 Comparator and power reduction modes

8.23 Keypad interrupt (KBI)

8.24 Watchdog timer

8.25 Additional features

8.25.1 Software reset

8.25.2 Dual data pointers

8.26 Flash program memory

8.26.1 General description

8.26.2 Features

8.26.3 Flash organization

8.26.4 Flash programming and erasing

8.26.5 In-circuit programming (ICP)

8.26.6 In-application programming

8.26.9 User sector security bytes

9. Limiting values

10. Static characteristics

11. Dynamic characteristics

12. Comparator electrical characteristics

13. Package outline

14. Soldering

14.1 Introduction

14.2 Through-hole mount packages

14.2.1 Soldering by dipping or by solder wave

14.2.2 Manual soldering

14.3 Surface mount packages

14.3.2 Wave soldering

14.3.3 Manual soldering