Philips P89LPC901, P89LPC902, P89LPC903 Technical data

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM

Rev. 04 — 21 November 2003 Product data

1. General description

The P89LPC901/902/903 are single-chip microcontrollers in low-cost 8-pin packages, based on a highperformance processorarchitecture that executesinstructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC901/902/903 in order to reduce component count, board space, and system cost.

2. Features

2.1 Principal features

■ 1 kB byte-erasable Flash code memory organized into 256-byte sectors and

16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

■ 128-byte RAM data memory.

■ Two 16-bit counter/timers. (P89LPC901 Timer 0 may be conﬁgured to toggle a

port output upon timer overﬂow or to become a PWM output.)

■ 23-bit system timer that can also be used as a Real-Time clock.

■ Two analog comparators (P89LPC902 and P89LPC903, single analog

comparator on P89LPC901).

■ Enhanced UART with fractional baudrate generator, break detect, framing error

detection, automatic address detection and versatile interrupt capabilities (P89LPC903).

■ High-accuracy internal RC oscillator option allows operation without external

oscillator components. The RC oscillator option is selectable and ﬁne tunable.

■ 2.4 V to 3.6 V VDDoperating range with 5 V tolerant I/O pins (may be pulled up or

driven to 5.5 V). Industry-standard pinout with VDD, VSS, and reset at locations 1, 8, and 4.

■ Up to six I/O pins when using internal oscillator and reset options.

■ 8-pin SO-8 package.

2.2 Additional features

■ A high performance 80C51 CPU provides instruction cycle times of 167 ns to

333 ns for all instructions except multiply and divide when executing at 12 MHz. This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.

■ In-Application Programming (IAP-Lite) and byte erase allows code memory to be

used for non-volatile data storage.

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■ Serial Flash In-Circuit Programming (ICP) allows simple production coding with

■ Watchdog timer with separate on-chip oscillator, requiring no external

■ Low voltage reset (Brownout detect) allows a graceful system shutdown when

■ Idle and two different Power-downreduced power modes. Improved wake-up from

■ Active-LOWreset. On-chippower-on reset allows operation without external reset

■ Conﬁgurable on-chip oscillator with frequency range options selected by user

■ Watchdog timer with separate on-chip oscillator, requiring no external

■ Programmable port output conﬁguration options: quasi-bidirectional, open drain,

■ Port ‘input pattern match’ detect. Port 0may generate aninterrupt when thevalue

■ LED drive capability (20 mA) on all port pins. A maximum limit is speciﬁed for the

■ Controlled slew rate port outputs to reduce EMI. Outputs have approximately

■ Only power and ground connections are required to operate the

■ Four interrupt priority levels.

■ Two (P89LPC901), three (P89LPC903), or ﬁve (P89LPC902) keypad interrupt

■ Second data pointer.

■ Schmitt trigger port inputs.

■ Emulation support.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

commercial EPROMprogrammers.Flash security bits prevent reading of sensitive application programs.

components. The watchdog prescaler is selectable from 8 values.

power fails. May optionally be conﬁgured as an interrupt.

Power-down mode (a low interrupt input starts execution). Typical Power-down current is 1 µA (total Power-down with voltage comparators disabled).

components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.

programmed Flash conﬁguration bits. Oscillatoroptions support frequencies from 20 kHz to the maximum operating frequency of 12 MHz (P89LPC901).

components. The watchdog prescaler is selectable from 8 values.

push-pull, input-only.

of the pins match or do not match a programmable pattern.

entire chip.

10 ns minimum ramp times.

P89LPC901/902/903 when internal reset option is selected.

inputs.

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3. Ordering information

Table 1: Ordering information

Type number Package

P89LPC901FD SO8 plastic small outline package; 8 leads; P89LPC902FD P89LPC903FD P89LPC901FN DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 P89LPC902FN

3.1 Ordering options

Table 2: Part options

Type number Temperature range Frequency

P89LPC901xx −40 °Cto+85°C 0 to 12 MHz P89LPC902xx Internal RC or watchdog P89LPC903xx Internal RC or watchdog

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Name Description Version

SOT96-1

body width 7.5 mm

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4. Block diagram

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

CRYSTAL

OR

RESONATOR

P89LPC901

1 kB

CODE FLASH

128-BYTE

DATA RAM

PORT 3

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

CONFIGURABLE

OSCILLATOR

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

INTERNAL BUS

CPU CLOCK

ON-CHIP

RC

OSCILLATOR

TIMER 0 TIMER 1

REAL-TIME CLOCK/

SYSTEM TIMER

ANALOG

COMPARATOR

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

002aaa444

Fig 1. P89LPC901 block diagram.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

P89LPC902

CODE FLASH

128-BYTE

DATA RAM

PORT 1

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

ON-CHIP

OSCILLATOR

1 kB

INPUT

RC

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

INTERNAL

BUS

CPU CLOCK

TIMER 0 TIMER 1

REAL-TIME CLOCK/

SYSTEM TIMER

ANALOG

COMPARATORS

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

002aaa445

Fig 2. P89LPC902 block diagram.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

P89LPC903

1 kB

CODE FLASH

128-BYTE

DATA RAM

PORT 1

INPUT

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

ON-CHIP

RC

OSCILLATOR

HIGH PERFORMANCE

ACCELERATED 2-CLOCK 80C51 CPU

INTERNAL

BUS

CPU CLOCK

UART

TIMER 0 TIMER 1

REAL-TIME CLOCK/

SYSTEM TIMER

ANALOG

COMPARATORS

POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)

002aaa446

Fig 3. P89LPC903 block diagram.

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Philips Semiconductors

5. Pinning information

5.1 Pinning

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

handbook, halfpage

Fig 4. P89LPC901 pinning (SO8).

handbook, halfpage

CLKOUT/XTAL2/P3.0

Fig 5. P89LPC901 pinning (DIP8).

handbook, halfpage

V

DD

XTAL1/P3.1

CLKOUT/XTAL2/P3.0

RST/P1.5

V

DD

XTAL1/P3.1

RST/P1.5

V

DD

P0.2/CIN2A/KBI2

P0.0/CMP2/KBI0

RST/P1.5

1 2 3 4

P89LPC901FD

002aaa438

P89LPC901FN

002aaa469

P89LPC902FD

002aaa439

V

8

SS

P0.4/CIN1A/KBI4

7

P0.5/CMPREF/KBI5

6

P1.2/T0

5

V

8

SS

P0.4/CIN1A/KBI4

7

P0.5/CMPREF/KBI5

6

P1.2/T0

5

V

8

SS

7

P0.4/CIN1A/KBI4

6

P0.5/CMPREF/KBI5

5

P0.6/CMP1/KBI6

Fig 6. P89LPC902 pinning (SO8).

handbook, halfpage

P0.2/CIN2A/KBI2

P0.0/CMP2/KBI0

V

DD

RST/P1.5

1 2 3 4

P89LPC902FN

002aaa470

V

8

SS

7

P0.4/CIN1A/KBI4

6

P0.5/CMPREF/KBI5 P0.6/CMP1/KBI6

5

Fig 7. P89LPC902 pinning (DIP8).

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

handbook, halfpage

P0.2/CIN2A/KBI2

V

DD

P1.1/RxD RST/P1.5

1 2 3 4

P89LPC903FD

002aaa440

V

8

SS

P0.4/CIN1A/KBI4

7

P0.5/CMPREF/KBI5

6

P1.0/TxD

5

Fig 8. P89LPC903 pinning (SO8).

5.2 Pin description

Table 3: P89LPC901 pin description

Symbol Pin Type Description

P0.0 - P0.6 6, 7 I/O Port 0: Port 0 isan I/O port with a user-conﬁgurable output type. During reset Port 0

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port

conﬁgurations” and Table 13 “DC electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

7 I/O P0.4 — Port 0 bit 4.

I CIN1A — Comparator 1 positive input. I KBI4 — Keyboard input 4.

6 I/O P0.5 — Port 0 bit 5.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5.

P1.0 - P1.5 4, 5 Port 1: Port 1 is an I/O port with a user-conﬁgurable output type. During resetPort 1

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the port conﬁguration selected. Each of the conﬁgurable port pins are programmed independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “DC

electrical characteristics” for details. P1.5 is input only.

All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

5 I/O P1.2 — Port 1 bit 2.

O T0 — Timer/counter 0 external count input or overﬂow output.

4IP1.5 — Port 1 bit 5 (input only).

I

RST — External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input aLOW on this pin resetsthe microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Table 3: P89LPC901 pin description

Symbol Pin Type Description

P3.0 - P3.1 2, 3 I/O Port 3: Port 3 is an I/O port with a user-conﬁgurableoutput types. During reset Port 3

3 I/O P3.0 — Port 3 bit 0.

O XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is

O CLKOUT — CPU clock divided by 2 when enabled via SFR bit(ENCLK -TRIM.6). It

2 I/O P3.1 — Port 3 bit 1.

I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

V

SS

V

DD

8IGround: 0 V reference. 1IPower Supply: This is the power supply voltage for normal operation as well as Idle

…continued

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of port 3 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port

conﬁgurations” and Table 13 “DC electrical characteristics” for details.

All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below:

selected via the FLASH conﬁguration).

can be used if the CPU clock is the internal RC oscillator, Watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the real time clock/system timer.

selected via the FLASH conﬁguration).It can be a port pin if internal RC oscillator or Watchdog oscillator is used as the CPU clock source,and if XTAL1/XTAL2 are not used to generate the clock for the real time clock/system timer.

and Power-down modes.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Table 4: P89LPC902 pin description

Symbol Pin Type Description

P0.0 - P0.6 2, 3, 5, 6,7I/O Port 0: Port 0 is an I/O port with a user-conﬁgurable output type. During reset Port 0

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port

conﬁgurations” and Table 13 “DC electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

3 I/O P0.0 — Port 0 bit 0.

I CMP2 — Comparator 2 output. I KBI0 — Keyboard input 0.

2 I/O P0.2 — Port 0 bit 2.

I CIN2A — Comparator 2 positive input. I KBI2 — Keyboard input 2.

7 I/O P0.4 — Port 0 bit 4.

I CIN1A — Comparator 1 positive input. I KBI4 — Keyboard input 4.

6 I/O P0.5 — Port 0 bit 5.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5.

5 I/O P0.6 — Port 0 bit 6.

O CMP1 — Comparator 1 output. I KBI6 — Keyboard input 6.

P1.0 - P1.5 4 Port 1: Port 1 is an I/O port with a user-conﬁgurable output type. During reset Port 1

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the port conﬁguration selected. Each of the conﬁgurable port pins are programmed independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “DC

electrical characteristics” for details. P1.5 is input only.

All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

4IP1.5 — Port 1 bit 5 (input only).

I

V

SS

V

DD

8IGround: 0 V reference. 1IPower Supply: This is the power supply voltage for normal operation as well as Idle

RST — External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

and Power-down modes.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Table 5: P89LPC903 pin description

Symbol Pin Type Description

P0.0 - P0.6 2, 6, 7 I/O Port 0: Port 0 is an I/O port with a user-conﬁgurable output type. During reset Port 0

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port conﬁguration selected. Each port pin is conﬁgured independently. Refer to Section 8.12.1 “Port

conﬁgurations” and Table 13 “DC electrical characteristics” for details.

The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:

2 I/O P0.2 — Port 0 bit 2.

I CIN2A — Comparator 2 positive input. I KBI2 — Keyboard input 2.

7 I/O P0.4 — Port 0 bit 4.

I CIN1A — Comparator 1 positive input. I KBI4 — Keyboard input 4.

6 I/O P0.5 — Port 0 bit 5.

I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5.

P1.0 - P1.5 3, 4, 5 Port 1: Port 1 is an I/O port with a user-conﬁgurable output type. During reset Port 1

latches are conﬁgured in the input only mode with the internal pull-up disabled. The operation of the conﬁgurable Port 1 pins as inputs and outputs depends upon the port conﬁguration selected. Each of the conﬁgurable port pins are programmed independently. Refer to Section 8.12.1 “Port conﬁgurations” and Table 13 “DC

electrical characteristics” for details. P1.5 is input only.

All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:

5 I/O P1.0 — Port 1 bit 0.

O TxD — Serial port transmitter data.

3 I/O P1.1 — Port 1 bit 1.

I RxD — Serial port receiver data.

4IP1.5 — Port 1 bit 5 (input only).

I

V

SS

V

DD

8IGround: 0 V reference. 1IPower Supply: This is the power supply voltage for normal operation as well as Idle

RST — External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force In-System Programming mode.

and Power-down modes.

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6. Logic symbols

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

V

DDVSS

KBI4 KBI5

CLKOUT

Fig 9. P89LPC901 logic symbol.

KBI4 KBI5 KBI6 KBI2 KBI0

Fig 10. P89LPC902 logic symbol.

CIN1A

CMPREF

XTAL2 XTAL1

CIN1A

CMPREF

CMP1

CIN2A

CMP2

PORT 0

PORT 3

VDDV

P89LPC901

002aaa441

SS

P89LPC902

002aaa442

PORT 1

RST

RST T0

VDDV

SS

KBI4 KBI5 KBI2

CIN1A

CMPREF

CIN2A

PORT 0

PORT 1

RST RxD TxD

P89LPC903

002aaa443

Fig 11. P89LPC903 logic symbol.

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P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

Table 6 highlights the differences between these three devices. For a complete list of

device features, please see Section 2 “Features” on page 1.

Table 6: Product comparison overview

Type number External

crystal pins

P89LPC901xx X X X - - - P89LPC902xx - - - X X - P89LPC903xx - - - X - X X

CLKOUT output T0 PWM output CMP2 input CMP1 and

CMP2 outputs

UART TxD Rxd

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7. Special function registers

Remark: Special Function Registers (SFRs) accesses are restricted in the following

ways:

• User must not attempt to access any SFR locations not deﬁned.

• Accesses to any deﬁned SFR locations must be strictly for the functions for the

SFRs.

• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise speciﬁed, must be written with ‘0’, but can return any value

when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read. – ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

P89LPC901/902/903

8-bit microcontrollers with two-clock 80C51 core

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Product data Rev. 04 — 21 November 2003 14 of 55

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Table 7: P89LPC901 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

ACC* Accumulator E0H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP - - ENT0 SRST 0 - DPS 00

B* B register F0H 00 00000000 CMP1 Comparator 1 control register ACH - - CE1 - CN1 - CO1 CMF1 00 DIVM CPU clock divide-by-M

DPTR Data pointer (2 bytes)

DPH Data pointer HIGH 83H 00 00000000

DPL Data pointer LOW 82H 00 00000000 FMADRH Program Flash address HIGH E7H 00 00000000 FMADRL Program Flash address LOW E6H 00 00000000 FMCON Program Flash Control

FMDATA Program Flash data E5H 00 00000000 IEN0* Interrupt enable 0 A8H EA EWDRT EBO - ET1 - ET0 - 00 00000000

IEN1* Interrupt enable 1 E8H -----ECEKBI - 00

IP0* Interrupt priority 0 B8H - PWDRT PBO - PT1 - PT0 - 00 IP0H Interrupt priority 0 HIGH B7H - PWDRTHPBOH - PT1H - PT0H - 00

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

addr.

Bit address E7 E6 E5 E4 E3 E2 E1 E0

Bit address F7 F6 F5 F4 F3 F2 F1 F0

95H 00 00000000

control

E4H BUSY - - - HVA HVE SV OI 70 01110000

(Read) Program Flash Control

(Write)

Bit address EF EE ED EC EB EA E9 E8

Bit address BF BE BD BC BB BA B9 B8

MSB LSB Hex Binary

FMCMD.7FMCMD.6FMCMD.5FMCMD.4FMCMD.3FMCMD.2FMCMD.1FMCMD.

Bit functions and addresses Reset value

[1]

0

[1]

[1] [1]

Philips Semiconductors

000000x0

xx000000

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903

00x00000

x0000000 x0000000

Bit address FF FE FD FC FB FA F9 F8

IP1* Interrupt priority 1 F8H -----PCPKBI - 00 IP1H Interrupt priority 1 HIGH F7H -----PCHPKBIH - 00 KBCON Keypad control register 94H ------PATN

KBIF 00

_SEL

[1] [1] [1]

00x00000 00x00000 xxxxxx00

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Table 7: P89LPC901 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

KBMASK Keypad interrupt mask

KBPATN Keypad pattern register 93H FF 11111111

P0* Port 0 80H - - CMPREF

P1* Port 1 90H - -

P3*Port3 B0H------XTAL1XTAL2 P0M1 Port 0 output mode 1 84H - - (P0M1.5) (P0M1.4) ----FF11111111 P0M2 Port 0 output mode 2 85H - - (P0M2.5) (P0M2.4) ----0000000000 P1M1 Port 1 output mode 1 91H - - (P1M1.5) - - (P1M1.2) - - FF P1M2 Port 1 output mode 2 92H - - (P1M2.5) - - (P1M2.2) - - 00 P3M1 Port 3 output mode 1 B1H ------(P3M1.1) (P3M1.0) 03 P3M2 Port 3 output mode 2 B2H ------(P3M2.1) (P3M2.0) 00 PCON Power control register 87H - - BOPD BOI GF1 GF0 PMOD1 PMOD0 00 00000000 PCONA Power control register A B5H RTCPD VCPD - - 00 PCONB reserved for Power Control

PSW* Program status word D0H CY AC F0 RS1 RS0 OV F1 P 00 00000000 PT0AD Port 0 digital input disable F6H - - PT0AD.5 PT0AD.4 ----00xx00000x RSTSRC Reset source register DFH - - BOF POF - R_WD R_SF R_EX RTCCON Real-time clock control D1H RTCF RTCS1 RTCS0 - - - ERTC RTCEN 60

RTCH Real-time clock register HIGH D2H 00 RTCL Real-time clock register LOW D3H 00 SP Stack pointer 81H 07 00000111 TAMOD Timer 0 auxiliary mode 8FH -------T0M2 00 xxx0xxx0

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

…continued

addr.

86H 00 00000000

register

Bit address 87 86 85 84 83 82 81 80

Bit address 97 96 95 94 93 92 91 90

Bit address B7 B6 B5 B4 B3 B2 B1 B0

B6H--------00

Register B

Bit address D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB Hex Binary

Bit functions and addresses Reset value

[1]

[3]

[6]

/KB5

CIN1A

/KB4

----

RST - - T0 - -

[1] [1] [1] [1]

[1] [1]

[1]

[6] [6]

11111111 00000000 xxxxxx11 xxxxxx00

00000000 xxxxxxxx

011xxx00

00000000 00000000

Philips Semiconductors

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

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Product data Rev. 04 — 21 November 2003 17 of 55

Table 7: P89LPC901 Special function registers

* indicates SFRs that are bit addressable.

Name Description SFR

TCON* Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 ----0000000000 TH0 Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TL0 Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H - - T1M1 T1M0 - - T0M1 T0M0 00 00000000 TRIM Internal oscillator trim register 96H - - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H

[1] All ports are in input only (high impedance) state after power-up. [2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is ‘0’. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reﬂects the cause of the P89LPC901/902/903 reset. Upon a power-up reset, all reset source ﬂags are cleared except POF and BOF; the power-on reset

[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all ‘1’, WDRUN = 1 and WDCLK = 1. WDTOFbit is ‘1’ after Watchdogreset and is ‘0’ after power-on reset. Other resets will

[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. [6] The only reset source that affects these SFRs is power-on reset.

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…continued

Bit functions and addresses Reset value

addr.

Bit address 8F 8E 8D 8C 8B 8A 89 88

Unimplemented bits in SFRs (labeled ’-’) are X (unknown) at all times. Unless otherwise speciﬁed, ones should not be written to these bits since they may be used for other purposes in future derivatives. The reset values shown for these bits are ‘0’s although they are unknown when read.

value is xx110000.

not affect WDTOF.

MSB LSB Hex Binary

[5] [6] [4] [6]

Philips Semiconductors

8-bit microcontrollers with two-clock 80C51 core

P89LPC901/902/903