INTEGRATED CIRCUITS
DATA SHEET
P89C738; P89C739
8-bit Flash microcontrollers
Product specification |
1998 Apr 07 |
Supersedes data of 1997 Dec 15
File under Integrated Circuits, IC20
Philips Semiconductors |
Product specification |
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8-bit Flash microcontrollers |
P89C738; P89C739 |
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CONTENTS
1FEATURES
2GENERAL DESCRIPTION
3ORDERING INFORMATION
4BLOCK DIAGRAM
5FUNCTIONAL DIAGRAM
6PINNING INFORMATION
6.1Pin configuration
6.2Pin description
7 |
FUNCTIONAL DESCRIPTION |
7.1General
7.2Instruction set execution
8 |
MEMORY ORGANIZATION |
8.1Program memory
8.2Internal data memory
8.3Addressing
9 |
INTERRUPT SYSTEM |
9.1Interrupt Enable Register (IE)
9.2Interrupt Priority Register (IP)
10 TIMERS/COUNTERS
10.1Timer 0 and Timer 1
10.2Timer 2
10.3Watchdog Timer (T3)
11I/O FACILITIES
12FULL DUPLEX SERIAL PORT (UART)
12.1The Serial Port operating modes
12.2Serial Port Control Register (SCON)
13 REDUCED POWER MODES
13.1Idle mode
13.2Power-down mode
13.3Wake-up from Power-down mode
13.4Status of external pins
13.5Power Control Register (PCON)
14 OSCILLATOR CIRCUIT
15 RESET
15.1Power-on reset
16MULTIPLE PROGRAMMING ROM (MTP-ROM)
16.1Features
16.2General description
16.3Automatic programming and Automatic chip erase
16.4Command definitions
16.5Silicon-ID-Read command
16.6Set-up of Automatic chip erase and Automatic erase commands
16.7Set-up of the Automatic program and Program commands
16.8Reset command
16.9Write operation status
16.10Write operation
16.11System considerations
16.12Command programming/data programming and erase operation
17SPECIAL FUNCTION REGISTERS OVERVIEW
18INSTRUCTION SET
19LIMITING VALUES
20DC CHARACTERISTICS
21AC CHARACTERISTICS
21.1Serial Port characteristics
21.2Timing waveforms
21.3Timing symbol naming conventions
22PACKAGE OUTLINES
23SOLDERING
23.1Introduction
23.2DIP
23.3PLCC and QFP
24DEFINITIONS
25LIFE SUPPORT APPLICATIONS
1998 Apr 07 |
2 |
Philips Semiconductors |
Product specification |
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8-bit Flash microcontrollers |
P89C738; P89C739 |
1 FEATURES
∙80C51 CPU
∙64-kbyte on-chip Multiple Programming ROM (MTP-ROM), expandable externally to 64 kbytes program memory address space
∙512-byte on-chip RAM, expandable externally to 64 kbytes data memory address space
∙P89C738 pin outs fully compatible to the standard 8051/8052
∙8-bit I/O ports for P89C738: 4 and P89C739: 6
∙Full-duplex UART compatible with the standard 80C51 and the 8052
∙Two standard 16-bit timers/event counters
∙An additional 16-bit timer (functionally equivalent to the Timer 2 of the 8052)
∙On-chip Watchdog Timer (T3)
∙6-source and 6-vector interrupt structure with 2 priority levels
∙Up to 3 external interrupt request inputs
∙Two programmable power reduction modes: Idle and Power-down
∙Termination of Idle mode by any interrupt, external or Watchdog Timer reset
∙Wake-up from Power-down by external interrupt, external or Watchdog Timer reset
∙Packages,
–P89C738: DIP40, PLCC44 and QFP44
–P89C739: PLCC68 and QFP64
∙Improved Electromagnetic Compatibility (EMC)
3 ORDERING INFORMATION
∙Frequency range: 3.5 to 40 MHz
∙ROM code protection.
2 GENERAL DESCRIPTION
The P89C738 and P89C739 (hereafter generally referred to as P89C738 unless the P89C739 is specifically mentioned) are 8 8-bit Flash microcontrollers manufactured in an advanced CMOS process and is a derivative of the PCB80C51 microcontroller family. This device provides architectural enhancements that make it applicable in a variety of applications in general control systems, especially in those systems which need a large on-chip ROM and RAM capacity.
The P89C738 contains a non-volatile 64-kbyte Multiple Programming ROM (MTP-ROM) program memory, a volatile 512 bytes read/write data memory, four 8-bit I/O ports (six for the P89C739), two 16-bit timer/event counters (identical to the timers of the 80C51), a 16-bit timer (identical to the Timer 2 of the 8052), a multi-source two-priority-level nested interrupt structure, one serial interface (UART), a Watchdog Timer (T3), an on-chip oscillator and timing circuits. For systems that require extra capability, the P89C738 can be expanded using standard TTL compatible memories and logic.
The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The P89C738 has the same instruction set as the PCB80C51 which consists of over 100 instructions: 49 one-byte, 46 two-byte and
16 three-byte. With a 16 MHz crystal, 58% of the instructions are executed in 750 ns and 40% in 1.5 μs. Multiply and divide instructions require 3 μs.
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PACKAGE |
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NUMBER(1) |
NAME |
DESCRIPTION |
VERSION |
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P89C738ABA |
PLCC44 |
plastic leaded chip carrier; 44 leads |
note 2 |
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P89C738ABP |
DIP40 |
plastic dual in-line package; 40 leads (600 mil) |
SOT129-1 |
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P89C738ABB |
QFP44 |
plastic quad flat package; 44 leads |
note 2 |
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P89C739ABA |
PLCC68 |
plastic leaded chip carrier; 68 leads |
note 2 |
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P89C739ABB |
QFP64 |
plastic quad flat package; 64 leads (lead length 1.95 mm); |
SOT319-1 |
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body 14 × 20 × 2.7 mm; high stand-off height |
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Notes |
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1.Temperature and frequency range for all types: 0 to 70 °C and 3.5 to 40 MHz.
2.For more information on the package outline of this version, please contact the Philips Semiconductors Sales office.
1998 Apr 07 |
3 |
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07 Apr 1998 |
T0 (2) |
T1 (2) |
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INT0 (2) |
INT1 (2) |
VDD |
pagewidth full book, |
VSS |
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RXD (2) TXD (2) |
BLOCK 4 |
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internal |
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DIAGRAM |
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interrupts |
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XTAL1 |
TWO 16-BIT |
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PROGRAM |
DATA |
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PROGRAMMABLE |
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SERIAL PORT |
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TIMERS/ |
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MEMORY |
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MEMORY |
FULL DUPLEX |
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EVENT |
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CPU |
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64-kbyte |
256-byte |
256-byte |
UART |
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COUNTERS |
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XTAL2 |
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MTP-ROM |
RAM |
AUX-RAM |
SYNCHRONOUS |
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(T0, T1) |
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SHIFT |
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80C51 core |
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P89C738 |
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excluding |
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P89C739 |
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ROM/RAM |
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8-bit |
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internal bus |
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PARALLEL I/O PORTS |
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16-BIT |
WATCHDOG |
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16 kbytes BUS |
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TIMER/ |
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AND |
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EXPANSION CONTROL |
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TIMER |
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EXTERNAL BUS |
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COUNTER |
(T3) |
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(T2) |
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8 |
8 |
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8 |
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internal |
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reset |
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P0 |
P1 |
P2 |
P3 |
P4(3) |
P5(3) |
PSEN |
ALE/WE |
WR (2) |
T2EX (1) T2 (1) |
RST |
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EA |
RD (2) |
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MGK189 |
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(1)Alternative function for Port 1.
(2)Alternative function for Port 3.
(3)P4 and P5 are only available on the P89C738ABA and P89C739ABB (PLCC68 and QFP64).
Fig.1 Block diagram.
microcontrollers Flash bit-8
P89C739 P89C738;
Semiconductors Philips
specification Product
Philips Semiconductors |
Product specification |
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8-bit Flash microcontrollers |
P89C738; P89C739 |
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5 FUNCTIONAL DIAGRAM |
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handbook, full pagewidth
XTAL1 |
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PORT 0 |
XTAL2 |
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RST |
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EA |
PORT 1 |
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PSEN |
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ALE |
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P89C738 |
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P89C739 |
PORT 5 |
PORT 2 |
PORT 4 |
PORT 3 |
VSS
VDD
ADDRESS
AND
DATA BUS
T2
T2EX
ADDRESS
BUS
RXD
TXD
INT0
INT1 secondary
T0 |
functions |
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T1 |
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WR |
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RD |
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MGK191
Fig.2 Functional diagram.
1998 Apr 07 |
5 |
Philips Semiconductors |
Product specification |
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8-bit Flash microcontrollers |
P89C738; P89C739 |
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6 PINNING INFORMATION
6.1Pin configuration
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P1.4 |
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P1.3 |
P1.2 |
P1.1/T2EX |
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P1.0/T2 |
n.c. |
V |
P0.0/AD0 |
P0.1/AD1 |
P0.2/AD2 |
P0.3/AD3 |
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2 |
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P1.5 |
7 |
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39 |
P0.4/AD4 |
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P1.6 |
8 |
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38 |
P0.5/AD5 |
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P1.7 |
9 |
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37 |
P0.6/AD6 |
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RST |
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36 |
P0.7/AD7 |
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P3.0/RXD/data |
11 |
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35 |
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EA/VPP |
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n.c. |
12 |
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P89C738ABA |
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34 |
n.c. |
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P3.1/TXD/clock |
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33 |
ALE/WE |
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P3.2/INT0 |
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PSEN |
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P3.3/INT1 |
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31 |
P2.7/A15 |
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P3.4/T0 |
16 |
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30 |
P2.6/A14 |
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P3.5/T1 |
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P2.5/A13 |
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P3.7/RD |
XTAL2 |
XTAL1 |
V |
n.c. |
P2.0/A8 |
P2.1/A9 |
P2.2/A10 |
P2.3/A11 |
P2.4/A12 |
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SS |
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MGK185
Fig.3 Pin configuration for PLCC44 package; for more information on the version see Chapter 3.
1998 Apr 07 |
6 |
Philips Semiconductors |
Product specification |
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8-bit Flash microcontrollers |
P89C738; P89C739 |
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P1.0/T2 |
1 |
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VDD |
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P1.1/T2EX |
2 |
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P0.0/AD0 |
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P1.2 |
3 |
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P0.1/AD1 |
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P1.3 |
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P0.2/AD2 |
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P1.4 |
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P0.3/AD3 |
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P1.5 |
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P0.4/AD4 |
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P1.6 |
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P0.5/AD5 |
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P1.7 |
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P0.6/AD6 |
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RST |
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P0.7/AD7 |
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P3.0/RXD/data |
10 |
P89C738ABP |
31 |
EA/VPP |
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P3.1/TXD/clock |
11 |
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30 |
ALE/WE |
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P3.2/INT0 |
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PSEN |
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P3.3/INT1 |
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P2.7/A15 |
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P3.4/T0 |
14 |
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27 |
P2.6/A14 |
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P3.5/T1 |
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26 |
P2.5/A13 |
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P3.6/WR |
16 |
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25 |
P2.4/A12 |
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P3.7/RD |
17 |
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24 |
P2.3/A11 |
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XTAL2 |
18 |
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23 |
P2.2/A10 |
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XTAL1 |
19 |
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22 |
P2.1/A9 |
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VSS |
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21 |
P2.0/A8 |
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MGK184 |
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Fig.4 Pin configuration for DIP40 package (SOT129-1).
1998 Apr 07 |
7 |
Philips Semiconductors |
Product specification |
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8-bit Flash microcontrollers |
P89C738; P89C739 |
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P3.6/WR |
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P3.7/RD |
XTAL2 |
XTAL1 |
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n.c. |
P2.0/A8 |
P2.1/A9 |
P2.2/A10 |
P2.3/A11 |
P2.4/A12 |
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SS |
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44 |
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43 |
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42 |
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41 |
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40 |
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39 |
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38 |
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37 |
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36 |
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35 |
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34 |
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P1.5 |
1 |
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33 |
P0.4/AD4 |
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P1.6 |
2 |
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32 |
P0.5/AD5 |
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P1.7 |
3 |
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31 |
P0.6/AD6 |
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RST |
4 |
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30 |
P0.7/AD7 |
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P3.0/RXD/data |
5 |
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29 |
EA/VPP |
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n.c. |
6 |
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P89C738ABB |
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28 |
n.c. |
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P3.1/TXD/clock |
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7 |
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27 |
ALE/WE |
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P3.2/INT0 |
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8 |
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26 |
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PSEN |
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P3.3/INT1 |
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9 |
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25 |
P2.7/A15 |
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P3.4/T0 |
10 |
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24 |
P2.6/A14 |
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P3.5/T1 |
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P2.5/A13 |
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11 |
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23 |
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12 |
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15 |
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18 |
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20 |
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22 |
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P1.4 |
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P1.3 |
P1.2 |
P1.1/T2EX |
P1.0/T2 |
n.c. |
DD |
P0.0/AD0 |
P0.1/AD1 |
P0.2/AD2 |
P0.3/AD3 |
|||||||||
|
V |
|||||||||||||||||||
MGK186
Fig.5 Pin configuration for QFP44 package; for more information on the version see Chapter 3.
1998 Apr 07 |
8 |
Philips Semiconductors |
Product specification |
|
|
8-bit Flash microcontrollers |
P89C738; P89C739 |
|
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handbook, full pagewidth
P5.5 10 P0.3/AD3 11 P0.2/AD2 12 P5.6 13 P0.1/AD1 14 P0.0/AD0 15 P5.7 16 VDD 17 n.c. 18 P1.0/T2 19 P4.0 20
P1.1/T2EX 21
P1.2 22
P1.3 23
P4.1 24
P1.4 25
P4.2 26
P0.4/AD4 |
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P5.4 |
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P5.3 |
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P0.5/AD5 |
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P0.6/AD6 |
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n.c. |
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P0.7/AD7 |
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EA/V |
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n.c. |
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ALE/WE |
PSEN |
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n.c. |
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P2.7/AD15 |
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P2.6/AD14 |
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P5.2 |
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P5.1 |
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P2.5/AD13 |
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PP |
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9 |
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8 |
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7 |
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6 |
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5 |
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4 |
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3 |
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2 |
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1 |
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68 |
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67 |
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66 |
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65 |
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64 |
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63 |
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62 |
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61 |
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60 |
P5.0 |
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59 |
P2.4/AD12 |
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58 |
P2.3/AD11 |
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57 |
P4.7 |
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56 |
P2.2/AD10 |
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55 |
P2.1/AD9 |
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54 |
P2.0/AD8 |
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53 |
P4.6 |
|||
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P89C739ABA |
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n.c. |
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52 |
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VSS |
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51 |
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50 |
P4.5 |
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49 |
XTAL1 |
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48 |
XTAL2 |
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47 |
P3.7/RD |
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46 |
P4.4 |
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45 |
P3.6/WR |
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44 |
P4.3 |
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27 |
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28 |
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29 |
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30 |
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31 |
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32 |
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33 |
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34 |
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35 |
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36 |
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37 |
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38 |
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39 |
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40 |
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41 |
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42 |
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43 |
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P1.5 |
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P1.6 |
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P1.7 |
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RST |
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n.c. |
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n.c. |
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n.c. |
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P3.0/RXD/data |
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n.c. |
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n.c. |
n.c. |
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n.c. |
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P3.1/TXD/clock |
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P3.2/INT0 |
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P3.3/INT1 |
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P3.4/T0 |
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P3.5/T1 |
MGK187 |
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Fig.6 Pin configuration for PLCC68 package; for more information on the version see Chapter 3.
1998 Apr 07 |
9 |
Philips Semiconductors |
Product specification |
|
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8-bit Flash microcontrollers |
P89C738; P89C739 |
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P0.4/AD4 1 P5.5 2 P0.3/AD3 3 P0.2/AD2 4
P5.6 5
P0.1/AD1 6
P0.0/AD0 7 P5.7 8 VDD 9 VSS 10
P1.0/T2 11
P4.0 12
P1.1/T2EX 13
P1.2 14
P1.3 15
P4.1 16
P1.4 17
P4.2 18
P1.5 19
P5.4 |
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P5.3 |
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P0.5/AD5 |
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P0.6/AD6 |
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P0.7/AD7 |
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EA/V |
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n.c. |
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ALE/WE |
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PSEN |
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P2.7/AD15 |
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P2.6/AD14 |
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P5.2 |
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P5.1 |
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PP |
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64 |
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63 |
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62 |
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61 |
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60 |
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59 |
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58 |
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57 |
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56 |
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55 |
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54 |
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53 |
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52 |
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P89C739ABB
20 |
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21 |
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22 |
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23 |
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24 |
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25 |
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26 |
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27 |
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28 |
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29 |
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30 |
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31 |
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32 |
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P1.6 |
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P1.7 |
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RST |
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n.c. |
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n.c. |
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n.c. |
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P3.0/RXD/data |
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n.c. |
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n.c. |
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P3.1/TXD/clock |
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P3.2/INT0 |
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P3.3/INT1 |
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P3.4/T0 |
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51 |
P2.5/AD13 |
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P5.0 |
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50 |
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P2.4/AD12 |
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49 |
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48 |
P2.3/AD11 |
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47 |
P4.7 |
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46 |
P2.2/AD10 |
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45 |
P2.1/AD9 |
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P2.0/AD8 |
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44 |
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P4.6 |
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43 |
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n.c. |
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42 |
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VSS |
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41 |
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40 |
P4.5 |
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39 |
XTAL1 |
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38 |
XTAL2 |
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37 |
P3.7/RD |
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P4.4 |
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36 |
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35 |
P3.6/WR |
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34 |
P4.3 |
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33 |
P3.5/T1 |
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MGK188 |
|||
Fig.7 Pin configuration for QFP64 package (SOT319-1).
1998 Apr 07 |
10 |
07 Apr 1998
11
_
Table 1 Pin description for DIP40; QFP44; PLC44; QFP64 and PLCC68.
SYMBOL |
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PIN(1) |
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DESCRIPTION |
||||||
PLCC68 |
QFP64 |
PLCC44 |
QFP44 |
DIP40 |
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P1.0/T2 |
19 |
11 |
16 |
2 |
1 |
Port 1: P1.0 to P1.7; 8-bit quasi-bidirectional I/O port. Port 1 can |
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sink/source one TTL (= 4 LSTTL) input. It can drive CMOS inputs |
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P1.1/T2EX |
21 |
13 |
15 |
3 |
2 |
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without external pull-ups. |
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P1.2 |
22 |
14 |
14 |
4 |
3 |
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Port 1 alternative functions are: T2; Timer/event counter 2 external |
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P1.3 |
23 |
15 |
13 |
5 |
4 |
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event counter input (falling edge triggered). T2EX; Timer/event |
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P1.4 |
25 |
17 |
12 |
6 |
5 |
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counter 2 capture/reload trigger or external interrupt 2 input (falling |
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P1.5 |
27 |
19 |
1 |
7 |
6 |
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edge triggered). |
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P1.6 |
28 |
20 |
2 |
8 |
7 |
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P1.7 |
29 |
21 |
3 |
9 |
8 |
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RST |
30 |
22 |
4 |
10 |
9 |
Reset; a HIGH level on this pin for two machine cycles while the |
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oscillator is running, resets the device. An internal pull-down resistor |
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permits power-on reset using only a capacitor connected to VDD. |
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After a Watchdog Timer overflow this pin is pulled HIGH while the |
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internal reset signal is active. |
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P3.0/RXD/data |
34 |
26 |
5 |
11 |
10 |
Port 3: P3.0 to P3.7; 8-bit quasi-bidirectional I/O Port with internal |
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pull-ups. Port 3 can sink/source one TTL (= 4 LSTTL) input. It can |
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P3.1/TXD/clock |
39 |
29 |
7 |
13 |
11 |
|||||||
drive CMOS inputs without external pull-ups. |
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P3.2/INT0 |
40 |
30 |
8 |
14 |
12 |
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Port 3 alternative functions are: RXD/data; Serial Port data input |
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P3.3/INT1 |
41 |
31 |
9 |
15 |
13 |
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(asynchronous) or data input/output (synchronous). |
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P3.4/T0 |
42 |
32 |
10 |
16 |
14 |
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TXD/clock; Serial Port data output (asynchronous) or clock output |
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P3.5/T1 |
43 |
33 |
11 |
17 |
15 |
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(synchronous). INT0; External interrupt 0 or gate control input for |
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45 |
35 |
44 |
18 |
16 |
Timer/event counter 0. INT1; External interrupt 1 or gate control |
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P3.6WR |
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input for Timer/event counter 1. T0; external input for Timer/event |
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P3.7/RD |
47 |
37 |
43 |
19 |
17 |
|||||||
counter 0. T1; external input for Timer/event counter 1. |
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WR; external data memory write strobe. RD; external data memory |
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read strobe. |
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XTAL2 |
48 |
38 |
42 |
20 |
18 |
Crystal input 2: output of the inverting amplifier that forms the |
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oscillator. This pin left open-circuit when an external oscillator clock |
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is used (see Figs 18 and 20). |
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||||||
XTAL1 |
49 |
39 |
41 |
21 |
19 |
Crystal input 1: input to the inverting amplifier that forms the |
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oscillator, and input to the internal clock generator. Receives the |
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external oscillator clock signal when an external oscillator is used |
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(see Figs 18 and 20). |
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||||||
VSS |
51 |
41 |
40 |
22 |
20 |
Ground: circuit ground potential. |
||||||
description Pin 2.6
microcontrollers Flash bit-8
P89C739 P89C738;
Semiconductors Philips
specification Product
1998 |
|
|
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SYMBOL |
|
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PIN(1) |
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DESCRIPTION |
|||||||||
Apr |
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PLCC68 |
QFP64 |
PLCC44 |
QFP44 |
DIP40 |
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P2.0/A8 to |
54 to 56 |
44 to 46 |
38 to 34 |
24 to 31 |
21 to 28 |
|
Port 2: P2.0 to P2.7; 8-bit quasi-bidirectional I/O Port with internal |
||||||||||||||||||
07 |
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||||||||||||||||||||||||
|
P2.2/A10 |
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pull-ups. Port 2 can sink/source one TTL (= 4 LSTTL) input. It can |
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drive CMOS inputs without external pull-ups. |
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P2.3/A11 to |
58 to 59 |
48 to 49 |
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P2.4/A12 |
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Port 2 alternative functions are: A8 to A15; during access to |
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|
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P2.5/A13 to |
61, 64 |
51, 54 |
23 to 25 |
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|
|
external memories (RAM/ROM) that use 16-bit addresses (MOVX |
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|
|
P2.7/A15 |
and 65 |
and 55 |
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@DPTR) Port 2 emits the high-order address byte (A8 to A15). |
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67 |
56 |
26 |
32 |
29 |
|
Program Store Enable output: read strobe to the external program |
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|
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PSEN |
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memory via Port 0 and Port 2. It is activated twice each machine |
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cycle during fetches from external program memory. |
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When executing out of external program memory two activations of |
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PSEN |
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are skipped during each access to external data memory. |
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PSEN |
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is not activated (remains HIGH) during no fetches from |
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external program memory. |
PSEN |
can sink/source 8 LSTTL inputs. It |
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can drive CMOS inputs without external pull-ups. |
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(2) |
68 |
57 |
27 |
33 |
30 |
|
Address Latch Enable output: latches the lower byte of the |
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|
|
ALE/WE |
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address during access to external memory in normal operation. It is |
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12 |
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activated every six oscillator periods except during an external data |
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memory access. ALE can sink/source 8 LSTTL inputs. It can drive |
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CMOS inputs without an external pull-up. |
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: Write Enable. |
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WE |
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2 |
59 |
29 |
35 |
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HIGH level, the CPU executes from the internal program ROM. |
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EA |
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out of external program memory via Port 0 and Port 2. |
EA |
is not |
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allowed to float. |
EA |
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VPP: programming supply voltage. |
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P0.7/AD7 to |
3, 5, 6 |
60, 61, 62 |
30 to 33 |
36 to 43 |
32 to 39 |
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and 1 |
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VDD |
17 |
9 |
18 |
44 |
40 |
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Power-down mode. |
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microcontrollers Flash bit-8
P89C739 P89C738;
Semiconductors Philips
specification Product
1998 |
SYMBOL |
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PIN(1) |
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DESCRIPTION |
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Apr |
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PLCC68 |
QFP64 |
PLCC44 |
QFP44 |
DIP40 |
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P4.0 to P4.7 |
20, 24, |
12, 16, |
n.a.(3) |
n.a. |
n.a. |
Port 4: P4.0 to P4.7; 8-bit quasi-bidirectional I/O port with internal |
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07 |
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26, 44, |
18, 34, |
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pull-ups. Port 4 can sink/source 4 LSTTL inputs. It can drive CMOS |
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46, 50, 53 |
36, 40, 43 |
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inputs without external pull-ups. |
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and 57 |
and 47 |
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P5.0 to P5.7 |
60, 62, |
50, 52, |
n.a. |
n.a. |
n.a. |
Port 5: P5.0 to P5.7; 8-bit quasi-bidirectional I/O port with internal |
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63, 7, 8, |
53, 63, |
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pull-ups. Port 5 can sink/source 4 LSTTL inputs. It can drive CMOS |
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10, 13 |
64, 2, 5 |
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inputs without external pull-ups. |
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and 16 |
and 8 |
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n.c. |
1, 4, 18, |
23, 24, |
6, 17, 28 |
1, 12, 23 |
n.a. |
Not connected. |
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31, 32, |
25, 27, |
and 39 |
and 34 |
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33, 35, |
28, 42 |
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36, 37, 38 |
and 58 |
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52 and 66 |
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Notes
1. To avoid a ‘latch-up’ effect at power-on, the voltage on any pin (at any time) must not be higher than VDD + 0.5 V or lower than VSS − 0.5 V respectively.
13 2. To prohibit the toggling of the ALE/WE pin (RFI noise reduction) the bit RFI in the PCON register (PCON.5) must be set by software. This bit is cleared on reset and can be cleared by software. When set, ALE/WE pin will be pulled down internally, switching an external address latch to a quiet state. The MOVX instruction will still toggle ALE/WE as a normal MOVX. ALE/WE will retain its normal HIGH value during Idle mode and a LOW value during Power-down mode while in the ‘RFI’ mode. Additionally during internal access (EA = 1) ALE/WE will toggle normally when the address exceeds the internal program memory size. During external access (EA = 0) ALE/WE will always toggle normally, whether the flag ‘RFI’ is set or not.
3. n.a. = not applicable.
microcontrollers Flash bit-8
P89C739 P89C738;
Semiconductors Philips
specification Product
Philips Semiconductors |
Product specification |
|
|
8-bit Flash microcontrollers |
P89C738; P89C739 |
|
|
7 FUNCTIONAL DESCRIPTION
This chapter gives a brief overview of the device. Detailed functional descriptions are given in the following chapters:
Chapter 8 “Memory organization”
Chapter 9 “Interrupt system”
Chapter 10 “Timers/counters”
Chapter 11 “I/O facilities”
Chapter 12 “Full duplex Serial Port (UART)”
Chapter 13 “Reduced power modes”
Chapter 14 “Oscillator circuit”
Chapter 15 “Reset”
Chapter 16 “Multiple Programming ROM (MTP-ROM)”.
7.1General
The P89C738 is a stand-alone high-performance microcontroller designed for use in real time applications such as instrumentation, industrial control and medium to high-end consumer applications.
In addition to the 80C51 standard functions, the device provides a number of dedicated hardware functions for these applications. The P89C738 is a control-oriented CPU with on-chip Program and data memory. It can execute programs with internal or external program memory up to 64 kbytes. It can also access up to
64 kbytes of external data memory. For systems requiring extra capability, the P89C738 can be expanded using standard memories and peripherals.
The P89C738 has two software selectable modes of reduced activity for further power reduction: Idle and Power-down. The Idle mode freezes the CPU while allowing the RAM, timers, serial ports and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative except the Watchdog Timer if it is enabled. The Power-down mode can be terminated by an external reset, a Watchdog Timer overflow and in addition, by either of the two external interrupts.
7.2Instruction set execution
The P89C738 uses the powerful instruction set of the 80C51. Additional Special Function Registers (SFRs) are incorporated to control the on-chip peripherals.
The instruction set consists of 49 single-byte, 46 two-byte and 16 three-byte instructions. When using a 16 MHz oscillator, 64 instructions execute in 750 ns and
45 instructions execute in 1.5 μs. Multiply and divide instructions execute in 3 μs (see Chapter 18).
1998 Apr 07 |
14 |
Philips Semiconductors |
Product specification |
|
|
8-bit Flash microcontrollers |
P89C738; P89C739 |
|
|
8 MEMORY ORGANIZATION
The Central Processing Unit (CPU) manipulates operands in three memory spaces; these are the 64 kbytes external data memory (of which the lower 256 bytes reside in the internal AUX-RAM), 512 bytes internal data memory (consisting of 256 bytes standard RAM and 256 bytes AUX-RAM) and the 64 kbytes internal and external program memory.
8.1Program memory
The program memory address space of the P89C738 comprises an internal and an external memory portion. The P89C738 has 64 kbytes of program memory on-chip. The program memory can also be externally addressed up to 64 kbytes. If the EA pin is held HIGH, the P89C738 executes out of the internal program memory. If EA pin is held LOW, the P89C738 fetches all instructions from the external program memory. Figure 8 illustrates the program memory address space.
The security bit is always set in the P89C738 and P89C739 to protect the ROM code. Table 2 lists the access to the internal and external program memory by the MOVC instructions when the security bit has been set to a logic 1. If the security bit has been set to a logic 0 there are no restrictions for the MOVC instructions.
Table 2 Internal and external program memory access
MOVC |
PROGRAM MEMORY ACCESS |
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INSTRUCTION |
INTERNAL |
EXTERNAL |
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MOVC in internal |
YES |
YES |
program memory |
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MOVC in external |
NO |
YES |
program memory |
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handbook, halfpage65535
INTERNAL |
EXTERNAL |
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(EA = 1) |
(EA = 0) |
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0
MGK190
PROGRAM MEMORY
Fig.8 Program memory address space.
8.2Internal data memory
The internal data memory is divided into three physically separated parts: 256 bytes of RAM, 256 bytes of AUX-RAM, and a 128 bytes Special Function Registers (SFRs) area. These parts can be addressed as follows (see Fig.9 and Table 3):
∙RAM locations 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of the selected register bank.
∙RAM locations 128 to 255 can only be addressed indirectly. Address pointers are R0 and R1 of the selected register bank.
∙AUX-RAM locations 0 to 255 are indirectly addressable as the external data memory locations 0 to 255 with the MOVX instructions. Address pointers are R0 and R1 of the selected register bank and DPTR. When executing from internal program memory, an access to AUX-RAM 0 to 255 will not affect the ports Port 0, Port 2,
P3.6 and P3.7.
∙The SFRs can only be addressed directly in the address range from 128 to 255.
An access to external data memory locations higher than 255 will be performed with the MOVX DPTR instructions in the same way as in the 80C51 structure, i.e. with Port 0 and Port 2 as data/address bus and P3.6 and P3.7 as write and read timing signals. Note that the external data memory cannot be accessed with R0 and R1 as address pointer.
Figure 9 shows the internal and external data memory address space. Chapter 17 shows the Special Function Registers overview. Four 8-bit register banks occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations.
The stack can be located anywhere in the internal 256-byte RAM. The stack depth is only limited by the available internal RAM space of 256 bytes. All registers except the Program Counter and the four 8-bit register banks reside in the SFR address space.
Table 3 Internal data memory access
MEMORY |
LOCATION |
ADDRESS MODE |
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RAM |
0 to 127 |
direct and indirect |
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128 to 255 |
indirect only |
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SFR |
128 to 255 |
direct only |
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AUX-RAM |
0 to 255 |
indirect only with MOVX |
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1998 Apr 07 |
15 |
Philips Semiconductors |
Product specification |
|
|
8-bit Flash microcontrollers |
P89C738; P89C739 |
|
|
handbook,64 kbytesfull |
pagewidth |
64 kbytes |
|
64 kbytes |
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INTERNAL |
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EXTERNAL |
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INDIRECT ONLY |
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AUXILIARY |
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MBK524 |
DATA MEMORY |
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Fig.9 Internal and external data memory address space.
8.3Addressing
The P89C738 has five modes for addressing:
∙Register
∙Direct
∙Register-Indirect
∙Immediate
∙Base-Register plus Index-Register-Indirect.
The first three methods can be used for addressing destination operands. Most instructions have a ‘destination/source’ field that specifies the data type, addressing methods and operands involved.
For operations other than MOVs, the destination operand is also a source operand.
Access to memory addresses is as follows:
∙Register in one of the four 8-bit register banks through Register, Direct or Register-Indirect addressing
∙512 bytes of internal RAM through Direct or Register-Indirect addressing. Bytes 0 to 127 of internal RAM may be addressed directly/indirectly. Bytes
128 to 255 of internal RAM share their address location with the SFRs and so may only be addressed indirectly as data RAM. Bytes 0 to 255 of AUX-RAM can only be addressed indirectly via MOVX.
∙SFR through Direct addressing at address locations 128 to 255
∙External data memory through Register-Indirect addressing
∙Program memory look-up tables through Base-Register plus Index-Register-Indirect addressing.
1998 Apr 07 |
16 |
Philips Semiconductors |
Product specification |
|
|
8-bit Flash microcontrollers |
P89C738; P89C739 |
|
|
9 INTERRUPT SYSTEM
The P89C738 contains the same interrupt structure as the PCB80C51BH, but with a six-source interrupt structure with two priority levels (see Fig.10).
The external interrupts INT0 and INT1 can each be either level-activated or transition-activated, depending on bits IT0 and IT1 in SFR TCON. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON. When an external interrupt is generated, the corresponding request flag is cleared by the hardware when the service routine is vectored to, only if the interrupt was transition-activated. If the interrupt was level-activated the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated.
The Timer 0 and Timer 1 interrupts are generated by TF0 and TF1, which are set by a roll-over in their respective timer/counter register (except for Timer 0 in Mode 3 of the serial interface). When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to.
The Serial Port interrupt is generated by the logical ‘OR’ of RI and TI. Neither of these flags is cleared by hardware. The service routine will normally have to determine whether it was RI or TI that generated the interrupt, and the bit will have to be cleared by software.
The Timer 2 interrupt is generated by the logical OR of TF2 and EXF2. Neither of these flags is cleared by hardware. In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be cleared by software.
An additional (third) external interrupt is available, if Timer 2 is not used as timer/counter or if Timer 2 is used in the baud rate generator mode. That external interrupt 2 is falling-edge triggered. It shares the Timer 2 interrupt vector, interrupt enable and interrupt priority bits. If bit EXEN2 = 1 (T2CON.3), a HIGH-to-LOW transition at pin P1.1/T2EX sets the interrupt request flag EXF2 (T2CON.6) and can be used to generate an external interrupt.
The interrupt vectors are listed in Table 4.
Table 4 Interrupt vectors
SOURCE |
PRIORITY |
VECTOR |
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WITHIN LEVEL |
ADDRESS |
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IE0 |
1 (highest) |
0003H |
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TF0 |
2 |
000BH |
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IE1 |
3 |
0013H |
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TF1 |
4 |
001BH |
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RI + TI |
5 |
0023H |
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TF2 + EXF2 |
6 (lowest) |
002BH |
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handbook, halfpage |
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0 |
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INT0 |
IT0 |
IE0 |
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1 |
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TF0 |
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0 |
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INT1 |
IT1 |
IE1 |
sources |
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1 |
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TF1
TI
RI
TF2
EXF2
MGK193
Fig.10 P89C738/P89C739 interrupt sources.
1998 Apr 07 |
17 |
Philips Semiconductors |
|
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Product specification |
||
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8-bit Flash microcontrollers |
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P89C738; P89C739 |
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9.1 Interrupt Enable Register (IE) |
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Table 5 Interrupt Enable Register (SFR address A8H) |
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7 |
6 |
5 |
4 |
3 |
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0 |
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EA |
− |
ET2 |
ES |
ET1 |
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EX1 |
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ET0 |
EX0 |
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Table 6 Description of IE bits |
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BIT |
SYMBOL |
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7 |
EA |
General enable/disable control. If EA = 0, no interrupt is enabled. If EA = 1, any |
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6 |
− |
reserved |
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5 |
ET2 |
enable Timer 2 interrupt |
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4 |
ES |
enable Serial Port interrupt |
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3 |
ET1 |
enable Timer 1 interrupt |
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2 |
EX1 |
enable external interrupt 1 |
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1 |
ET0 |
enable Timer 0 interrupt |
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0 |
EX0 |
enable external interrupt 0 |
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9.2Interrupt Priority Register (IP)
Table 7 Interrupt Priority Register (SFR address B8H)
7 |
6 |
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5 |
4 |
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3 |
2 |
1 |
0 |
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− |
− |
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PT2 |
PS |
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PT1 |
PX1 |
PT0 |
PX0 |
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Table 8 Description of IP bits |
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BIT |
SYMBOL |
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DESCRIPTION |
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7 |
− |
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reserved |
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6 |
− |
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reserved |
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5 |
PT2 |
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Timer 2 interrupt priority level |
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4 |
PS |
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Serial Port interrupt priority level |
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3 |
PT1 |
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Timer 1 interrupt priority level |
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2 |
PX1 |
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external interrupt 1 priority level |
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1 |
PT0 |
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Timer 0 interrupt priority level |
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0 |
PX0 |
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external interrupt 0 priority level |
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1998 Apr 07 |
18 |
Philips Semiconductors |
Product specification |
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8-bit Flash microcontrollers |
P89C738; P89C739 |
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10 TIMERS/COUNTERS
The P89C738 contains three 16-bit timer/counters: Timer 0, Timer 1 and Timer 2; and one 8-bit timer, the Watchdog Timer (T3). Timer 0, Timer 1 and Timer 2 may be programmed to carry out the following functions:
·Measure time intervals and pulse durations
·Count events
·Generate interrupt requests.
10.1Timer 0 and Timer 1
Timers 0 and 1 each have a control bit in SFR TMOD that selects the timer or counter function of the corresponding timer. In the timer function, the register is incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists
of 12 oscillator periods, the count rate is 1¤12 of the oscillator frequency.
In the counter function, the register is incremented in response to a HIGH-to-LOW transition at the corresponding external input pin, T0 or T1. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a HIGH in one cycle and a LOW in the next cycle, the counter is incremented. Thus, it takes two machine cycles
(24 oscillator periods) to recognize a HIGH-to-LOW transition. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.
10.1.1Timer/Counter Mode Control Register (TMOD)
Timer 0 and Timer 1 can be programmed independently to operate in one of four modes:
Mode 0 8-bit timer/counter with divide-by-32 prescaler
Mode 1 16-bit timer/counter
Mode 2 8-bit timer/counter with automatic reload
Mode 3 Timer 0: one 8-bit timer/counter and one 8-bit timer. Timer 1: stopped.
When Timer 0 is in Mode 3, Timer 1 can be programmed to operate in Modes 0, 1 or 2 but cannot set an interrupt request flag and generate an interrupt. However, the overflow from Timer 1 can be used to pulse the Serial Port transmission-rate generator. With a 16 MHz crystal, the counting frequency of these timer/counters is as follows:
·In the timer function, the timer is incremented at a frequency of 1.33 MHz (1¤12 ´ oscillator frequency)
·In the counter function, the frequency handling range for external inputs is 0 to 0.66 MHz.
Both internal and external inputs can be gated to the timer by a second external source for directly measuring pulse duration.
The timers are started and stopped under software control. Each one sets its interrupt request flag when it overflows from all logic 1's to all logic 0's (respectively, the automatic reload value), with the exception of Mode 3 as previously described.
Table 9 Timer/Counter Mode Control Register (SFR address 89H)
7 |
6 |
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5 |
4 |
3 |
2 |
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1 |
0 |
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GATE |
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M1 |
M0 |
GATE |
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M1 |
M0 |
C/T |
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C/T |
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Table 10 Description of TMOD bits for Timer 1 and Timer 0
Timer 0: bit TMOD.0 to TMOD.3; Timer 1: bit TMOD.4 to TMOD.7; n = 0, 1.
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SYMBOL |
DESCRIPTION |
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7 and 3 |
GATE |
Gating control. When set Timer/counter ‘n’ is enabled only when |
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pin is HIGH and |
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INTn |
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control bit TRn (TR1 or TR0) is set. When cleared Timer n is enabled whenever TRn |
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control bit is set. |
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6 and 2 |
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Timer or Counter Selector. Cleared for Timer operation; input from internal system |
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C/T |
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clock. Set for Counter operation; input from pin Tn (T1 or T0). |
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5 and 1 |
M1 |
Timer 0, Timer 1 mode select; see Table 11. |
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4 and 0 |
M0 |
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1998 Apr 07 |
19 |
Philips Semiconductors |
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Product specification |
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8-bit Flash microcontrollers |
P89C738; P89C739 |
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Table 11 Timer 0; Timer 1 mode select |
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M1 |
M0 |
OPERATING |
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0 |
0 |
Timer TL0; TL1 serves as 5-bit prescaler. |
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0 |
1 |
16-bit Timer/Counter TH0; TH1 and TL0; TL1 are cascaded; there is no prescaler. |
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1 |
0 |
8-bit auto-reload Timer/Counter TH0; TH1 holds a value which is to be reloaded into |
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TL0; TL1 each time it overflows. |
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1 |
1 |
Timer 0: TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. |
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TH0 is an 8-bit timer only controlled by Timer 1 control bits. |
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1 |
1 |
Timer 1: Timer/Counter 1 stopped. |
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10.1.2Timer/Counter Control Register (TCON)
Table 12 |
Timer/Counter Control Register (SFR address 88H) |
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7 |
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6 |
5 |
4 |
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3 |
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2 |
1 |
0 |
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TF1 |
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TR1 |
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TF0 |
TR0 |
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IE1 |
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IT1 |
IE0 |
IT0 |
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Table 13 |
Description of TCON bits |
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BIT |
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SYMBOL |
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DESCRIPTION |
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7 and |
5 |
TF1 and TF0 |
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Timer 1 and Timer 0 overflow flags . Set by hardware on Timer/Counter overflow. |
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Cleared by hardware when processor vectors to interrupt routine. |
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6 and |
4 |
TR1 and TR0 |
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Timer 1 and Timer 0 run control bits. Set/cleared by software to turn Timer/Counter |
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on/off. |
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3 and |
1 |
IE1 and IE0 |
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Interrupt 1 and Interrupt 0 edge flags . Set by hardware when external interrupt edge |
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detected. Cleared when interrupt processed. |
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2 and |
0 |
IT1 and IT0 |
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Interrupt 1 and Interrupt 0 type control bits. Set/cleared by software to specify falling |
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edge/LOW level triggered external interrupts. |
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1998 Apr 07 |
20 |
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