Philips P89C51X2, P89C52X2, P89C54X2, P89C58X2 Technical data

P89C51X2

INTEGRATED CIRCUITS

P89C51X2/52X2/54X2/58X2

80C51 8-bit Flash microcontroller family

4K/8K/16K/32K Flash 128B/256B RAM

Preliminary data	2002 Jun 05
Supersedes data of 2002 Feb 28

P s

on o s

Philips Semiconductors Preliminary data

	80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
	4K/8K/16K/32K Flash

DESCRIPTION

The Philips microcontrollers described in this data sheet are high-performance static 80C51 designs. They are manufactured in an advanced CMOS process and contain a non-volatile Flash program memory. They support both 12-clock and 6-clock operation.

The P89C51X2 and P89C52X2/54X2/58X2 contain 128 byte RAM and 256 byte RAM respectively, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits.

In addition, the devices are static designs which offer a wide range of operating frequencies down to zero. Two software selectable

modes of power reduction Ð idle mode and power-down mode Ð are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data. Then the execution can be resumed from the point the clock was stopped.

SELECTION TABLE

For applications requiring more Flash and RAM, as well as more on-chip peripherals, see the P89C66x and P89C51Rx2 data sheets.

Type

Memory

Timers

Serial Interfaces

ADCbits/ch.

RAM

ROM

OTP

Flash

of# Timers

PWM

PCA

WD

UART

I

CAN

SPI

C

2

P89C58X2

256B

±

±

32K

3

±

±

±

n

±

±

±

±

P89C54X2

256B

±

±

16K

3

±

±

±

n

±

±

±

±

P89C52X2

256B

±

±

8K

3

±

±

±

n

±

±

±

±

P89C51X2

128B

±

±

4K

3

±

±

±

n

±

±

±

±

NOTE:

			DefaultClock Rate	Optional ClockRate	Max.
PinsI/O	Interrupts (External)	Program Security			Freq.
					at 6-clk
					/ 12-clk
					(MHz)
32	6 (2)	n	12±clk	6-clk	20/33
32	6 (2)	n	12±clk	6-clk	20/33
32	6 (2)	n	12±clk	6-clk	20/33
32	6 (2)	n	12±clk	6-clk	20/33

Freq. Freq. Range Range at 3V at 5V (MHz) (MHz)

±0±20/33

±0±20/33

±0±20/33

±0±20/33

1.I2C = Inter-Integrated Circuit Bus; CAN = Controller Area Network; SPI = Serial Peripheral Interface; PCA = Programmable Counter Array;

ADC = Analog-to-Digital Converter; PWM = Pulse Width Modulation

DEVICE COMPARISON TABLE

Item	P89C5xX2 devices (this data	P89C5xBx devices (separate data	P89C5xUxx devices
	sheet)	sheet)	(discontinued)
Type Description	P89C5xX2Bxx/P89C5xX2Fxx	P89C5xBx	P89C5xUBxx/P89C5xUFxx
PROGRAMMING	When using a parallel programmer,	When using a parallel programmer,	When using a parallel programmer,
ALGORITHM	be sure to select P89C5xX2 devices.	be sure to select P89C5xBx devices.	be sure to select P89C5xUxxx
	IF DEVICES ARE NOT YET	IF DEVICES ARE NOT YET	devices.
	SELECTABLE ASK YOUR	SELECTABLE ASK YOUR
	PROGRAMMER VENDOR FOR A	PROGRAMMER VENDOR FOR A
	SOFTWARE UPDATE	SOFTWARE UPDATE
Quad Flat Package	LQFP package (P89C5xX2xBD)	LQFP package (P89C5xBBD)	PQFP package (P89C5xUxBB)
type
Package identifiers	PLCC = A	PLCC = A	PLCC = AA
	LQFP = BD	LQFP = BD	LQFP = BB
	PDIP = N	PDIP = P	PDIP = PN
Flash Memory program	10,000 program and erase cycles	10,000 program and erase cycles	100 program and erase cycles
and erase cycles

2002 Jun 06

2

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

FEATURES

•80C51 Central Processing Unit

±4 Kbytes Flash (P89C51X2)

±8 Kbytes Flash (P89C52X2)

±16 Kbytes Flash (P89C54X2)

±32 Kbytes Flash (P89C58X2)

±128 byte RAM (P89C51X2)

±256 byte RAM (P89C52/54X2/58X2)

±Boolean processor

±Fully static operation

•12-clock operation with selectable 6-clock operation (via software or via parallel programmer)

•Memory addressing capability

± Up to 64 Kbytes ROM and 64 Kbytes RAM

•Power control modes:

±Clock can be stopped and resumed

±Idle mode

±Power-down mode

•Two speed ranges

±0 to 20 MHz with 6-clock operation

±0 to 33 MHz with 12-clock operation

•LQFP, PLCC or DIP package

•Extended temperature ranges

•Dual Data Pointers

•Three security bits

•Four interrupt priority levels

•Six interrupt sources

•Four 8-bit I/O ports

•Full-duplex enhanced UART

±Framing error detection

±Automatic address recognition

•Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture and compare)

•Programmable clock-out pin

•Asynchronous port reset

•Low EMI (inhibit ALE, slew rate controlled outputs, and 6-clock mode)

•Wake-up from Power Down by an external interrupt

2002 Jun 06

3

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

P89C51X2 ORDERING INFORMATION (4 KBYTE FLASH)

Type number	Package			Temperature
				Range (°C)
	Name	Description	Version
P89C51X2BA	PLCC44	plastic leaded chip carrier; 44 leads	SOT187-2	0 to +70
P89C51X2BN	DIP40	plastic dual in-line package; 40 leads (600 mil)	SOT129-1	0 to +70
P89C51X2BBD	LQFP44	plastic low profile quad flat package; 44 leads	SOT389-1	0 to +70
P89C51X2FA	PLCC44	plastic leaded chip carrier; 44 leads	SOT187-2	±40 to +85

P89C52X2 ORDERING INFORMATION (8 KBYTE FLASH)

Type number	Package			Temperature
				Range (°C)
	Name	Description	Version
P89C52X2BA	PLCC44	plastic leaded chip carrier; 44 leads	SOT187-2	0 to +70
P89C52X2BN	DIP40	plastic dual in-line package; 40 leads (600 mil)	SOT129-1	0 to +70
P89C52X2BBD	LQFP44	plastic low profile quad flat package; 44 leads	SOT389-1	0 to +70
P89C52X2FA	PLCC44	plastic leaded chip carrier; 44 leads	SOT187-2	±40 to +85
P89C52X2FN	DIP40	plastic dual in-line package; 40 leads (600 mil)	SOT129-1	±40 to +85
P89C52X2FBD	LQFP44	plastic low profile quad flat package; 44 leads	SOT389-1	±40 to +85

P89C54X2 ORDERING INFORMATION (16 KBYTE FLASH)

Type number	Package			Temperature
				Range (°C)
	Name	Description	Version
P89C54X2BA	PLCC44	plastic lead chip carrier; 44 leads	SOT187-2	0 to +70
P89C54X2BN	DIP40	plastic dual in-line package; 40 leads (600 mil)	SOT129-1	0 to +70
P89C54X2BBD	LQFP44	plastic low profile quad flat package; 44 leads	SOT389-1	0 to +70
P89C54X2FA	PLCC44	plastic lead chip carrier; 44 leads	SOT187-2	±40 to +85

P89C58X2 ORDERING INFORMATION (32 KBYTE FLASH)

Type number	Package			Temperature
				Range (°C)
	Name	Description	Version
P89C58X2BA	PLCC44	plastic lead chip carrier; 44 leads	SOT187-2	0 to +70
P89C58X2BN	DIP40	plastic dual in-line package; 40 leads (600 mil)	SOT129-1	0 to +70
P89C58X2BBD	LQFP44	plastic low profile quad flat package; 44 leads	SOT389-1	0 to +70
P89C58X2FA	PLCC44	plastic lead chip carrier; 44 leads	SOT187-2	±40 to +85

2002 Jun 06

4

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

PART NUMBER DERIVATION

Memory							Temperature Range	Package
	P89C51X2						B = 0 °C TO +70 °C	A = PLCC
						X2 = 6-clock	F = ±40 °C TO +85 °C	N = DIP
	9 = Flash				1 = 128 BYTES RAM			BD = LQFP
					4 KBYTES FLASH	mode available
					2 = 256 BYTES RAM
					8 KBYTES FLASH
					4 = 256 BYTES RAM
					16 KBYTES FLASH
					8 = 256 BYTES RAM
					32 KBYTES FLASH

The following table illustrates the correlation between operating mode, power supply and maximum external clock frequency:

Operating Mode	Power Supply	Maximum Clock Frequency
6-clock	5 V ± 10%	20 MHz
12-clock	5 V ± 10%	33 MHz

2002 Jun 06

5

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

BLOCK DIAGRAM 1

	ACCELERATED 80C51 CPU
	(12-CLK MODE, 6-CLK MODE)
	0K / 4K / 8K / 16K /
	32 KBYTE
	CODE FLASH
	FULL-DUPLEX
	ENHANCED UART
	128 / 256 BYTE
	DATA RAM
	TIMER 0
	TIMER 1
	PORT 3
	CONFIGURABLE I/Os
	TIMER 2
	PORT 2
	CONFIGURABLE I/Os
	PORT 1
	CONFIGURABLE I/Os
	PORT 0
	CONFIGURABLE I/Os
CRYSTAL OR	OSCILLATOR
RESONATOR
	su01617
2002 Jun 06	6

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

BLOCK DIAGRAM 2 (CPU-ORIENTED)

				P0.0±P0.7	P2.0±P2.7
				PORT 0	PORT 2
				DRIVERS	DRIVERS
VCC
VSS
	RAM ADDR		RAM	PORT 0	PORT 2	ROM/EPROM
	REGISTER			LATCH	LATCH
							8
	B		ACC			STACK
	REGISTER					POINTER
							PROGRAM
					TMP1		ADDRESS
				TMP2			REGISTER
				ALU			BUFFER
					SFRs
					TIMERS		PC
				PSW			INCRE-
							MENTER
						8	16
							PROGRAM
							COUNTER
PSEN		INSTRUCTION	REGISTER
ALE/PROG	TIMING						DPTR'S
EA / VPP	AND						MULTIPLE
	CONTROL
RST
	PD			PORT 1		PORT 3
				LATCH		LATCH
	OSCILLATOR
				PORT 1		PORT 3
				DRIVERS		DRIVERS
	XTAL1		XTAL2
				P1.0±P1.7		P3.0±P3.7
							SU00845
2002 Jun 06					7

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

LOGIC SYMBOL

		VCC	VSS
		XTAL1
			0	ADDRESS AND
			PORT	DATA BUS
		XTAL2
				T2
			1	T2EX
		RST
			PORT
		EA/VPP
		PSEN
FUNCTIONSSECONDARY	ALE/PROG		2PORT
	RxD	3PORT
	TxD
	INT0
	INT1			ADDRESS BUS
	T0
	T1
	WR
	RD
				SU00830

PLASTIC DUAL IN-LINE PACKAGE

PIN CONFIGURATIONS

	T2/P1.0
			1				40		VCC
T2EX/P1.1
			2				39		P0.0/AD0
		P1.2	3				38		P0.1/AD1
		P1.3	4				37		P0.2/AD2
		P1.4	5				36		P0.3/AD3
		P1.5	6				35		P0.4/AD4
		P1.6	7				34		P0.5/AD5
		P1.7	8				33		P0.6/AD6
		RST	9				32		P0.7/AD7
					DUAL
	RxD/P3.0		10				31		EA/VPP
				IN-LINE
	TxD/P3.1		11	PACKAGE			30		ALE
			12				29
	INT0/P3.2								PSEN
			13				28		P2.7/A15
	INT1/P3.3
	T0/P3.4		14				27		P2.6/A14
	T1/P3.5		15				26		P2.5/A13
			16				25		P2.4/A12
	WR/P3.6
			17				24		P2.3/A11
	RD/P3.7
	XTAL2		18				23		P2.2/A10
	XTAL1		19				22		P2.1/A9
		VSS	20				21		P2.0/A8
						SU01063

PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS

6	1	40
7		39
	PLCC
17		29
18		28

Pin	Function			Pin	Function				Pin	Function
1	NIC*			16	P3.4/T0				31	P2.7/A15
2	P1.0/T2			17	P3.5/T1				32
										PSEN
3	P1.1/T2EX			18					33	ALE
					P3.6/WR
4	P1.2			19					34	NIC*
					P3.7/RD
5	P1.3			20	XTAL2				35	EA/VPP
6	P1.4			21	XTAL1				36	P0.7/AD7
7	P1.5			22	VSS				37	P0.6/AD6
8	P1.6			23	NIC*				38	P0.5/AD5
9	P1.7			24	P2.0/A8				39	P0.4/AD4
10	RST			25	P2.1/A9				40	P0.3/AD3
11	P3.0/RxD			26	P2.2/A10				41	P0.2/AD2
12	NIC*			27	P2.3/A11				42	P0.1/AD1
13	P3.1/TxD			28	P2.4/A12				43	P0.0/AD0
14				29	P2.5/A13				44	VCC
	P3.2/INT0
15				30	P2.6/A14
	P3.3/INT1

* NO INTERNAL CONNECTION	SU01062

LOW PROFILE QUAD FLAT PACK

PIN FUNCTIONS

						44								34
	1																		33
											LQFP
	11																		23
						12								22
Pin	Function							Pin			Function							Pin		Function
1	P1.5					16					VSS			31						P0.6/AD6
2	P1.6					17					NIC*			32						P0.5/AD5
3	P1.7					18					P2.0/A8			33						P0.4/AD4
4	RST					19					P2.1/A9			34						P0.3/AD3
5	P3.0/RxD					20					P2.2/A10			35						P0.2/AD2
6	NIC*					21					P2.3/A11			36						P0.1/AD1
7	P3.1/TxD					22					P2.4/A12			37						P0.0/AD0
8						23					P2.5/A13			38						VCC
	P3.2/INT0
9						24					P2.6/A14			39						NIC*
	P3.3/INT1
10	P3.4/T0					25					P2.7/A15			40						P1.0/T2
11	P3.5/T1					26								41						P1.1/T2EX
											PSEN
12						27					ALE			42						P1.2
	P3.6/WR
13						28					NIC*			43						P1.3
	P3.7/RD
14	XTAL2					29								44						P1.4
											EA/VPP
15	XTAL1					30					P0.7/AD7

* NO INTERNAL CONNECTION

SU01487

2002 Jun 06

8

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

DIP

PLCC

LQFP

TYPE

NAME AND FUNCTION

VSS

20

22

16

I

Ground: 0 V reference.

VCC

40

44

38

I

Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

P0.0-0.7

39±32

43±36

37±30

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to

them float and can be used as high-impedance inputs. Port 0 is also the multiplexed

low-order address and data bus during accesses to external program and data memory. In

this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the

code bytes during program verification and received code bytes during Flash programming.

External pull-ups are required during program verification.

P1.0±P1.7

1±8

2±9

40±44,

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s

1±3

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,

port 1 pins that are externally pulled low will source current because of the internal pull-ups.

(See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address byte

during program memory verification. Alternate functions for Port 1 include:

1

2

40

I/O

T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out)

2

3

41

I

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control

P2.0±P2.7

21±28

24±31

18±25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,

port 2 pins that are externally being pulled low will source current because of the internal

pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte

during fetches from external program memory and during accesses to external data memory

that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal

pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses

(MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins

receive the high order address bits during Flash programming and verification.

P3.0±P3.7

10±17

11,

5,

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s

13±19

7±13

written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,

port 3 pins that are externally being pulled low will source current because of the pull-ups.

(See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51

family, as listed below:

10

11

5

I

RxD (P3.0): Serial input port

11

13

7

O

TxD (P3.1): Serial output port

12

14

8

I

(P3.2): External interrupt

INT0

13

15

9

I

(P3.3): External interrupt

INT1

14

16

10

I

T0 (P3.4): Timer 0 external input

15

17

11

I

T1 (P3.5): Timer 1 external input

16

18

12

O

(P3.6): External data memory write strobe

WR

17

19

13

O

(P3.7): External data memory read strobe

RD

RST

9

10

4

I

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the

device. An internal diffused resistor to VSS permits a power-on reset using only an external

capacitor to VCC.

ALE/PROG

30

33

27

O

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

address during an access to external memory. In normal operation, ALE is emitted at a

constant rate of 1/6 (12-clk) or 1/3 (6-clk Mode) the oscillator frequency, and can be used for

external timing or clocking. Note that one ALE pulse is skipped during each access to

external data memory. This pin is also the program pulse input

(PROG)

during Flash

programming. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be

active only during a MOVX instruction.

29

32

26

O

Program Store Enable: The read strobe to external program memory. When the device is

PSEN

executing code from the external program memory,

PSEN

is activated twice each machine

cycle, except that two

PSEN

activations are skipped during each access to external data

memory.

PSEN

is not activated during fetches from internal program memory.

31

35

29

I

External Access Enable/Programming Supply Voltage:

must be externally held low to enable the device

EA/VPP

EA

to fetch code from external program memory locations 0000H to 0FFFH/1FFFH/3FFFH/7FFFH. If

EA

is held

high, the device executes from internal program memory unless the program counter contains an address

greater than the on-chip Flash. This pin also receives the 5 V / 12 V programming supply voltage (VPP) during

Flash programming. If security bit 1 is programmed,

EA

will be internally latched on Reset.

XTAL1

19

21

15

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator

circuits.

XTAL2

18

20

14

O

Crystal 2: Output from the inverting oscillator amplifier.

NOTE:	+ 0.5 V or V		± 0.5 V, respectively.
To avoid ªlatch-upº effect at power-on, the voltage on any pin at any time must not be higher than V		SS
CC

2002 Jun 06

9

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

Table 1.

Special Function Registers

SYMBOL

DESCRIPTION

DIRECT

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION

RESET

ADDRESS

MSB

LSB

VALUE

ACC*

Accumulator

E0H

E7

E6

E5

E4

E3

E2

E1

E0

00H

AUXR#

Auxiliary

8EH

xxxxxxx0B

±

±

±

±

±

±

±

AO

AUXR1#

Auxiliary 1

A2H

xxx000x0B

±

±

±

±

WUPD

0

±

DPS

B*

B register

F0H

00H

F7

F6

F5

F4

F3

F2

F1

F0

CKCON

Clock Control Register

8FH

xxx00000B

±

±

±

±

±

±

±

X2

DPTR:

Data Pointer (2 bytes)

DPH

Data Pointer High

83H

00H

DPL

Data Pointer Low

82H

00H

AF

AE

AD

AC

AB

AA

A9

A8

IE*

Interrupt Enable

A8H

0x000000B

EA

±

ET2

ES

ET1

EX1

ET0

EX0

BF

BE

BD

BC

BB

BA

B9

B8

IP*

Interrupt Priority

B8H

xx000000B

±

±

PT2

PS

PT1

PX1

PT0

PX0

IPH#

Interrupt Priority High

B7H

xx000000B

±

±

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

87

86

85

84

83

82

81

80

P0*

Port 0

80H

FFH

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

97

96

95

94

93

92

91

90

P1*

Port 1

90H

FFH

±

±

±

±

±

±

T2EX

T2

A7

A6

A5

A4

A3

A2

A1

A0

P2*

Port 2

A0H

FFH

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

B7

B6

B5

B4

B3

B2

B1

B0

P3*

Port 3

B0H

FFH

RD

WR

T1

T0

INT1

INT0

TxD

RxD

PCON#1

Power Control

87H

00xx0000B

SMOD1

SMOD0

±

POF

GF1

GF0

PD

IDL

D7

D6

D5

D4

D3

D2

D1

D0

PSW*

Program Status Word

D0H

000000x0B

CY

AC

F0

RS1

RS0

OV

±

P

RACAP2H#

Timer 2 Capture High

CBH

00H

RACAP2L#

Timer 2 Capture Low

CAH

00H

SADDR#

Slave Address

A9H

00H

SADEN#

Slave Address Mask

B9H

00H

SBUF

Serial Data Buffer

99H

xxxxxxxxB

9F

9E

9D

9C

9B

9A

99

98

SCON*

Serial Control

98H

00H

SM0/FE

SM1

SM2

REN

TB8

RB8

TI

RI

SP

Stack Pointer

81H

07H

8F

8E

8D

8C

8B

8A

89

88

TCON*

Timer Control

88H

00H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

CF

CE

CD

CC

CB

CA

C9

C8

T2CON*

Timer 2 Control

C8H

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

00H

T2MOD#

Timer 2 Mode Control

C9H

±

±

±

±

±

±

T2OE

DCEN

xxxxxx00B

TH0

Timer High 0

8CH

00H

TH1

Timer High 1

8DH

00H

TH2#

Timer High 2

CDH

00H

TL0

Timer Low 0

8AH

00H

TL1

Timer Low 1

8BH

00H

TL2#

Timer Low 2

CCH

00H

TMOD

Timer Mode

89H

GATE

C/T

M1

M0

GATE

C/T

M1

M0

00H

NOTE:

Unused register bits that are not defined should not be set by the user's program. If violated, the device could function incorrectly.

*SFRs are bit addressable.

# SFRs are modified from or added to the 80C51 SFRs.

± Reserved bits.

1. Reset value depends on reset source.

2002 Jun 06

10

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

FLASH EPROM MEMORY

General Description

The P89C51X2/P89C52X2/P89C54X2/P89C58X2 FLASH reliably stores memory contents even after 10,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling.

Features

•FLASH EPROM internal program memory with Chip Erase

•Up to 64 kbyte external program memory if the internal program memory is disabled (EA = 0)

•Programmable security bits

•10,000 minimum erase/program cycles for each byte

•10 year minimum data retention

•Programming support available from many popular vendors

OSCILLATOR CHARACTERISTICS

Using the oscillator, XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol.

To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. However, minimum and maximum high and low times specified in the data sheet must be observed.

Clock Control Register (CKCON)

This device provides control of the 6-clock/12-clock mode by both an SFR bit (bit X2 in register CKCON) and a Flash bit (bit FX2, located in the Security Block). When X2 is 0, 12-clock mode is activated. By setting this bit to 1, the system is switching to 6-clock mode. Having this option implemented as SFR bit, it can be accessed anytime and changed to either value. Changing X2 from 0 to 1 will result in executing user code at twice the speed, since all system time intervals will be divided by 2. Changing back from 6-clock to 12-clock mode will slow down running code by a factor of

2.

The Flash clock control bit (FX2) activates the 6-clock mode when programmed using a parallel programmer, superceding the X2 bit (CKCON.0). Please also see Table 2 below.

Table 2.

FX2 clock mode bit	X2 bit	CPU clock mode
(can only be set by	(CKCON.0)
parallel programmer)
erased	0	12-clock mode
		(default)
erased	1	6-clock mode
programmed	X	6-clock mode

Programmable Clock-Out Pin

A 50% duty cycle clock can be programmed to be output on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed:

1.to input the external clock for Timer/Counter 2, or

2.to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency in 12-clock mode (122 Hz to

8 MHz in 6-clock mode).

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer.

The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation:

Oscillator Frequency

n (65536±RCAP2H, RCAP2L)

Where:

n = 2 in 6-clock mode, 4 in 12-clock mode.

(RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.

In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the

Clock-Out frequency will be the same.

RESET

A reset is accomplished by holding the RST pin HIGH for at least two machine cycles (24 oscillator periods in 12-clock and 12 oscillator periods in 6-clock mode), while the oscillator is running. To insure a reliable power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles, unless it has been set to

6-clock operation using a parallel programmer.

LOW POWER MODES

Stop Clock Mode

The static design enables the clock speed to be reduced down to

0 MHz (stopped). When the oscillator is stopped, the RAM and Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested.

Idle Mode

In idle mode (see Table 3), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.

2002 Jun 06

11

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

Power-Down Mode

To save even more power, a Power Down mode (see Table 3) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0 V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down Mode is terminated.

Either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. WUPD (AUXR1.3±Wakeup from Power Down) enables or disables the wakeup from power down with external interrupt. Where:

WUPD = 0: Disable

WUPD = 1: Enable

To properly terminate Power Down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms).

To terminate Power Down with an external interrupt, INT0 or INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be

executed after RETI will be the one following the instruction that put the device into Power Down.

Design Consideration

When the idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

ONCE Mode

The ONCE (ªOn-Circuit Emulationº) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked in the following way:

1.Pull ALE low while the device is in reset and PSEN is high;

2.Hold ALE low as RST is deactivated.

While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.

Table 3. External Pin Status During Idle and Power-Down Modes

MODE	PROGRAM MEMORY	ALE		PSEN		PORT 0	PORT 1	PORT 2	PORT 3
Idle	Internal	1		1		Data	Data	Data	Data
Idle	External	1		1		Float	Data	Address	Data
Power-down	Internal	0		0		Data	Data	Data	Data
Power-down	External	0		0		Float	Data	Data	Data

TIMER 0 AND TIMER 1 OPERATION

Timer 0 and Timer 1

The ªTimerº or ªCounterº function is selected by control bits C/Tin the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the following text.

Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure 2 shows the Mode 0 operation.

In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The counted input is enabled to the Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the

Timer to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a control bit in the Special Function Register TCON (Figure 3).

The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers.

Mode 0 operation is the same for Timer 0 as for Timer 1. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

Mode 1

Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits.

Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 4. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which is preset by software. The reload leaves THn unchanged.

Mode 2 operation is the same for Timer 0 as for Timer 1.

Mode 3

Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0.

Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 5. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, and TF0 as well as pin INT0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the ªTimer 1º interrupt.

2002 Jun 06

12

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

Mode 3 is provided for applications requiring an extra 8-bit timer on

turned on and off by switching it out of and into its own Mode 3, or

the counter. With Timer 0 in Mode 3, an 80C51 can look like it has

can still be used by the serial port as a baud rate generator, or in

three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be

fact, in any application not requiring an interrupt.

TMOD

Address = 89H

Reset Value = 00H

Not Bit Addressable

7

6

5

4

3

2

1

0

GATE

C/T

M1

M0

GATE

C/T

M1

M0

TIMER 1

TIMER 0

BIT

SYMBOL

FUNCTION

TMOD.3/

GATE

Gating control when set. Timer/Counter ªnº is enabled only while

pin is high and

ªINTnº

TMOD.7

ªTRnº control pin is set. when cleared Timer ªnº is enabled whenever ªTRnº control bit is set.

TMOD.2/

Timer or Counter Selector cleared for Timer operation (input from internal system clock.)

C/T

TMOD.6

Set for Counter operation (input from ªTnº input pin).

M1

M0

OPERATING

0

0

8048 Timer: ªTLnº serves as 5-bit prescaler.

01 16-bit Timer/Counter: ªTHnº and ªTLnº are cascaded; there is no prescaler.

10 8-bit auto-reload Timer/Counter: ªTHnº holds a value which is to be reloaded into ªTLnº each time it overflows.

11 (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.

TH0 is an 8-bit timer only controlled by Timer 1 control bits.

1

1

(Timer 1) Timer/Counter 1 stopped.

SU01580

Figure 1. Timer/Counter 0/1 Mode Control (TMOD) Register

OSC	d*
	C/T = 0		TLn	THn
					TFn	Interrupt
			(5 Bits)	(8 Bits)
	C/T = 1
Tn Pin			Control
	TRn
Timer n
Gate bit
INTn Pin
*d = 6 in 6-clock mode; d = 12 in 12-clock mode.						SU01618
	Figure 2.	Timer/Counter 0/1 Mode 0: 13-Bit Timer/Counter

2002 Jun 06

13

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

TCON

Address = 88H

Reset Value = 00H

Bit Addressable

7

6

5

4

3

2

1

0

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

BIT

SYMBOL

FUNCTION

TCON.7

TF1

Timer 1 overflow flag. Set by hardware on Timer/Counter overflow.

Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software.

TCON.6

TR1

Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off.

TCON.5

TF0

Timer 0 overflow flag. Set by hardware on Timer/Counter overflow.

Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software.

TCON.4

TR0

Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off.

TCON.3

IE1

Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected.

Cleared when interrupt processed.

TCON.2

IT1

Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered

external interrupts.

TCON.1

IE0

Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected.

Cleared when interrupt processed.

TCON.0

IT0

Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level

triggered external interrupts.

SU01516

Figure 3. Timer/Counter 0/1 Control (TCON) Register

OSC	d*
	C/T = 0	TLn
			TFn	Interrupt
		(8 Bits)
	C/T = 1
	Tn Pin	Control
	TRn	Reload
Timer n
Gate bit
		THn
INTn Pin		(8 Bits)
*d = 6 in 6-clock mode; d = 12 in 12-clock mode.				SU01619
	Figure 4.	Timer/Counter 0/1 Mode 2: 8-Bit Auto-Reload

2002 Jun 06

14

Philips Semiconductors Preliminary data

80C51 8-bit Flash microcontroller family	P89C51X2/52X2/54X2/58X2
4K/8K/16K/32K Flash

OSC	d*
	C/T = 0
		TL0	TF0	Interrupt
		(8 Bits)
	C/T = 1
	T0 Pin	Control
	TR0
Timer 0
Gate bit
INT0 Pin
	d*	TH0	TF1	Interrupt
OSC		(8 Bits)
		Control
	TR1
*d = 6 in 6-clock mode; d = 12 in 12-clock mode.				SU01620
	Figure 5.	Timer/Counter 0 Mode 3: Two 8-Bit Counters

TIMER 2 OPERATION

Timer 2

Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2 in the special function register T2CON (see Figure 6). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate

Generator, which are selected by bits in the T2CON as shown in Table 4.

Capture Mode

In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which, upon overflowing, sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the

IE register). If EXEN2=1, Timer 2 operates as described above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 (like TF2) can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in

Figure 7 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/12 (12-clock Mode) or osc/6 (6-clock Mode) pulses).

Auto-Reload Mode (Up or Down Counter)

In the 16-bit auto-reload mode, Timer 2 can be configured as either a timer or counter (C/T2 in T2CON), then programmed to count up or down. The counting direction is determined by bit DCEN (Down

Counter Enable) which is located in the T2MOD register (see Figure 8). After reset, DCEN=0 which means Timer 2 will default to counting up. If DCEN is set, Timer 2 can count up or down depending on the value of the T2EX pin.

Figure 9 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the

Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software.

If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1.

In Figure 10 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX, Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2.

A logic 0 applied to pin T2EX causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. A Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2.

The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation.

2002 Jun 06

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