Philips N74F862N, N74F863D, N74F863N, N74F864D, N74F861D Datasheet

 

74F862, 74F863 Bus transceivers (3-State)

Product specification Supersedes data of 1999 Jan 08 IC15 Data Handbook

2000 Mar 24

INTEGRATED CIRCUITS

Philips Semiconductors Product specification

74F862, 74F863

Bus transceivers (3-State)

2

2000 Mar 24 853-0881 23378

FEA TURES

•Provide high performance bus interface buffering for wide

data/address paths or buses carrying parity

•High impedance NPN base inputs for reduced loading (20µA in

High and Low states)

•I

IL

is 20µA vs. 1000µA for AM29861 series

•Buffered control inputs for light loading, or increased fan-in as

required with MOS microprocessors

•Positive and negative over-shoots are clamped to ground

•3-State outputs glitch free during power-up and power-down

•Slim dual In-line (DIP) 300mil package

•Broadside pinout compatible with AMD AM29862–29863

•Outputs sink 64mA

DESCRIPTION

The 74F862 and 74F863 bus transceivers provide high performance bus interface buffering for wide data/address paths of buses carrying parity. The 74F863 9-bit bus transceiver has NOR-ed transmit and receive output enables for maximum control flexibility.

TYPE

TYPICAL

PROPAGATION

DELA Y

TYPICAL SUPPL Y

CURRENT

(TOT AL)

74F862 6.0ns 150mA 74F863 6.0ns 115mA

ORDERING INFORMATION

PACKAGES

COMMERCIAL RANGE

V

CC

= 5V±10%;

T

a

= 0°C to +70°C

PKG DWG #

24-pin Plastic Slim Dual In-line (300mil) Package

N74F862N, N74F863N SOT222-1

24-pin Plastic Small Outline Large

1

N74F862D, N74F863D SOT137-1

NOTE:

1. Thermal mounting techniques are recommended. See SMD Process Applications for a discussion of thermal considerations for surface mounted devices.

PIN CONFIGURATION

1 2

3 4 5 6 7 8

9 10 11 12

18

24

OEAB

B

0

B

1

B

2

B

3

B

4

B

5

B

6

B

7

B

8

B

9

V

CC

13

23 22 21

20 19

17 16 15 14

TOP VIEW

OEBA

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

GND

SF00518

Philips Semiconductors Product specification

74F862, 74F863

Bus transceivers (3-State)

2000 Mar 24

3

PIN CONFIGURATION

1 2

3 4 5 6 7 8

9 10 11 12

18

24

OEAB

B

0

B

1

B

2

B

3

B

4

B

5

B

6

B

7

B

8

B

9

V

CC

13

23 22 21

20 19

17 16 15 14

TOP VIEW

74F862

OEBA

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

GND

SF00521

LOGIC SYMBOL

A

0

1

13

OEAB OEBA

234567891011

23 22 21 2019 18 1716 15 14

A

1A2A3A4A5A6A7A8A9

B0B1B2B3B4B5B6B7B8B

9

VCC= Pin 24 GND = Pin 12

74F862

SF00522

LOGIC SYMBOL (IEEE/IEC)

1

13

74F862

EN1(BA) EN2(AB)

2

3 4 5

6 7 8

9 10 11

23

22 21 20

19 18 17 16 15 14

∆

1

∆

2

∆

SF00523

PIN CONFIGURA TION

1 2

3 4 5 6 7 8

9 10 11 12

18

24

OEAB

1

B

0

B

1

B

2

B

3

B

4

B

5

B

6

B

7

B

8

V

CC

13

23 22 21

20 19

17 16 15 14

TOP VIEW

OEBA

0

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

GND

OEBA

1

OEAB

0

SF01441

74F863

LOGIC SYMBOL

A

0

11

1

OEBA

0

OEBA

1

2345678910

23 22 21 2019 18 1716 15

A

1A2A3A4A5A6A7A8

B0B1B2B3B4B5B6B7B

8

VCC= Pin 24 GND = Pin 12

74F863

13

14

OEAB

0

OEAB

1

SF00525

LOGIC SYMBOL (IEEE/IEC)

1

11

74F863

EN1(BA) EN2(AB)

2

3 4 5

6 7 8

9

10 11

23

22 21 20

19 18 17 16 15 14

∆

1

∆

2

∆

14 13

&

SF00526

Philips Semiconductors Product specification

74F862, 74F863

Bus transceivers (3-State)

2000 Mar 24

4

LOGIC DIAGRAM

74F862

10 10

OEAB

OEBA

A

n

B

n

SF00531

LOGIC DIAGRAM

74F863

99

OEAB

0

A

n

B

n

OEAB

1

OEBA

0

OEBA

1

SF00532

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

74F(U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

A0 – A

9

Data transmit inputs 3.5/0.1 17 70µA/70µA

B0 – B

9

Data receive inputs 3.5/0.1 17 70µA/70µA

OEBA Transmit output enable input 1.0/0.033 20µA/20µA

74F862

OEAB Receive output enable input 1.0/0.033 20µA/20µA

A0 – A

9

Data transmit outputs 1200/106.7 24mA/64mA

B0 – B

9

Data receive outputs 1200/106.7 24mA/64mA

A0 – A

9

Data transmit inputs 3.5/0.1 17 70µA/70µA

B0 – B

9

Data receive inputs 3.5/0.1 17 70µA/70µA

OEBA

n

Transmit output enable input 1.0/0.033 20µA/20µA

74F863

OEAB

n

Receive output enable input 1.0/0.033 20µA/20µA

A0 – A

9

Data transmit outputs 1200/106.7 24mA/64mA

B0 – B

9

Data receive outputs 1200/106.7 24mA/64mA

NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.

FUNCTION TABLE FOR 74F862

INPUTS OPERATING MODES

OEAB OEBA 74F862

L H A data to B bus H L B bus to A data H H Z

H = High voltage level L = Low voltage level Z = High impedance “off” state

FUNCTION TABLE FOR 74F863

INPUTS OPERATING MODES

OEAB

0

OEAB

1

OEBA

0

OEBA

1

74F863

L

L0

L L

H

X

X H

A data to B bus

H X

X H

L L

B bus to A data

H H H H Z

H = High voltage level L = Low voltage level Z = High impedance “off” state