Philips N74F723AD, N74F725N, N74F725AN, N74F725AD, N74F725-1N Datasheet
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74F723A
Quad 2-to-1 data selector multiplexer
(3-State)
74F723-1
Quad 2-to-1 data selector multiplexer
with 30Ω equivalent output termination
impedance (3-State)
74F725A
Quad 3-to-1 data selector multiplexer
(3-State)
74F725-1
Quad 3-to-1 data selector multiplexer
with 30Ω equivalent output termination
impedance (3-State)
Product specification
IC15 Data Handbook
1990 Dec 13
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74F723A/74F723–1/
74F725A/74F725–1
Multiplexers
74F723A Quad 3-to-1 Data Selector Multiplexer (3-State)
74F723-1 Quad 3-to-1 Data Selector Multiplexer with 30 Equivalent Output Termination Impedance (3-State)
74F725A Quad 4-to-1 Data Selector Multiplexer
74F725-1 Quad 4-to-1 Data Selector Multiplexer with 30
Equivalent Output Termination Impedance
2
1990 Dec 13 853-1369 01257
FEATURES for 74F723A/74F723-1
•Consists of four 3-to-1 Multiplexers
•High impedance PNP base inputs for reduced loading
(20µA in High and Low states)
•Inverting or non-inverting data path capability by an inverting (INV)
input
•Designed for address multiplexing of dynamic RAM and other
applications
•Multiple side pins for V
CC
and GND to reduce lead inductance
(improves speed and noise immunity)
•3-State outputs sink 64mA (74F723A only)
•30 termination impedance on each output – 74F723-1
FEATURES for 74F725A/74F725-1
•Consists of four 4-to-1 Multiplexers
•High impedance PNP base inputs for reduced loading
(20µA in High and Low states)
•Equivalent to two 74F253s without 3-State
•Outputs sink 64mA (74F725A only)
•30 termination impedance on each output – 74F725-1
DESCRIPTION
The 74F723A/74F723-1 consist of four 3-to-1 multiplexers designed
for address multiplexing of dynamic RAMs and other multiplexing
applications. Select (S0, S1) inputs control which line is to be
selected, as defined in the Function Table for 74F723A/74F723-1.
When the invering input (INV
) is Low, the input data path is inverted.
To improve speed and noise immunity, VCC and GND side pins are
used. The 3-State outputs source 15mA and sink 64mA. The
74F723-1 is the same as 74F723A except that it has a 30
temination impedance on each output to reduce line noise and the
3-State outputs sink 5mA.
The 74F725A/74F725-1 consist of four 4-to1 multiplexers designed
for general multiplexing purpose. The select (S0, S1) inputs control
which line is to be selected, as defined in the Function Table for
74F725A/725-1. The outputs source 15mA and sink 64mA. The
74F725-1 is the same as the 74F725A except that it has a 30
termination impedance on each output to reduce line noise and the
outputs sink 5mA.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPL Y
CURRENT
(TOT AL)
74F723A 5.5ns 25mA
74F723-1 7.0ns 26mA
74F725A 5.5ns 20mA
74F725-1 6.5ns 20mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ± 10%
T
amb
= 0° C to +70°C
PKG DWG
#
20-Pin Plastic Slim N74F723AN, N74F723-1N,
DIP (300 mil)
,,
N74F725AN, N74F725-1N
SOT222-1
N74F723AD, N74F723-1D,
24-Pin Plastic SOL
,,
N74F725AD, N74F725-1D
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
TYPE PINS DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Dna, Dnb, Dnc Data inputs 1.0/0.066 20µA/40µA
74F723A/
S0, S1 Select inputs 1.0/0.033 20µA/20µA
74F723-1
OE Output Enable input 1.0/0.033 20µA/20µA
INV Output inverting input 1.0/0.033 20µA/20µA
74F723A Q0 - Q3 Data outputs for 74F723A 750/106.7 15mA/64mA
74F723-1 Q0 - Q3 Data outputs for 74F723-1 750/8.33 15mA/5mA
74F725A/
Dna, Dnb, Dnc, Dnd Data inputs 1.0/0.066 20µA/40µA
74F725-1
S0, S1 Select inputs 1.0/0.033 20µA/20µA
74F725A Q0 - Q3 Data outputs 750/106.7 15mA/64mA
74F725-1 Q0 - Q3 Data outputs 750/8.33 15mA/5mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
Philips Semiconductors Product specification
74F723A/74F723–1/
74F725A/74F725–1
Multiplexers
1990 Dec 13
3
PIN CONFIGURATION – 74F723A/74F723-1
SF01226
24
23
22
21
20
19
18
17
16
15
14
1312
10
11
9
8
7
6
5
4
3
2
1
OE
INV
D1a
D1b
V
CC
D2a
D2b
D2c
S0
S1
D0a
D0b
D0c
Q0
GND
GND
Q2
Q3
D3a
Q1
D3b
D3c
D1c
V
CC
PIN CONFIGURATION – 74F725A/74F725-1
24
23
22
21
20
19
18
17
16
15
14
1312
10
11
9
8
7
6
5
4
3
2
1
D0a
D0b
D1a
D1b
D1d
D2a
D2b
D2c
D2d
D3d
SO
S1
D0c
D0d
Q1
GND
Q2
Q3
D3a
Q0
D3b
D3c
D1c
V
CC
SF01227
LOGIC SYMBOL – 74F723A/74F723-1
13S0S1
Q1Q0
1 2 3 22212017161510
48
Q2 Q3
59
INV
14
23
V
CC
= Pin 18, 19
GND = Pin 6, 7
SF01228
24
11 12
D0a D0b D1a D1b D2a D2b D3a D3bD0c D1c D2c D3c
OE
LOGIC SYMBOL – 74F725A/74F725-1
VCC = Pin 18
GND = Pin 7
23S0S1
D0a D0b D1a D1b D2a D2b D3a
Q1Q0
1 2 3 4 22 21 20 19 17 16
55
Q2 Q3
69
D3b
24
D0c D1c D2c D3c
15 14 10 11 12
SF01229
D0d D1d D2d D3d
13
LOGIC SYMBOL (IEEE/IEC) – 74F723A/74F723-1
SF01230
MUX
G1
EN
13
23
24
2
3
22
20
17
16
1
10
15
M
4
5
8
9
21
12
11
G2
14
LOGIC SYMBOL (IEEE/IEC) – 74F725A/74F725-1
SF01231
MUX
G1
G2
24
23
2
3
4
22
21
20
1
17
19
5
6
9
8
15
14
10
11
12
16
13
Philips Semiconductors Product specification
74F723A/74F723–1/
74F725A/74F725–1
Multiplexers
1990 Dec 13
4
LOGIC DIAGRAM – 74F723A/74F723-1
24
23
14
13
1
2
3
22
21
20
17
16
15
10
11
12
OE
INV
S0
S1
D0a
D0b
D0c
D1a
D1b
D1c
D2a
D2b
D2c
D3a
D3b
D3c
Q3
Q2
Q1
Q0
4
5
8
9
V
CC
= Pin 18, 19
GND = Pin 6, 7
SF01232
FUNCTION TABLE – 74F723A/74F723-1
INPUTS OUTPUT
S0 S1 INV OE Dna Dnb Dnc Qn
L L L L Data a Data b Data c Data a
L L H L Data a Data b Data c Data a
H L L L Data a Data b Data c Data b
H L H L Data a Data b Data c Data b
X H L L Data a Data b Data c Data c
X H H L Data a Data b Data c Data c
X X X H X X X Z
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance “off” state
Philips Semiconductors Product specification
74F723A/74F723–1/
74F725A/74F725–1
Multiplexers
1990 Dec 13
5
LOGIC DIAGRAM – 74F725A/74F725-1
24
23
1
2
3
S0
S1
D0a
D0b
D0c
D1a
D1b
D1c
D2a
D2b
D2c
D3a
D3b
D3c
V
CC
= Pin 18
GND = Pin 7
SF01233
Q0
5
22
21
20
Q1
6
17
16
15
Q2
8
10
11
12
Q3
9
D3d
D2d
D1d
D0d
4
19
14
13
FUNCTION TABLE – 74F725A/74F725-1
INPUTS OUTPUT
S0 S1 Dna Dnb Dnc Dnd Qn
L L Data a Data b Data c Data d Data a
H L Data a Data b Data c Data d Data b
L H Data a Data b Data c Data d Data c
H H Data a Data b Data c Data d Data d
H = High voltage level
L = Low voltage level
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