Philips N74F670N, N74F670D Datasheet

INTEGRATED CIRCUITS

74F670

4 x 4 register file (3-State)

Product specification

1990 Jul 12

IC15 Data Handbook

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Philips Semiconductors	Product specification
4 x 4 register file (3-State)	74F670

FEATURES

•Simultaneous and Independent Read and Write operations

•Expandable to almost any word size and bit length

•3-State outputs

DESCRIPTION

The 74F670 is a 16-bit 3-State Register File organized as 4 words of 4 bits each. Separate Read and Write Address and Enable inputs are available, permitting simultaneous writing into one word location and reading from another location. The 4-bit word to be stored is presented to four data inputs.

The Write address inputs (WA and WB) determine the location of the stored word. The Write Address inputs should only be changed when the Write Enable input (WE) is High for conventional operation. When the WE is Low, the data is entered into the addressed location.

The addressed location remains transparent to the data while the WE is Low. Data supplied at the inputs will be read out in true (non-inverting) form from the 3-State outputs. Data and address inputs are inhibited when the WE is High. Direct acquisition of data stored in any of the four registers is made possible by individual Read Address inputs (RA, RB). The addressed word appears at the four outputs when the Read Enable (RE) is Low. Data outputs are in the high impedance ªoffº state when the REis High. This permits outputs to be tied together to increase the word capacity to very large numbers.

Up to 128 devices can be stacked to increase the word size to 512 locations by tying the 3-State outputs together. Since the limiting factor for expansion is the output High current, further stacking is possible by tying pullup reisistors to the outputs to increase the IOH current available. Design of the Read Enable signals for the stacked devices must ensure that there is no overlap in the Low levels which cause more than one output to be active at the same time. Parallel expansion to generate n-bit words is accomplished by driving the Enable and address inputs of each device in parallel.

PIN CONFIGURATION

D1	1		16		VCC
D2	2		15		D0
D3	3		14		WA
RB	4		13		WB
RA	5		12		WE
Q3
	6		11		RE
Q2					Q0
	7		10
GND
	8		9		Q1
		SF01178

	TYPICAL	TYPICAL
TYPE	PROPAGATION	SUPPLY CURRENT
	DELAY	(TOTAL)
74F670	6.5ns	50mA

ORDERING INFORMATION

	COMMERCIAL RANGE
DESCRIPTION	VCC = 5V ±10%,	PKG DWG #
	Tamb = 0°C to +70°C
16-pin plastic DIP	N74F670N	SOT38-4
16-pin plastic SOL	N74F670D	SOT162-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

	PINS				DESCRIPTION	74F(U.L.)	LOAD VALUE
						HIGH/LOW	HIGH/LOW
	D0 - D3				Data inputs	1.0/1.0	20μA/0.6mA
	WA, WB				Write address inputs	1.0/1.0	20μA/0.6mA
	RA, RB				Read address inputs	1.0/1.0	20μA/0.6mA
					Write Enable inputs	1.0/1.0	20mA/0.6mA
		WE
					Read Enable inputs	1.0/1.0	20mA/0.6mA
		RE
	Q0±Q3				Data output	150/40	3.0mA/24mA

NOTE:

One (1.0) FAST Unit Load is defined as: 20μA in the High state and 0.6mA in the Low state.

1990 Jul 12

2

853-0014 99965

Philips Semiconductors	Product specification
4 x 4 register file (3-State)	74F670

LOGIC SYMBOL

		14		13		5			4		15		1		2			3
		WA WB RA RB D0											D1 D2 D3
12		WE
11		RE		Q0			Q1				Q2			Q3
				10		9					7				6
VCC=Pin 16																SF01179
GND=Pin 8

LOGIC SYMBOL (IEEE/IEC)

	14		RAM 4X4
		0
				0
	13		1A
		1		3
	5	0
				0
	4		2A
		1		3
	12	C4 [WRITE]
	11
		EN [READ]
	15					10
		1A, 4D
	1					9
				2A
	2					7
	3					6

SF01180

WORD SELECT FUNCTION TABLE

	WRITE MODE				READ MODE		OPERATING MODE
	WB		WA		RB	RA	Word Selected
	L		L		L	L	Word 0
	L		H		L	H	Word 1
	H		L		H	L	Word 2
	H		H		H	H	Word 3
H	=	High voltage level
L	=	Low voltage level

READ MODE FUNCTION TABLE

	INPUT				INTERNAL	OUTPUT	OPERATING MODE
					LATCHES*
	RE					Qn
		L			L	L	Read
		L			H	H
		H			X	Z	Disabled
H	=		High voltage level
L	=		Low voltage level
X	=		Don't care
Z	=		High impedance ªoffº state

*= The selection of ªinternal latchesº by Read Address

(RA and RB) are not constrained by WE or RE operation.

WRITE MODE FUNCTION TABLE

			INPUTS				INTERNAL	OPERATING MODE
							LATCHES*
	WE				Dn
		L			L		L	Write data
		L			H		H
		H			X		NC	Data latched
H	=		High voltage level
L	=		Low voltage level
NC=			No change
X	=		Don't care

*= The write address (WA and WB) to the ªinternal latchesº must be stabled while WE is Low for conventional operation.

1990 Jul 12

3

Philips Semiconductors	Product specification
4 x 4 register file (3-State)	74F670

LOGIC DIAGRAM

RE	11
RA	5
RB	4
WE 12
WB 13
WA 14
	Q	Q	Q	Q	6
					Q3
	E	E	E	E
	D	D	D	D
D3	3
	Q	Q	Q	Q	7
					Q2
	E	E	E	E
	D	D	D	D
D2	2
	Q	Q	Q	Q	9
					Q1
	E	E	E	E
	D	D	D	D
D1	1
	Q	Q	Q	Q	10
					Q0
	E	E	E	E
	D	D	D	D
D0	15
VCC=Pin 16					SF01181
GND=Pin 8
1990 Jul 12			4