Philips N74F652AN, N74F651AD, N74F652AD, N74F651AN Datasheet

INTEGRATED CIRCUITS

74F651A/74F652A

Transceivers/registers

Product specification

1999 Jun 23

Replaces datasheet 74F651/74F652/74F651A/74F652A of 1990 Oct 23

IC15 Data Handbook

P s

on o s

Philips Semiconductors	Product specification
Transceivers/registers	74F651A/74F652A

74F651A Octal transceiver/register, inverting (3-State) 74F652A Octal transceiver/register, non-inverting (3-State)

FEATURES

•Combines 74F245 and two 74F374 type functions in one chip

•High impedance base inputs for reduced loading (70μA in high and low states)

•Independent registers for A and B buses

•Multiplexed real-time and stored data

•Choice of non-inverting and inverting data paths

•3-State outputs

•Industrial temperature range available (±40°C to +85°C) for 74F652A

DESCRIPTION

The 74F651A and 74F652A transceivers/registers consist of bus transceiver circuits with 3±State outputs, D±type flip±flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes high. Output enable (OEAB, OEBA) and select (SAB, SBA) pins are provided for bus management.

TYPE	TYPICAL fmax	TYPICAL SUPPLY CURRENT( TOTAL)
74F651/74F652	110MHz	140mA
74F651A/74F652A	175MHz	110mA

ORDERING INFORMATION

		ORDER CODE
	DESCRIPTION	COMMERCIAL RANGE	INDUSTRIAL RANGE	PKG DWG #
		VCC = 5V ±10%,	VCC = 5V ±10%,
		Tamb = 0°C to +70°C	Tamb = ±40°C to +85°C
	24±pin plastic slim DIP (300mil)	N74F651AN, N74F652AN	I74F652AN	SOT222-1
	24±pin plastic SOL	N74F651AD, N74F652AD	I74F652AD	SOT137-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS			DESCRIPTION	74F (U.L.) HIGH/LOW	LOAD VALUE HIGH/LOW
A0 ± A7, B0 ± B7			A, B inputs	3.5/0.116	70μA/70μA
CPAB, CPBA			A±to±B, B±to±A clock inputs	1.0/0.033	20μA/20μA
SAB, SBA			A±to±B, B±to±A select inputs	1.0/0.033	20μA/20μA
OEAB,			A±to±B, B±to±A output enable inputs	1.0/0.033	20μA/20μA
	OEBA
A0 ± A7, B0 ± B7			A, B outputs for N74F651, N74F652	750/106.7	15mA/64mA
A0 ± A7, B0 ± B7			A, B outputs for N74F651A, N74F652A	750/80	15mA/48mA
A0 ± A7, B0 ± B7			A, B outputs for I74F652A	750/60	15mA/36mA

Note to input and output loading and fan out table

1. One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.

1999 Jun 23

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853±1126 21852

Philips Semiconductors	Product specification
Transceivers/registers	74F651A/74F652A

PIN CONFIGURATION				LOGIC SYMBOL
		74F651A					74F651A
CPAB	1	24	VCC		4	5	6	7	8	9	10	11
SAB	2	23
			CPBA
OEAB	3	22	SBA
A0	4	21	OEBA		A0	A1	A2	A3	A4	A5	A6	A7
A1	5	20	B0	1	CPAB
A2	6	19	B1	2	SAB
				3	OEAB
A3	7	18	B2	23	CPBA
A4	8	17	B3	22	SBA
				21	OEBA
A5	9	16	B4		B0	B1	B2	B3	B4	B5	B6	B7
A6	10	15	B5
A7	11	14	B6
GND 12		13	B7		20	19	18	17	16	15	14	13
				VCC = Pin 24
		SF00401		GND = Pin 12						SF00402

	IEC/IEEE SYMBOL
		74F651A
	21	EN1 [BA]
	3	EN1 [AB]
	23	G3
	22
		G5
	1
		C6
	2
		G7
	4	1	5	20
				4D
		1	5	1
		6D	7	1
		1	7	2
	5			19
	6			18
	7			17
	8			16
	9			15
	10			14
	11			13
				SF00403

LOGIC DIAGRAM

OEBA	21		74F651A
OEAB	3
CPBA	23
SBA	22
	1
CPAB
	2
SAB
	I	of 8	channels	1D
				C1
A0	4			20
				B0
			1D
			C1
VCC = Pin 24			to 7 other	channels
GND = Pin 12				SF00404

1999 Jun 23

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Philips Semiconductors	Product specification
Transceivers/registers	74F651A/74F652A

PIN CONFIGURATION												LOGIC SYMBOL
				74F652A																74F652A
CPAB
		1					24		VCC
																4		5		6		7		8		9		10		11
SAB		2					23		CPBA
OEAB		3					22		SBA
A0		4					21		OEBA							A0		A1		A2		A3		A4		A5		A6		A7
A1		5					20		B0			1				CPAB
												2				SAB
A2		6					19		B1			3				OEAB
									B2			23				CPBA
A3		7					18
A4												22				SBA
		8					17		B3			21				OEBA
A5																B0		B1		B2		B3		B4		B5		B6		B7
		9					16		B4
A6		10					15		B5
A7
		11					14		B6							20		19		18		17		16		15		14		13
GND									B7
	12						13
												VCC = Pin 24
						SF00405						GND = Pin 12																SF00406

	IEC/IEEE SYMBOL
		74F652A
	21	EN1 [BA]
	3	EN1 [AB]
	23	G3
	22
		G5
	1
		C6
	2
		G7
		1	5	20
	4			4D
		1
			5	1
		6D	7	1
		1	7	2
	5			19
	6			18
	7			17
	8			16
	9			15
	10			14
	11			13
				SF00407

LOGIC DIAGRAM

OEBA	21		74F652A
OEAB	3
CPBA	23
SBA	22
CPAB	1
SAB	2
	I	of 8	channels	1D
				C1
A0	4			20
				B0
			1D
			C1
			to 7 other	channels
				SF00408

1999 Jun 23

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Philips Semiconductors	Product specification
Transceivers/registers	74F651A/74F652A

The following examples demonstrate the four fundamental	transferred through the device in real time. The output enable pins
bus-management functions that can be performed with the 74F651A	determine the direction of the data flow.
and 74F652A. The select pins determine whether data is stored or

BUS MANAGEMENT FUNCTIONS

REAL TIME BUS TRANSFER	REAL TIME BUS TRANSFER	STORAGE FROM	TRANSFER STORED DATA
BUS B TO BUS A	BUS A TO BUS B	A, B, OR A AND B	TO A AND/OR B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

OEAB

CPAB CPBA SAB SBA

OEAB

OEBA

CPAB CPBA SAB SBA

OEAB OEBA CPAB CPBA SAB SBA

OEAB OEBA CPAB CPBA SAB SBA

OEBA

L

L

X

X X L

H

H

X

X

L X

X

H

↑

X

X X

H

L H or L H or L H H

L

X

X

↑

X

X

L

H

↑

↑

X

X

SF00409

FUNCTION TABLE

INPUTS

DATA I/O

OPERATING MODE

OEAB

OEBA

CPAB

CPBA

SAB

SBA

An

Bn

74F651A

74F652A

L

H

H or L

H or L

X

X

Input

Input

Isolation

Isolation

L

H

↑

↑

X

X

Input

Input

Store A and B data

Store A and B data

X

H

↑

H or L

X

X

Input

Unspecified*

Store A, hold B

Store A hold B

H

H

↑

↑

L

X

Input

Output

Store A in both registers

Store A in both registers

L

X

H or L

↑

X

X

Unspecified*

Input

Hold A, store B

Hold A, store B

L

L

↑

↑

X

L

Output

Input

Store B in both registers

Store B in both registers

L

L

X

X

X

L

Output

Input

Real time

data to A bus

Real time B data to A bus

B

L

L

X

H or L

X

H

Output

Input

Stored

data to A bus

Stored B data to A bus

B

H

H

X

X

L

X

Input

Output

Real time

data to B bus

Real time A data to B bus

A

H

H

H or L

X

H

X

Input

Output

Stored

data to B bus

Stored A data to B bus

A

H

L

H or L

H or L

H

H

Output

Output

Stored

data to B bus

Stored A data to B bus

A

H

L

H or L

H or L

H

H

Output

Output

Stored

data to A bus

Stored B data to A bus

B

Notes to function table

1.

H

=

High-voltage level

2.

L

=

Low-voltage level

and OEAB inputs. Data input functions are

3.

*

=

The data output function may be enabled or disabled by various signals at the

OEBA

↑

always enabled, i.e., data at the bus pins will be stored on every low-to-high transition of the clock.

4.

=

Low-to-high clock transition

5.

X

=

Don't care

1999 Jun 23

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