N74F595N
74F595
8-bit shift register with output laches
(3-State)
Product specification
IC15 Data Handbook
1990 Apr 18
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74F5958-bit shift register with output latches (3-State)
2
1990 Apr 18 853–1096 99392
FEA TURES
•Low noise, now switching feedthrough current
•Controlled output edge rates
•High impedance PNP base inputs for reduced loading
(20µA in High and Low states)
•8-bit serial-in, parallel-out shift register with storage
•3-state outputs
•Shift register has direct clear
•Guaranteed shift frequency-DC to 100MHz
DESCRIPTION
The 74F595 contains an 8-bit serial-in, parallel-out shift register that
feeds an 8-bit D-type storage register. The storage register has
parallel 3-State outputs. Separate clocks are provided for both the
shift register and the storage register. The shift register has a direct
overriding clear, serial input and serial output pins for cascading.
Both the shift register and storage register clocks are positive
edge-triggered. If the user wishes to connect both clocks together,
the shift register state will always be one clock pulse ahead of the
storage register.
This device uses patented circuitry to control system noise and
internal ground bounce. This is done by eliminating switching
feedthrough current and controlling both Low-to-High and
High-to-Low slew rates.
PIN CONFIGURATION
16
15
14
13
12
11
107
6
5
4
3
2
1
Q7
V
CC
STCP
SHCP
SHR
OE
Q0
DS
Q1
Q2
Q6
Q3
Q4
Q5
SF01096
98GND QS
TYPE TYPICAL f
MAX
TYPICAL SUPPL Y CURRENT
(TOTAL)
74F595 130MHz 65mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
PKG DWG #
16-pin plastic DIP N74F595N SOT38-4
16-pin plastic SO N74F595D SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Ds Serial data input 1.0/0.033 20µA/20µA
SHCP Shift register clock pulse input (active rising edge) 1.0/0.033 20µA/20µA
STCP Storage register clock pulse input (active rising edge) 1.0/0.033 20µA/20µA
SHR Shift register reset input (active Low) 1.0/0.033 20µA/20µA
OE Output Enable input (active Low) 1.0/0.033 20µA/20µA
Qs Serial expansion output 50/33 1.0mA/20mA
Q0–Q7 Data outputs 150/40 3.0mA/24mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
Philips Semiconductors Product specification
74F5958-bit shift register with output latches (3-State)
1990 Apr 18
3
LOGIC SYMBOL
12
13
OE
STCP
15 1 2 3
Q0 Q1 Q2 Q3
10
11
SHCP
SHR
SF01097
V
CC
= Pin 16
GND = Pin 8
14
Ds
9
Qs
456
Q4 Q5 Q6
7
Q7
IEC/IEEE SYMBOL (IEEE/IEC)
SF01098
14
1D
EN3
C1/
13
12
10
11
2
3
4
C2
3
15
1
R
SRG8
2D
6
7
9
5
3
2D
MODE SELECT – FUNCTION TABLE
INPUTS
INTERNAL SHIFT
REGISTERS
INTERNAL STORAGE
REGISTER
OUTPUTS
OPERATING
OE SHR SHCP STCP Dn O0 O1–O7 Q0–Q7 Q0–Q7 QS
MODES
H H ↑ ↑ X O0 O1–O7 Q0–Q7 Z Q7 No Change
H L X ↑ X L0 L Q0–Q7 Z L
Clear shift
L L X ↑ X L0 L Q0–Q7 Q0–Q7 L
register, hold latch
H H ↑ ↑ ds Ds o0–o6 Q0–Q7 Z o6
L H ↑ ↑ ds Ds o0–o6 Q0–Q7 Q0–Q7 o6
Shift
H H ↑ ↑ X O0 O1–O7 o0–o7 Z Q7
L H ↑ ↑ X O0 O1–O7 o0–o7 o0–o7 Q7
Store
H H ↑ ↑ ds Ds o0–o6 o0–o7* Z o6
L H ↑ ↑ ds Ds o0–o6 o0–o7* o0–o* o6
Store
,
then
Shift
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance
dn (on)=Lower case letters indicate the state of the referenced input (or output) one setup time prior to the Low-to-High clock transition
↑ = Low-to-High clock transition
↑
= Not a Low-to-High clock transition
* = When clocking both SHCP and STCP simultaneously the Shift Register state will always be one clock pulse ahead of the Storage
Register
Philips Semiconductors Product specification
74F5958-bit shift register with output latches (3-State)
1990 Apr 18
4
LOGIC DIAGRAM
V
CC
= Pin 16
GND = Pin 8
SF01099
15
Q0
OE
STCP
SHCP
SHR
Ds
13
12
11
10
14
R
Q
CP
S
D
Q
CP
CLR
Q
1
Q1RQ
CP
S
R
Q
CP
CLR
S
Q
2
Q2RQ
CP
S
R
Q
CP
CLR
S
Q
3
Q3RQ
CP
S
R
Q
CP
CLR
S
Q
4
Q4RQ
CP
S
R
Q
CP
CLR
S
Q
5
Q5RQ
CP
S
R
Q
CP
CLR
S
Q
6
Q6RQ
CP
S
R
Q
CP
CLR
S
Q
7
Q7
RQ
CP
S
R
Q
CP
CLR
S
Q
9
Qs
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