N74F564D
74F564
Octal D flip-flop (3-State)
Product specification 1996 Jan 05
INTEGRATED CIRCUITS
IC15 Data Handbook
Philips Semiconductors Product specification
74F564Octal D flip-flop (3-State)
2
1996 Jan 05 853-0166 16189
FEA TURES
•74F564 is broadside pinout version of 74F534
•Inputs and Outputs on opposite side of package allow easy
interface to Microprocessors
•Useful as an Input or Ouput port for Microprocessors
•3-State Ouputs for Bus interfacing
•Common Output Enable
•74F574 is a non-inverting version of 74F564
DESCRIPTION
The 74F564 has a broadside pinout configuration to facilitate PC
board layout and allows easy interface with microprocessors.
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by the clock (CP) and Output Enable (OE
) control gates.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q
output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active Low Output Enable (OE
) controls all eight 3-State buffers
independently of the register operation. When OE
is Low, data in the
register appears at the outputs. When OE
is High, the outputs are in
high impedance “off” state, which means they will neither drive nor
load the bus.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20OE
GND
V
CC
CP
SF01052
Q0
D0
D1
Q
1
D2
Q
2
Q
3
D3
Q
4
D4
Q
5
D5
Q
6
D6
Q
7
D7
TYPE TYPICAL f
MAX
TYPICAL SUPPL Y
CURRENT
(TOTAL)
74F564 180MHz 50mA
ORDERING INFORMATION
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
PKG.
DWG #
20-Pin Plastic DIP N74F564N SOT146-1
20-Pin Plastic SOL N74F564D SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 - D7 Data inputs 1.0/1.0 20µA/0.6mA
OE Output Enable input (active Low) 1.0/1.0 20µA/0.6mA
CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA
Q0 - Q7 3-State outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
345678
141516171819
1
11 CP
OE
Q0
D0 D1
Q1
D2
Q2 Q3
D3
Q4
D4
Q5
D5
9
2
1213
Q6
D6
Q7
D7
SF01053
V
CC
=Pin 20
GND=Pin 10
LOGIC SYMBOL (IEEE/IEC)
1
2D
EN1
1
SF01054
11
C2
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Philips Semiconductors Product specification
74F564Octal D flip-flop (3-State)
1996 Jan 05
3
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
Q
0Q1Q2Q3Q4Q5Q6Q7
CP
OE
23456789
1213141516171819
1
11
CP
D
Q CP
D
Q CP Q
D
CP
D
Q CP
D
Q CP
D
Q CP
D
Q CP
D
Q
V
CC
=Pin 20
GND=Pin 10
SF01055
FUNCTION TABLE
INPUTS
INTERNAL
OUTPUTS
OE CP Dn
REGISTER
Q0 – Q7
OPERATING
MODES
L
L
↑
↑
l
h
L
H
H
L
Load and read register
L ↑ X NC NC Hold
H
H
↑
↑
X
Dn
NC
Dn
Z
Z
Disable outputs
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-High clock transition
↑
= Not a Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER RATING UNIT
V
CC
Supply voltage –0.5 to +7.0 V
V
IN
Input voltage –0.5 to +7.0 V
I
IN
Input current –30 to +5.0 mA
V
OUT
Voltage applied to output in High output state –0.5 to +V
CC
V
I
OUT
Current applied to output in Low output state 48 mA
T
amb
Operating free-air temperature range 0 to +70 °C
T
stg
Storage temperature –65 to +150 °C
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