INTEGRATED CIRCUITS
74F533*,74F534
Latch/flip-flop
* Discontinued part. Please see the Discontinued Product List.
Product specification |
1999 Jan 08 |
Supersedes data of 1989 May 11
IC15 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Latch/flip-flop |
74F533,* 74F534 |
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74F533 Octal Transparent Latch, Inverting (3-State)
74F534 Octal D Flip-Flop, Inverting (3-State)
FEATURES
•8-bit positive edge-triggered register ± 74F534
•3-State inverting output buffers
•Common 3-State Output register
•Independent register and 3-State buffer operation
DESCRIPTION
The 74F533 is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the Enable (E) input is High. The latch remains transparent to the data input while E is High and stores the data that is present one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in high impedance ªoffº state, which means they will neither drive nor load the bus.
The 74F534 is an 8-bit edge-triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the Clock (CP) and Output Enable (OE) control gates.
The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in high impedance ªoffº state, which means they will neither drive nor load the bus.
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TYPICAL |
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TYPICAL SUPPLY |
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CURRENT |
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PROPAGATION DELAY |
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74F533 |
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5.5ns |
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41mA |
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TYPICAL SUPPLY |
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TYPICAL fMAX |
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CURRENT |
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(TOTAL) |
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74F534 |
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165MHz |
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51mA |
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ORDERING INFORMATION |
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COMMERCIAL |
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DESCRIPTION |
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RANGE |
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PKG DWG # |
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VCC = 5V ±10%, |
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Tamb = 0°C to +70°C |
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20-Pin Plastic DIP |
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N74F534N |
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SOT146-1 |
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20-Pin Plastic SOL |
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N74F534D |
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SOT163-1 |
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INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
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PINS |
DESCRIPTION |
74F (U.L.) |
LOAD VALUE |
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HIGH/LOW |
HIGH/LOW |
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D0 - D7 |
Data inputs |
1.0/1.0 |
20μA/0.6mA |
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E (74F533) |
Enable input (active High) |
1.0/1.0 |
20μA/0.6mA |
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Output Enable input (active Low) |
1.0/1.0 |
20μA/0.6mA |
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OE |
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CP (74F534) |
Clock Pulse input (active rising edge) |
1.0/1.0 |
20μA/0.6mA |
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Data outputs |
150/40 |
3.0mA/24mA |
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Q0 - Q7 |
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* Discontinued part. Please see the Discontinued Products List. |
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1999 Jan 08 |
2 |
853-0374 20616 |
Philips Semiconductors |
Product specification |
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Latch/flip-flop |
74F533,* 74F534 |
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NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20μA in the High state and 0.6mA in the Low state.
PIN CONFIGURATION ± 74F533
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1 |
20 |
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OE |
VCC |
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2 |
19 |
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Q0 |
Q7 |
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D0 |
3 |
18 |
D7 |
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D1 |
4 |
17 |
D6 |
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5 |
16 |
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Q1 |
Q6 |
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6 |
15 |
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Q2 |
Q5 |
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D2 |
7 |
14 |
D5 |
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D3 |
8 |
13 |
D4 |
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9 |
12 |
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Q3 |
Q4 |
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GND |
10 |
11 |
E |
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SF00981 |
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PIN CONFIGURATION ± 74F534
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1 |
20 |
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OE |
VCC |
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2 |
19 |
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Q0 |
Q7 |
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D0 |
3 |
18 |
D7 |
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D1 |
4 |
17 |
D6 |
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5 |
16 |
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Q1 |
Q6 |
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6 |
15 |
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Q2 |
Q5 |
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D2 |
7 |
14 |
D5 |
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D3 |
8 |
13 |
D4 |
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9 |
12 |
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Q3 |
Q4 |
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GND |
10 |
11 |
CP |
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SF00982 |
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LOGIC SYMBOL ± 74F533
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3 |
4 |
7 |
8 |
13 |
14 |
17 |
18 |
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D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
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11 |
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E |
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1 |
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OE |
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Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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2 |
5 |
6 |
9 |
12 |
15 |
16 |
19 |
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VCC=Pin 20 |
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GND=Pin 10 |
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SF00983 |
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LOGIC SYMBOL (IEEE/IEC) ± 74F533
1 |
EN1 |
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11 |
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EN2 |
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3 |
2D |
1 |
2 |
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4 |
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9 |
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12 |
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13 |
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15 |
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16 |
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17 |
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19 |
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SF00985 |
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LOGIC SYMBOL ± 74F534
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3 |
4 |
7 |
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13 |
14 |
17 |
18 |
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D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
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11 |
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CP |
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1 |
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OE |
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Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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2 |
5 |
6 |
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12 |
15 |
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19 |
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VCC=Pin 20 |
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GND=Pin 10 |
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SF00984 |
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LOGIC SYMBOL (IEEE/IEC) ± 74F534
1 |
EN1 |
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11 |
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C1 |
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3 |
2D |
1 |
2 |
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4 |
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9 |
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12 |
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13 |
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15 |
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14 |
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16 |
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17 |
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19 |
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18 |
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SF00986 |
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* Discontinued part. Please see the Discontinued Products List. |
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1999 Jan 08 |
3 |
Philips Semiconductors |
Product specification |
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Latch/flip-flop |
74F533,* 74F534 |
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LOGIC DIAGRAM ± 74F533
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D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
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D7 |
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3 |
4 |
7 |
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13 |
14 |
17 |
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18 |
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D |
D |
D |
D |
D |
D |
D |
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D |
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E Q |
E Q |
E Q |
E Q |
E Q |
E Q |
E Q |
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E Q |
E |
11 |
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OE |
1 |
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2 |
5 |
6 |
9 |
12 |
15 |
16 |
19 |
VCC=Pin 20 |
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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GND=Pin 10 |
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SF00987 |
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LOGIC DIAGRAM ± 74F534
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D0 |
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D1 |
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D2 |
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D3 |
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D4 |
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D5 |
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D6 |
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D7 |
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3 |
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4 |
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13 |
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18 |
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D |
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D |
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D |
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D |
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D |
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D |
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D |
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D |
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CP |
Q |
CP |
Q |
CP |
Q |
CP |
Q |
CP |
Q |
CP |
Q |
CP |
Q |
CP |
Q |
CP |
11 |
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OE |
1 |
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2 |
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6 |
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9 |
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12 |
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15 |
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16 |
19 |
VCC=Pin 20 |
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Q0 |
Q1 |
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Q2 |
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Q3 |
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Q4 |
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Q5 |
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Q6 |
Q7 |
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GND=Pin 10 |
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SF00988 |
FUNCTION TABLE ± 74F533
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INPUTS |
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INTERNAL |
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OUTPUTS |
OPERATING MODES |
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OE |
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E |
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Dn |
REGISTER |
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Q0 ± Q7 |
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L |
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H |
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L |
L |
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H |
Load and read register |
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L |
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H |
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H |
H |
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L |
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L |
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↓ |
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l |
L |
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H |
Enable and read register |
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L |
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↓ |
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h |
H |
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L |
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L |
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L |
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X |
NC |
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NC |
Hold |
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H |
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L |
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X |
NC |
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Z |
Disable outputs |
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H |
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H |
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Dn |
Dn |
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Z |
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H |
= |
High voltage level |
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h |
= |
High voltage level one setup time prior to the High-to-Low E transition |
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L |
= |
Low voltage level |
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l |
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Low voltage level one setup time prior to the High-to-Low E transition |
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NC= |
No change |
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X |
= |
Don't care |
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Z |
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High impedance ªoffº state |
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↓= High-to-Low E transition
*Discontinued part. Please see the Discontinued Products List.
1999 Jan 08 |
4 |
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