Philips Semiconductors Product specification
74ALS651/74ALS651-1
74ALS652/74ALS652-1
T ransceiver/register
74ALS651/651-1 Octal transceiver/register, inverting (3-State)
74ALS652/652-1 Octal transceiver/register, non-inverting (3-State)
2
1991 Feb 08 853–1407 01670
FEA TURES
•Independent registers for A and B buses
•Multiplexed real-time and stored data
•Choice of non-inverting and inverting data paths
•3-State outputs
•The -1 versions sinks 48mA I
OL
within the ±5% VCC range
DESCRIPTION
The 74LAS651 and 74ALS652 transceivers/registers consist of bus
transceiver circuits with 3-State outputs, D-type flip-flops, and
control circuitry arranged for multiplexed transmission of data
directly from the input bus or the internal registers. Data on the A or
B bus will be clocked into the registers as the appropriate clock pin
goes High. Output enable (OEAB, OEBA
) and select (SAB, SBA)
pins are provided for bus management. The 74LAS651-1 and
74ALS652-1 will sink 48mA if the V
CC
is limited to 5.0V ± 0.25V .
TYPE
TYPICAL
f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS651/74ALS651-1 140MHz 40mA
74ALS652/74ALS652-1 140MHz 46mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
DRAWING
NUMBER
24-pin plastic DIP
74ALS651N, 74ALS651-1N,
74ALS652N, 74ALS652-1N
SOT222-1
24-pin plastic SOL
74ALS651D, 74ALS651-1D,
74ALS652D, 74ALS652-1D
SOT137-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 – A7 A inputs 1.0/1.0 70µA/0.1mA
B0 – B7 B inputs 1.0/1.0 70µA/0.1mA
CPAB A-to-B clock input 1.0/1.0 20µA/0.1mA
CPBA B-to-A clock input 1.0/1.0 20µA/0.1mA
SAB A-to-B select input 1.0/1.0 20µA/0.1mA
SBA B-to-A select input 1.0/1.0 20µA/0.1mA
OEAB A-to-B output enable input 1.0/1.0 20µA/0.1mA
OEBA B-to-A output enable input 1.0/1.0 20µA/0.1mA
A0 – A7, B0 – B7 A, B outputs 750/240 15mA/24mA
A0 – A7, B0 – B7 A, B outputs (-1 version) 750/480 15mA/48mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.