Philips N74ALS573BD, N74ALS573BN, N74ALS574ADB, N74ALS574AN Datasheet
74ALS573B/74ALS574A
Latch flip–flop
Product specification
IC05 Data Handbook
1991 Feb 08
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74ALS573B/74ALS574ALatch/flip-flop
74ALS573B Octal transparent latch (3-State)
74ALS574A Octal D flip-flop (3-State)
2
1991 Feb 08 853–1307 01670
FEA TURES
•74ALS573B is broadside pinout version of 74ALS373
•74ALS574A is broadside pinout version of 74ALS374
•Inputs and outputs on opposite side of package allow easy
interface to microprocessors
•Useful as an input or output port for microprocessors
•3-State outputs for bus interfacing
•Common output enable
•74ALS563A and 74ALS564A are inverting version of 74ALS573B
and 74ALS574A respectively
DESCRIPTION
The 74ALS573B is an octal transparent latch coupled to eight
3-State output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE
) control gates.
The 74ALS573B is functionally identical to the 74ALS373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the data that is present one setup
time before the High-to-Low enable transition.
The 74ALS574A is functionally identical to the 74ALS374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
It is an 8-bit edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by clock (CP) and output enable (OE
) control gates.
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The active-Low output enable (OE
) controls all eight 3-State buffers
independent of the latch operation. When OE
is Low, latched or
transparent data appears at the output.
When OE
is High, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
TYPE
TYPICAL
PROPAGATION
DELA Y
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS573B 5.0ns 12mA
74ALS574A 6.0ns 15mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
DRAWING
NUMBER
20-pin plastic DIP 74ALS573BN, 74ALS574AN SOT146-1
20-pin plastic SOL 74ALS573BD, 74ALS574AD SOT163-1
20-pin plastic SSOP
Type II
74ALS573BDB,
74ALS574ADB
SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 – D7 Data inputs 1.0/1.0 20µA/0.2mA
E (74ALS573B) Latch enable input 1.0/1.0 20µA/0.1mA
OE Output Enable input (active-Low) 1.0/1.0 20µA/0.1mA
CP (74ALS574A) Clock pulse input (active rising edge) 1.0/2.0 20µA/0.2mA
Q0 – Q7 Data outputs 130/240 2.6mA/24mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
Philips Semiconductors Product specification
74ALS573B/74ALS574ALatch/flip-flop
1991 Feb 08
3
PIN CONFIGURATION – 74ALS573B
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
OE
GND
V
CC
E
SF01073
Q0
D0
D1
Q1
D2
Q2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
Q7
D7
PIN CONFIGURATION – 74ALS574A
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
OE
GND
V
CC
CP
SF01074
Q0
D0
D1
Q1
D2
Q2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
Q7
D7
LOGIC SYMBOL – 74ALS573B
345678
141516171819
1
11 E
OE
Q0
D0 D1Q1D2
Q2 Q3D3Q4D4Q5
D5
9
2
1213
Q6D6Q7
D7
SF01075
VCC=Pin 20
GND=Pin 10
LOGIC SYMBOL – 74ALS574A
345678
141516171819
1
11 CP
OE
Q0
D0 D1Q1D2
Q2 Q3D3Q4D4Q5
D5
9
2
1213
Q6D6Q7
D7
SF01076
VCC=Pin 20
GND=Pin 10
IEC/IEEE SYMBOL – 74ALS573B
2D
1
SF01077
1
11
2
3
4
5
6
7
8
9
EN1
EN2
19
18
17
16
15
14
13
12
IEC/IEEE SYMBOL – 74ALS574A
2D
1
SF01078
1
11
EN1
C2
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
Philips Semiconductors Product specification
74ALS573B/74ALS574ALatch/flip-flop
1991 Feb 08
4
LOGIC DIAGRAM – 74ALS573B
V
CC
= Pin 20
GND = Pin 10
D0
D
E
Q
Q0
2
19
D1
D
E
Q
Q1
3
18
D2
D
E
Q
Q2
4
17
D3
D
E
Q
Q3
5
16
D4
D
E
Q
Q4
6
15
D5
D
E
Q
Q5
7
14
D6
D
E
Q
Q6
8
13
D7
D
E
Q
Q7
9
12
11
E
SC00109
1
OE
FUNCTION T ABLE – 74ALS573B
INPUTS
OUTPUTS
INTERNAL
OE E Dn
REGISTER
Q0 – Q7
OPERATING MODE
L H L L L
L H H H H
Enable and read register
L ↓ l L L
L ↓ h H H
Latch and read register
L L X NC NC Hold
H L X NC Z
p
H H Dn Dn Z
Disable outputs
H = High-voltage level
h = High state must be present one setup time before the High-to-Low enable transition
L = Low-voltage level
l = Low state must be present one setup time before the High-to-Low enable transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low enable transition
LOGIC DIAGRAM – 74ALS574A
VCC = Pin 20
D0
D
CP
Q
Q0
2
19
D1
D
CP
Q
Q1
3
18
D2
D
CP
Q
Q2
4
17
D3
D
CP
Q
Q3
5
16
D4
D
CP
Q
Q4
6
15
D5
D
CP
Q
Q5
7
14
D6
D
CP
Q
Q6
8
13
D7
D
CP
Q
Q7
9
12
11
OE
CP
GND = Pin 10
SC00110
1
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